SIST EN IEC 60749-26:2026

SLOVENSKI STANDARD
01-april-2026
Nadomešča:
SIST EN IEC 60749-26:2018
Polprevodniški elementi - Metode za mehansko in klimatsko preskušanje - 26. del:
Preskušanje občutljivosti na elektrostatično razelektritev (ESD) - Model
človeškega telesa (HBM) (IEC 60749-26:2025)
Semiconductor devices - Mechanical and climatic test methods - Part 26: Electrostatic
discharge (ESD) sensitivity testing - Human body model (HBM) (IEC 60749-26:2025)
Halbleiterbauelemente - Mechanische und klimatische Prüfverfahren - Teil 26: Prüfung
der Empfindlichkeit gegen elektrostatische Entladungen (ESD) - Human Body Model
(HBM) (IEC 60749-26:2025)
Dispositifs à semiconducteurs - Méthodes d'essais mécaniques et climatiques - Partie
26: Essai de sensibilité aux décharges électrostatiques (DES) - Modèle du corps humain
(HBM) (IEC 60749-26:2025)
Ta slovenski standard je istoveten z: EN IEC 60749-26:2026
ICS:
19.020 Preskuševalni pogoji in Test conditions and
postopki na splošno procedures in general
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

EUROPEAN STANDARD EN IEC 60749-26

NORME EUROPÉENNE
EUROPÄISCHE NORM February 2026
ICS 31.080.01 Supersedes EN IEC 60749-26:2018
English Version
Semiconductor devices - Mechanical and climatic test methods -
Part 26: Electrostatic discharge (ESD) sensitivity testing -
Human body model (HBM)
(IEC 60749-26:2025)
Dispositifs à semiconducteurs - Méthodes d'essais Halbleiterbauelemente - Mechanische und klimatische
mécaniques et climatiques - Partie 26: Essai de sensibilité Prüfverfahren - Teil 26: Prüfung der Empfindlichkeit gegen
aux décharges électrostatiques (DES) - Modèle du corps elektrostatische Entladungen (ESD) - Human Body Model
humain (HBM) (HBM)
(IEC 60749-26:2025) (IEC 60749-26:2025)
This European Standard was approved by CENELEC on 2026-01-27. CENELEC members are bound to comply with the CEN/CENELEC
Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration.
Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC
Management Centre or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other language made by translation
under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the
same status as the official versions.
CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic,
Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the
Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia, Slovakia, Slovenia, Spain, Sweden, Switzerland,
Türkiye and the United Kingdom.

European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
CEN-CENELEC Management Centre: Rue de la Science 23, B-1040 Brussels
© 2026 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members.
Ref. No. EN IEC 60749-26:2026 E

European foreword
The text of document 47/2963/FDIS, future edition 5 of IEC 60749-26, prepared by TC 47
"Semiconductor devices" was submitted to the IEC-CENELEC parallel vote and approved by
CENELEC as EN IEC 60749-26:2026.
The following dates are fixed:
• latest date by which the document has to be implemented at national (dop) 2027-02-28
level by publication of an identical national standard or by endorsement
• latest date by which the national standards conflicting with the (dow) 2029-02-28
document have to be withdrawn
This document supersedes EN IEC 60749-26:2018 and all of its amendments and corrigenda (if any).
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CENELEC shall not be held responsible for identifying any or all such patent rights.
Any feedback and questions on this document should be directed to the users’ national committee. A
complete listing of these bodies can be found on the CENELEC website.
Endorsement notice
The text of the International Standard IEC 60749-26:2025 was approved by CENELEC as a European
Standard without any modification.
In the official version, for Bibliography, the following notes have to be added for the standard indicated:
IEC 60749-26 NOTE Approved as EN IEC 60749-26
IEC 60749-27 NOTE Approved as EN 60749-27
IEC 60749-28 NOTE Approved as EN IEC 60749-28

IEC 60749-26 ®
Edition 5.0 2025-12
INTERNATIONAL
STANDARD
Semiconductor devices - Mechanical and climatic test methods -
Part 26: Electrostatic discharge (ESD) sensitivity testing - Human body model
(HBM)
ICS 31.080.01  ISBN 978-2-8327-0918-4

IEC 60749-26:2025-12(en)
IEC 60749-26:2025 © IEC 2025
CONTENTS
FOREWORD . 4
1 Scope . 6
2 Normative references . 6
3 Terms and definitions . 6
4 Apparatus and required equipment . 10
4.1 Waveform verification equipment . 10
4.2 Oscilloscope . 10
4.3 Additional requirements for digital oscilloscopes . 11
4.4 Current probe . 11
4.5 Evaluation loads . 11
4.6 Attenuator . 11
4.7 Human body model simulator . 12
4.8 HBM test equipment parasitic properties . 12
5 Stress test equipment qualification and routine verification . 12
5.1 Overview of required HBM tester evaluations . 12
5.2 Measurement procedures. 13
5.2.1 Reference pin pair determination . 13
5.2.2 Waveform capture with current probe . 13
5.2.3 Determination of waveform parameters . 14
5.2.4 High voltage discharge path test . 17
5.3 HBM tester qualification . 17
5.3.1 HBM ESD tester qualification requirements . 17
5.3.2 HBM tester qualification procedure . 17
5.4 Test fixture board qualification for socketed testers . 18
5.5 Routine waveform check requirements . 19
5.5.1 Standard routine waveform check description . 19
5.5.2 Waveform check frequency . 19
5.5.3 Alternate routine waveform capture procedure . 20
5.6 High voltage discharge path check . 20
5.6.1 Relay testers . 20
5.6.2 Non-relay testers . 20
5.7 Tester waveform records . 20
5.7.1 Tester and test fixture board qualification records . 20
5.7.2 Periodic waveform check records . 20
5.8 Safety . 21
5.8.1 Initial set-up. 21
5.8.2 Training . 21
5.8.3 Personnel safety . 21
6 Classification procedure . 21
6.1 Devices for classification . 21
6.2 Parametric and functional testing . 21
6.3 Device stressing . 21
6.3.1 Device stressing methods . 21
6.3.2 No connect pins . 22
6.4 Pin combination stressing . 22
6.4.1 Pin combination stressing options . 22
IEC 60749-26:2025 © IEC 2025
6.4.2 No connect pins . 23
6.4.3 Supply pins . 23
6.4.4 Non-supply pins . 24
6.5 Pin groupings . 24
6.5.1 Supply pin groups . 24
6.5.2 Partitioning supply pin groups . 24
6.5.3 Supply pins connected by package plane . 25
6.5.4 Supply pins connected by an above-passivation layer. 25
6.5.5 Shorted non-supply pin groups . 25
6.6 Pin stress combinations . 25
6.6.1 Pin stress combination categorization . 25
6.6.2 Non-supply and supply to supply combinations (1, 2, … N) . 27
6.6.3 Non-supply to non-supply combinations . 28
6.7 Pin-pair stressing . 28
6.8 Low-parasitic HBM simulator allowance . 28
6.9 Testing after stressing . 29
7 Failure criteria . 29
8 Component classification . 29
Annex A (informative) Cloned non-supply (I/O) pin sampling test method. 30
A.1 Purpose and overview . 30
A.2 Pin sampling overview and statistical details . 30
A.3 IC product selections . 31
A.4 Randomly selecting and testing cloned I/O pins . 32
A.5 Determining if sampling can be used with the Excel spreadsheet . 32
A.5.1 Using the Excel spreadsheet . 32
A.5.2 Without using the Excel spreadsheet . 32
A.6 HBM testing with a sample of cloned I/O pins . 33
A.7 Examples of testing with sampled cloned I/Os . 33
A.7.1 Example 1 . 33
A.7.2 Example 2 . 34
Annex B (informative) Determination of withstand thresholds for pin or pin-combination
subsets . 36
B.1 Overview . 36
B.2 Testing procedures . 36
B.3 Restrictions . 37
B.4 Example of using subset withstand threshold data . 37
Annex C (informative) HBM test equipment parasitic properties . 38
C.1 Optional trailing pulse detection equipment or apparatus . 38
C.2 Optional pre-pulse voltage rise detection test equipment . 40
C.3 Optional pre-HBM current spike detection equipment . 41
C.4 Open-relay tester capacitance parasitics . 43
C.5 Test to Determine if an HBM Simulator is an N-channel Low-Parasitic
Simulator . 43
Annex D (informative) HBM test method flow chart . 45
Annex E (informative) Failure window detection testing methods . 48
E.1 Methodology . 48
E.2 Combined withstand threshold method and window search . 48
E.3 Failure window detection with a known withstand threshold . 48
IEC 60749-26:2025 © IEC 2025
Bibliography . 50

Figure 1 – Simplified HBM simulator circuit with loads . 12
Figure 2 – Current waveform through shorting wires . 15
Figure 3 – Current waveform through a 500 Ω resistor . 16
Figure 4 – Peak current short circuit ringing waveform . 17
Figure A.1 – SPL, V , and V with the Bell shape distribution pin failure curve . 31
1 M
Figure A.2 – I/O sampling test method flow chart . 35
Figure C.1 – Diagram of trailing pulse measurement setup . 38
Figure C.2 – Positive stress at 4 000 V . 39
Figure C.3 – Negative stress at 4 000 V . 39
Figure C.4 – Illustration of measuring voltage before HBM pulse with a Zener diode or
a device . 40
Figure C.5 – Example of voltage rise before the HBM current pulse across a 9,4 V
Zener diode . 41
Figure C.6 – Optional pre-current pulse detection equipment or apparatus . 42
Figure C.7 – Positive stress at 1 000 V . 42
Figure C.8 – Diagram of a 10-pin shorting test device showing current probe . 44
Figure D.1 – HBM test method flow chart . 47

Table 1 – Waveform specification . 19
Table 2 – Preferred pin combinations sets . 26
Table 3 – Alternative pin combinations sets . 26
Table 4 – HBM ESD component classification levels . 29
Table B.1 – Inclusion of lower ESD level high-speed pin data ESD information for
handling of ESDS in an ESD protected area (required) . 37

IEC 60749-26:2025 © IEC 2025
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
Semiconductor devices -
Mechanical and climatic test methods -
Part 26: Electrostatic discharge (ESD) sensitivity testing -
Human body model (HBM)
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and
in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports,
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preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with
may participate in this preparatory work. International, governmental and non-governmental organizations liaising
with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for
Standardization (ISO) in accordance with conditions determined by agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence between
any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter.
5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any
services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
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expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) IEC draws attention to the possibility that the implementation of this document may involve the use of (a)
patent(s). IEC takes no position concerning the evidence, validity or applicability of any claimed patent rights in
respect thereof. As of the date of publication of this document, IEC had not received notice of (a) patent(s), which
may be required to implement this document. However, implementers are cautioned that this may not represent
the latest information, which may be obtained from the patent database available at https://patents.iec.ch. IEC
shall not be held responsible for identifying any or all such patent rights.
IEC 60749-26 has been prepared by IEC technical committee 47: Semiconductor devices in
collaboration with technical committee 101: Electrostatics. It is an International Standard.
This fifth edition cancels and replaces the fourth edition published in 2018. This edition
constitutes a technical revision. This standard is based upon ANSI/ESDA/JEDEC JS-001-2023.
It is used with permission of the copyright holders, ESD Association and JEDEC Solid state
Technology Association.
IEC 60749-26:2025 © IEC 2025
This edition includes the following significant technical changes with respect to the previous
edition:
a) new definitions have been added;
b) text has been added to clarify the designation of and allowances resulting from “low
parasitics”. The new designation includes the maximum number of pins of a device that can
pass the test procedure.
The text of this International Standard is based on the following documents:
Draft Report on voting
47/2963/FDIS 47/2984/RVD
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/publications.
A list of all parts in the IEC 60749 series, published under the general title Semiconductor
devices - Mechanical and climatic test methods, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
– reconfirmed,
– withdrawn, or
– revised.
IEC 60749-26:2025 © IEC 2025
1 Scope
This part of IEC 60749 establishes the procedure for testing, evaluating, and classifying
components and microcircuits in accordance with their susceptibility (sensitivity) to damage or
degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD).
The purpose of this document is to establish a test method that will replicate HBM failures and
provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component
type. Repeatable data will allow accurate classifications and comparisons of HBM ESD
sensitivity levels.
ESD testing of semiconductor devices is selected from this test method, the machine model
(MM) test method (see IEC 60749-27) or other ESD test methods in the IEC 60749 series.
Unless otherwise specified, this test method is the one selected.
2 Normative references
There are no normative references in this document.
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminology databases for use in standardization at the following
addresses:
– IEC Electropedia: available at https://www.electropedia.org/
– ISO Online browsing platform: available at https://www.iso.org/obp
3.1
above-passivation layer
APL
low-impedance metal plane built on the surface of a die, above the passivation layer, which
connects a group of bumps or pins
Note 1 to entry This structure is sometimes referred to as a redistribution layer (RDL). There can be multiple APLs
(sometimes referred to as islands) for a power or ground group.
Note 2 to entry: The group of bumps or pins is typically a power group or a ground group.
3.2
cloned non-supply pin
set of input, output or bidirectional pins using the same I/O cell and electrical schematic and
sharing the same associated supply pin group(s) including ESD power clamp(s)
3.3
component
item such as a resistor, diode, transistor, integrated circuit (IC) or hybrid circuit
3.4
component failure
condition in which a tested component does not meet one or more specified static or dynamic
data sheet parameters
IEC 60749-26:2025 © IEC 2025
3.5
coupled non-supply pin pair
two pins that have an intended direct current path (such as a pass gate or resistors, such as
differential amplifier inputs, or low voltage differential signalling (LVDS) pins), including
analogue and digital differential pairs and other special function pairs (e.g. D+/D−,
XTALin/XTALout, RFin/RFout, TxP/TxN, RxP/RxN, CCP_DP/CCN_DN, etc.)
3.6
data sheet parameters
static and dynamic component performance data supplied by the component manufacturer or
supplier
3.7
ESD withstand voltage
withstand threshold
highest voltage level not causing device failure with the device passing all tests performed at
lower voltage levels
Note 1 to entry: See note under ‘failure window’ definition
3.8
exposed pad
exposed metal plate on an IC package
Note 1 to entry: This metal plate can be electrically connected to the die.
3.9
feedthrough
direct or indirect (via a series resistor) connection from a pad cell layout
Note 1 to entry: This connection can allow additional elements, not included in the pad cell, to make electrical
connections to the bond pad (see Annex A).
3.10
failure window
intermediate range of stress voltages that can induce failure in a particular device type, when
the device type can pass some stress voltages both higher and lower than this range
Note 1 to entry: A component with a failure window can pass a 500 V test, fail a 1 000 V test and pass a 2 000 V
test. The withstand voltage of such a device is 500 V.
3.11
human body model electrostatic discharge
HBM ESD
ESD event meeting the waveform criteria specified in this document, approximating the
discharge from the fingertip of a typical human being to a grounded device
3.12
HBM ESD tester
HBM simulator
equipment that applies an HBM ESD to a component
3.13
I
ps
peak current value determined by the current at time t on the linear extrapolation of the
max
exponential current decay curve, based on the current waveform data over a 40 nanosecond
period beginning at t
max
SEE: Figure 2 a).
IEC 60749-26:2025 © IEC 2025
3.14
I
psmax
highest current value measured including the overshoot or ringing components due to internal
test simulator RLC parasitics
SEE: Figure 2 a).
3.15
no connect pin
package interconnection that is not electrically connected to a die
EXAMPLE Pin, bump, ball interconnection.
Note 1 to entry: There are some pins which are labelled as no connect, which are actually connected to the die and
should not be classified as a no connect pin.
3.16
non-socketed tester
HBM simulator that makes contact to the device under test (DUT) pins (or balls, lands, bumps
or die pads) with test probes rather than placing the DUT in a socket
3.17
non-supply pin
pin that is not categorized as a supply pin or no connect pin
Note 1 to entry This includes pins such as input, output, offset adjusts, compensation, clocks, controls, address,
data, Vref pins and VPP pins on EPROM memory. Most non-supply pins transmit or receive information such as
digital or analogue signals, timing, clock signals, and voltage or current reference levels.
3.18
package plane
low impedance metal layer built into an IC package connecting a group of bumps or pins
(typically power or ground)
Note 1 to entry: There can be multiple package planes (sometimes referred to as islands) for each power and
ground group.
3.19
pin
terminal, land, lead, bump, ball, or exposed pad on the package that can make an electrical
connection to the die
3.20
pre-pulse voltage
voltage occurring at the device under test (DUT) just prior to the generation of the HBM current
pulse
Note 1 to entry: See Clause C.2.
3.21
pulse generation circuit
dual polarity pulse source circuit network that produces a human body discharge current
waveform
Note 1 to entry The circuit network includes a pulse generator with its test equipment internal path up to the contact
pad of the test fixture. This circuit is also referred to as dual polarity pulse source.
3.22
ringing
high frequency oscillation superimposed on a waveform
IEC 60749-26:2025 © IEC 2025
3.23
shorted non-supply pin
any non-supply pin (typically an I/O pin) that is metallically connected (typically < 3 Ω) on the
chip or within the package to another non-supply pin (or set of non-supply pins)
3.24
socketed tester
HBM simulator that makes contact to DUT pins (or balls, lands, bumps or die pads) using a
DUT socket mounted on a test fixture board
3.25
specification limit
SPL
target specification level set by the customer's requirements or internal target
Note 1 to entry: See Annex A.
3.26
spurious current pulse
small HBM shaped pulse that follows the main current pulse, and is typically defined as a

percentage of I
psmax
3.27
step-stress hardening
ability of a component subjected to increasing ESD voltage stresses to withstand higher stress
levels than a similar component not previously stressed
EXAMPLE: A component can fail at 1 000 V if subjected to a single stress, but fail at 3 000 V if stressed
incrementally from 250 V.
3.28
supply pin
any pin that provides current to a circuit
Note 1 to entry: Supply pins typically transmit no information (such as digital or analogue signals, timing, clock
signals, and voltage or current reference levels). For the purpose of ESD testing, power and ground pins are treated
as supply pins.
3.29
terminal
output (A) or return (B) of the simulator pulse source
3.30
tester channel
path connecting the pulse source of the simulator to the DUT pin
3.31
test fixture board
specialized circuit board, with one or more component sockets, which connects the DUT(s) to
the HBM simulator
3.32
t
max
time when I is at its maximum value (I )
ps psmax
SEE: Figure 2.
IEC 60749-26:2025 © IEC 2025
3.33
trailing current pulse
current pulse that occurs after the HBM current pulse has decayed
Note 1 to entry: See Clause C.2.
Note 2 to entry: A trailing current pulse is a relatively constant current often lasting for hundreds of microseconds.
3.34
V
maximum HBM stress voltage step where all of the selected cloned non-supply pins pass
Note 1 to entry: See Annex A.
3.35
V
minimum HBM stress voltage step where all the selected cloned non-supply pins fail
Note 1 to entry: See Annex A.
3.36
V
M
minimum HBM stress voltage step where 50 % or greater of the selected cloned non-supply
pins fail
Note 1 to entry: See Annex A.
4 Apparatus and required equipment
4.1 Waveform verification equipment
All equipment used to evaluate the tester shall be calibrated in accordance with the
manufacturer's recommendation. This includes the oscilloscope, current probe and high voltage
resistor load. Maximum time between calibrations shall be one year. Calibration shall be
traceable to national or international standards.
Equipment capable of verifying the pulse waveforms defined in the test method in this document
includes, but is not limited to, an oscilloscope, evaluation loads and a current probe.
4.2 Oscilloscope
A digital oscilloscope should be preferred but analogue oscilloscopes may also be used. In
order to ensure accurate current waveform capture, the oscilloscope shall meet the following
requirements:
a) minimum sensitivity of 100 mA per major division when used in conjunction with the current
probe as specified in 4.4;
b) minimum bandwidth of 350 MHz;
c) for analogue scopes, minimum writing rate of one major division per nanosecond.
IEC 60749-26:2025 © IEC 2025
4.3 Additional requirements for digital oscilloscopes
Where a digital oscilloscope is used, the following additional requirements apply:
a) number of channels: 2 or more;
b) minimum sampling rate: 10 samples per second;
c) minimum vertical resolution: 8-bit;
d) minimum vertical accuracy: ±2,5 %;
e) minimum time base accuracy: 0,01 %;
f) minimum record length: 10 points.
4.4 Current probe
The requirements for the current probe are:
a) minimum bandwidth of 200 MHz;
b) peak pulse capability of 12 A;
c) rise time of less than 1 ns;
d) capable of accepting a solid conductor as specified in 4.5;
e) provides an output voltage per signal current as required in 4.2;
NOTE 1 This is usually between 1 mV/mA and 5 mV/mA.
f) low-frequency 3 dB point below 10 kHz (e.g. Tektronix CT-2 ) for measurement of decay
constant t (see 5.2.3.2, Table 1, and 4.4, NOTE 2).
d
NOTE 2 Results using a current probe with a low-frequency 3 dB point of 25 kHz (e.g. Tektronix CT-1 ) to
measure decay constant t are acceptable if t is found to be between 130 ns and 165 ns.
d d
4.5 Evaluation loads
Tester operation shall be checked with two evaluation loads.
2 2
a) Load 1: a solid 18 AWG to 24 AWG (non-US standard wire size 0,25 mm to 0,75 mm
cross-sectional area) tinned copper shorting wire as short as practicable to span the
distance between the two farthest pins in the socket while passing through the current probe
or long enough to pass through the current probe and contacted by the probes of the non-
socketed tester.
b) Load 2: a (500 ± 5) Ω, minimum 4 000 V voltage rating.
4.6 Attenuator
A 20,0 dB attenuator shall be used with a precision of ±0,5 dB, at least 1 GHz bandwidth, and
an impedance of (50 ± 5) Ω.
___________
Tektronix CT-1 and CT-2 are the trade names of products supplied by Tektronix, Inc. This information is given
for the convenience of users of this document and does not constitute an endorsement by IEC of the products
named. Equivalent products may be used if they can be shown to lead to the same results.
IEC 60749-26:2025 © IEC 2025
4.7 Human body model simulator
A simplified schematic of the HBM simulator or tester is given in Figure 1. The performance of
the tester is influenced by parasitic capacitance and inductance. Thus, construction of a tester
using this schematic does not guarantee that it will provide the HBM pulse required for this
document. The waveform capture procedures and requirements described in Clause 5
determine the acceptability of the equipment for use. DUT socket adapters may be stacked
(piggybacking or the insertion of secondary sockets into the main test socket) only if the
secondary socket waveform meets the requirements defined in Table 1 of this document.

Figure 1 – Simplified HBM simulator circuit with loads
NOTE 1 The current probes are specified in 4.4.
NOTE 2 The shorting wire (short) and 500 Ω resistor (R4) are evaluation loads specified in 4.5.
NOTE 3 Reversal of terminal A and terminal B is not commonly used to achieve dual polarity performance except
under the conditions described in 6.6.2.3 and 6.8.
NOTE 4 The charge removal circuit ensures a slow discharge of the device, thus avoiding the possibility of a
charged device model discharge. A simple example is a 10 kΩ or larger resistor (possibly in series with a switch) in
parallel with the test fixture board. This resistor can also be useful to control parasitic pre-pulse voltages (see
Clause C.2 and Clause C.3).
NOTE 5 The dual polarity pulse source (generator) is designed to avoid recharge transients and double pulses.
NOTE 6 Component values are nominal.
4.8 HBM test equipment parasitic properties
Some HBM simulators have been found to incorrectly classify HBM sensitivity levels due to
parasitic artifacts or uncontrolled voltages unintentionally built into the HBM simulator’s
environment. Annex C describes methods for determining if these effects are present and
optional mitigation techniques. See Clause C.5 for a procedure to determine if an HBM
simulator is considered an N-channel low-parasitic HBM simulator for a device with N pins
simultaneously connected to the simulator.
5 Stress test equipment qualification and routine verification
5.1 Overview of required HBM tester evaluations
The HBM tester and test fixture boards shall be qualified, re-qualified, and periodically verified
as described in Clause 5. A flow chart for this procedure is given in Annex D. The safety
precautions described in 5.8 shall be followed at all times.
IEC 60749-26:2025 © IEC 2025
5.2 Measurement procedures
5.2.1 Reference pin pair determination
The two pins of each socket on a test fixture board which make up the reference pin pair are:
a) the socket pin with the shortest wiring path of the test fixture to the pulse generation circuit
(terminal B), and
b) the socket pin with the longest wiring path of the test fixture from the pulse generation circuit
(terminal A) to the ESD stress socket (see Figure 1).
This information is typically provided by the equipment or test fixture board manufacturer. If
more than one pulse generation circuit is connected to a socket, then there will be more than
one reference pin pair.
On non-positive clamp fixtures, feed-through test point pads should be added on these paths
to allow connection of either the shorting wire or the 500 Ω load resistor during waveform
verification measurements. These test points should be added as close as possible to the
socket(s), and if the test fixture board uses more than one pulse generator, multiple feed-
through test points should be added for each pulse generator’s longest and shortest paths.
NOTE A positive clamp test socket is a zero insertion force (ZIF) socket with a clamping mechanism. It allows the
shorting wire to be easily clamped into the socket. Examples are dual in-line package (DIP) and pin grid array (PGA)
ZIF sockets.
5.2.2 Waveform capture with current probe
5.2.2.1 General
To capture a current waveform between two socket pins (usually the reference pin pair), use
the shorting wire (see 4.5, Load 1) for the short circuit measurement or the 500 Ω resistor
(see 4.5, Load 2) for the 500 Ω current measurement and the current probe (see 4.4).
NOTE At high stress voltages, an attenuator (4.6) can be necessary to prevent off-scale measurements on the
oscilloscope and avoid oscilloscope damage. At low stress levels, especially at the 50 V and 125 V levels, an
attenuator is not used when signal levels reach the lower limits of the oscilloscope voltage sensitivity.
5.2.2.2 Short circuit current waveform
Attach the shorting wire between the pins to be measured. Place the current probe around the
shorting wire, as close to terminal B as practical, observing the polarity shown in Figure 1. Apply
an ESD stress at the voltage and polarity required to execute the qualification, re-qualification
or periodic verification being conducted.
a) For positive clamp sockets, insert the shorting wire between the socket pins connected to
terminal A and terminal B and hold in place by closing the clamp.
b) For non-positive clamp sockets, attach the shorting wire between the socket pins connected
to terminal A and terminal B. If it is not possible to make contact within the socket, connect
the shorting wire between the reference pin pair test points or socket mounting holes, if
available. The design of the socket is important as some socket types can include contact
springs (coils) in their design. These springs can add more parasitic inductance to the signal
path and can affect the HBM waveform. Sockets that minimize the use of springs (coils)
should be selected. However, if it is not possible, their length should be kept as short as
possible.
c) For non-socketed testers, place the shorting wire with the inductive current probe on an
insulating surface and place the simulator terminal A and terminal B probes on the ends of
the wires.
IEC 60749-26:2025 © IEC 2025
5.2.2.3 500 Ω load current waveform
Place the current probe around the 500 Ω resistor’s lead, observing the polarity as shown in
Figure 1. Attach the 500 Ω resistor between the pins to be measured. The current probe shall
be placed around the wire between the resistor and terminal B. Apply an ESD stress at the
voltage and polarity required to execute the qualification, re-qualification or periodic verification
being conducted.
a) For socketed testers, follow procedures in accordance with the socket type as described in
5.2.2.2.
b) For non-socketed testers, place the test load and current probe on an insulating surface and
connect the tester’s probes to the ends of the test load.
5.2.3 Determination of waveform parameters
5.2.3.1
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