oSIST prEN IEC 60749-29:2026

SLOVENSKI STANDARD
01-marec-2026
Polprevodniški elementi - Mehanske in klimatske preskusne metode - 29. del:
Preskus zapore
Semiconductor devices - Mechanical and climatic test methods - Part 29: Latch-up test
Halbleiterbauelemente - Mechanische und klimatische Prüfverfahren - Teil 29: Latch-up-
Prüfung
Dispositifs à semiconducteurs - Méthodes d'essai mécaniques et climatiques - Partie 29:
Essai de verrouillage
Ta slovenski standard je istoveten z: prEN IEC 60749-29:2026
ICS:
19.020 Preskuševalni pogoji in Test conditions and
postopki na splošno procedures in general
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

47/2991/CDV
COMMITTEE DRAFT FOR VOTE (CDV)

PROJECT NUMBER:
IEC 60749-29 ED3
DATE OF CIRCULATION: CLOSING DATE FOR VOTING:
2026-01-30 2026-04-24
SUPERSEDES DOCUMENTS:
47/2971/RR
IEC TC 47 : SEMICONDUCTOR DEVICES
SECRETARIAT: SECRETARY:
Korea, Republic of Mr Cheolung Cha
OF INTEREST TO THE FOLLOWING COMMITTEES: HORIZONTAL FUNCTION(S):

ASPECTS CONCERNED:
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TITLE:
Semiconductor devices - Mechanical and climatic test methods - Part 29: Latch-up test

PROPOSED STABILITY DATE: 2031
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IEC CDV 60749-29 © IEC:2025
1 CONTENTS
2 Foreword . 3
3 1 Scope . 8
4 2 Normative references . 8
5 3 Terms and definitions . 9
6 4 Latch-up characterization . 14
7 4.1 General description . 14
8 4.2 Latch-up immunity . 14
9 4.3 Temperature Classification . 15
10 4.4 Overall requirement classifications . 15
11 5 Apparatus and material . 15
12 5.1 Latch-up tester . 15
13 5.1.1 Hardware Requirements and Capabilities . 15
14 5.1.2 Test Board . 16
15 5.1.3 Temperature Control. 16
16 6 Latch-up test procedure . 17
17 6.1 General Latch-Up Test Overview . 17
18 6.2 Device Handling . 19
19 6.3 Sample Size . 19
20 6.4 Preparation of the Latch-Up Test . 19
21 6.4.1 Pin Types and Grouping . 19
22 6.4.2 Power Supply Assignments . 20
23 6.4.3 Product Pre-Conditioning . 21
24 6.4.4 Device Temperature Set-Up . 21
25 6.5 Latch-Up Detection Criteria . 21
26 6.5.1 Latch-Up Detection . 21
27 6.5.2 Power Supply Current Limits . 22
28 6.6 Signal Pin Test . 23
29 6.6.1 Signal Pin Test Flow . 23
30 6.6.2 Waveforms for the Positive Signal Pin Tests . 25
31 6.6.3 Waveforms for the negative signal pin test – I Test / E Test . 28
32 6.7 Supply Test . 31
33 6.7.1 Supply Test Flow . 31
34 6.7.2 Waveforms for the Supply Test . 33
35 6.8 Functional and parametric test after latch-up stress. 34
36 6.9 Failure analysis . 34
37 6.10 DUR disposition . 35
38 7 Report requirements . 35
39 7.1 Report normatives . 35
40 Annex A (informative) Special pins . 36
41 A.1 Purpose . 36
42 A.2 Pins creating latch-up challenges . 36
43 A.3 Definition of special pins . 37
44 A.4 Special pin guidance . 37
45 Annex B (informative) Calculations for junction, ambient or case temperature . 48
IEC CDV 60749-29 © IEC:2025
46 B.1 Calculating operating ambient temperature T or T from one known
a j
47 temperature . 48
48 B.2 Calculating operating case temperature T c or Tj from one known temperature . 49
49 B.3 Temperature monitoring and control equipment . 49
50 B.4 Device temperature control . 50
51 B.4.1 Temperature control methodology . 50
52 B.4.2 Class II testing . 50
53 B.4.3 Tjmax determination . 51
54 Annex C (informative) Equivalent circuits for latch-up testing . 52
55 Annex D (informative) Reporting data examples . 56
56 Annex E (informative) Determining MSV . 57
57 Annex F (Informative) Pulse Source Verification . 62
58 F.1 Introduction . 62
59 F.2 Verification test setup . 62
60 F.3 Standard pulse . 63
61 F.4 I-Test . 63
62 F.5 E-Test and supply test . 65
63 F.6 Specialized pulse source verification . 67
64 F.7 Sample pulse measurements . 67
65 Annex G (Informative) Signal pin test – I-Test vs E-Test – How to decide which is best . 70
66 Annex H (Informative) Controlling pin under test during pre- and post-stress . 71
68 Figure 1 – General Latch-Up Test Flow for the Signal Pin Test and Supply Tests. . 18
69 Figure 2 – Signal pin test flow example: positive current stress with input pins biased
70 to low (VminOP). Also applicable to VmaxOP. . 24
71 Figure 1 – Test waveform for positive signal pin test (I Test) . 26
72 Figure 5 – Test waveform for negative signal pin test (I Test) . 29
73 Figure 6 – Test waveform for negative signal pin test (E Test) . 30
74 Figure 7 – Supply test flow example: power supply stress with input pins biased to low
75 (VminOP) and to high (VmaxOP) . 32
76 Figure 8 — Test waveform for the supply test . 33
77 Figure 9 – Pins connected through passive components . 38
78 Figure 10 – Differential Inputs: Op Amp inputs, clock oscillators, comparators . 39
79 Figure 11 – Inputs, Outputs, IOs powered by internal power domain . 39
80 Figure 12 – Input / Output Pair with an Inverter in-between . 39
81 Figure 13 – Pins with digital and/or analog circuits multiplexed . 40
82 Figure 14 – RF pins with direct connection to ground . 40
83 Figure 15 – Temperature sensing diode pins. 40
84 Figure 17 – Voltage and current reference pins . 41
85 Figure 18 – Voltage monitor and sense pins . 41
86 Figure 19 – Current sense pins . 41
87 Figure 20 – DC voltage regulators . 42
88 Figure 21 – Switched voltage regulators . 43
89 Figure 22 – Circuits with multiple supply sources . 43
90 Figure 23 – Non-volatile programming pins . 44
IEC CDV 60749-29 © IEC:2025
91 Figure 24 – Power supplies with specific relationships . 44
92 Figure 25 – Example 1: Complex microcontroller . 44
93 Figure 26 – Example 1: as used in a typical application . 45
94 Figure 27 – Example 2: Differential comparator . 45
95 Figure 28 – Example 3: Non-integrated regulator . 46
96 Figure 29 – Example 4: Integrated regulator . 47
97 Figure 30 – Equivalent circuit for positive current pulse signal pin test latch-up testing . 52
98 Figure 31 – Equivalent circuit for positive voltage pulse signal pin test latch-up testing . 53
99 Figure 32 – Equivalent circuit for negative current pulse signal pin test latch-up testing . 54
100 Figure 33 – Equivalent circuit for negative voltage pulse signal pin test latch-up testing . 54
101 Figure 34 — Equivalent circuit for supply test latch-up testing . 55
102 Figure 35 – Electrical stress chart for latch-up stress and MSV . 58
103 Figure 36 --- Verification test set-up . 63
104 Figure 37 – Comparison of 2 pulses intended to create a 100 mA pulse Through a 20
105 Ohm resistor . 68
106 Figure 38 – Comparison of 3 pulses intended to create a 100 mA pulse through a 1 kΩ
107 resistor . 69
108 Figure 39 – Pre-stress and post-stress current and voltage control . 71
110 Table 1 – Latch-up immunity levels . 14
111 Table 2 – Overview of latch-up tests for a complete latch-up characterization . 19
112 Table 3 – Latch-Up Detection Criteria . 21
113 Table 4 – Pulse current and voltage requirements for the positive signal pin test . 27
114 Table 5 – Timing Requirements for the Signal Pin Test and the Supply Test . 28
115 Table 6 – Pulse current and voltage requirements for the negative signal pin test . 30
116 Table 7 – Pulse current and voltage requirements for the supply test . 34
117 Table 8 – DC regulator cross references . 41
118 Table 9 – Samples of verification resistor values for positive I Test pulse verification
119 for different technologies being tested . 64
120 Table 10 – Samples of verification resistor values for negative I Test pulse verification
121 for different technologies being tested . 65
122 Table 11 – Samples of verification resistor values for positive E Test pulse verification
123 for different technologies being tested . 66
124 Table 12 – Samples of verification resistor values for negative E Test pulse verification
125 for different technologies being tested . 66
126 Table 15 – Example 1(b) Pre-stress conditions . 72
127 Table 16 – Example 1(b) Post-stress conditions. 72
128 Table 17 – Example 2 Pre-stress conditions . 73
129 Table 18 – Example 2 Pre-stress conditions . 73
IEC CDV 60749-29 © IEC:2025
132 INTERNATIONAL ELECTROTECHNICAL COMMISSION
133 ___________
135 SEMICONDUCTOR DEVICES –
136 MECHANICAL AND CLIMATIC TEST METHODS –
138 Part 29: Latch-up test
141 FOREWORD
142 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
143 all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
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152 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
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172 8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
173 indispensable for the correct application of this publication.
174 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
175 patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
176 International Standard IEC 60749-29 has been prepared by IEC technical committee 47:
177 Semiconductor devices.
178 This fourth edition cancels and replaces the third edition published in 2010. This edition
179 constitutes a full technical revision. This standard is based upon JEDEC JESD78F.02. It is
180 used with permission of the copyright holder, JEDEC Solid state Technology Association.
181 The significant changes with respect to the previous edition include:
182 a) Extensive technical changes to definitions, test methods and classifications;
183 b) Fully revised annexes covering the testing of pins, voltage domain descriptions and
184 statistics of testing coverage.
IEC CDV 60749-29 © IEC:2025
186 The text of this standard is based on the following documents:
FDIS Report on voting
47/2083/FDIS 47/2090/RVD
188 Full information on the voting for the approval of this standard can be found in the report on
189 voting indicated in the above table.
190 The language used for the development of this International Standard is English.
191 This document has been drafted in accordance with the ISO/IEC Directives, Part 2, and
192 developed in accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC
193 Supplement, available at www.iec.ch/members_experts/refdocs. The main document types
194 developed by IEC are described in greater detail at www.iec.ch/publications.
195 The committee has decided that the contents of this document will remain unchanged until the
196 stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
197 the specific document. At this date, the document will be
198 • reconfirmed,
199 • withdrawn,
200 • replaced by a revised edition, or
201 • amended.
IEC CDV 60749-29 © IEC:2025
203 INTRODUCTION
204 For almost three decades, characterization of the latch-up sensitivity as per JEDEC’s JESD78
205 and the IEC 60749-29 harmonized specification, or its predecessor JESD17, have been the
206 industry accepted qualification test for integrated circuits (ICs) and semiconductor devices.
207 Achieving the application related level of latch-up immunity has been shown minimize No
208 Trouble Found (NTF) and Electrically Induced Physical Damage (EIPD) failures due to latch-
209 up. The actual version of IEC60749-29 has been completely rewritten and updated to include
210 contemporary state of the art testing and classification.
211 Latch-up is a state in the device whereby voltage and current outside of normal conditions
212 triggers a high current, low impedance in the device that is not related to normal functionality,
213 and which does not end without removing power from the system. Latch-up may or may not
214 cause physical damage. The document establishes tests for latch-up sensitive structures with
215 two test types, overvoltage on supply pins and current injection into signal pins. Current
216 injection is achieved either by current forcing with voltage compliance limit (I Test) or by
217 applying voltage with current compliance limit (E Test)
218 As device technologies and products have evolved; product design is more complex and
219 functionality is more varied. This specification edition has been revised to address the
220 complexity of the devices and product and improve the characterization methods. An example
221 of such an adjustment is the introduction of the concept of the maximum stress voltage (MSV)
222 to enable latch-up characterization differentiate between EIPD latch-up damage and non-
223 latch-up damage.
224 Latch-up testing has become an increasingly complex task, often requiring experienced
225 engineering assessment and support. Due to actual and current device complexity many
226 devices have individual pins that cannot be characterized unambiguously as either inputs,
227 outputs, or supply pins. Each pin type requires special consideration to determine whether a
228 voltage test or a current injection test is required. Some pin types require unique pre-
229 configuration or special data assessment methods to properly perform latch-up testing as will
230 now be included in this document.
231 Some large changes include the extension of the term “latch-up” itself. Historically, latch-up
232 was restricted to the triggering of a parasitic thyristor structure (PNPN), but there are also
233 other structures within an integrated circuit that can cause a similar low impedance path when
234 triggered. The effects of the low impedance path created by these other structures are
235 indistinguishable from the effects of a triggered parasitic thyristor are just as detrimental to
236 system performance from a customer perspective,
237 Similarly, the definition of the triggered structure was extended to an ESD protection device or
238 any structure that, once triggered, will cause higher than normal currents to flow between
239 power and ground, for example, bipolar transistors. Note that current increase by a change of
240 a functional state is still not considered as latch-up.
241 Amongst other changes, the classification of special pins is clarified by introducing a "decision
242 flow" to evaluate many special pin types such as voltage reference pins, signal pins (formerly
243 called I/O pins) with LDO's and voltage/current sensing pins.
244 Updated definitions for pre-conditioning of the device-under-test (DUT), the latch-up stress
245 pulse, the detection of latch-up, and the failure criteria are included. Also defined are two
246 different types of latch-up stresses, an overvoltage test applied to supply pins (in this
247 document referred to as Supply Test) and a current injection test applied to signal pins
248 (Signal Pin Test). The Signal Pin Test can be performed either as a test with a current stress
249 pulse (known in prior revisions as I Test) or with a voltage stress pulse (known as E Test in
250 AEC-Q100-004-Rev-D). The possibility of using an E Test instead of an I Test for the current
251 injection to a signal pad is new in this revision, although, in reality, the originally defined I
252 Test was often performed as an E Test. Current injection in the Signal Pin Test is achieved
IEC CDV 60749-29 © IEC:2025
253 either by forcing current with voltage compliance limit (I Test) or by applying voltage with
254 current compliance limit (E Test). As the current injection test to signal pins can be performed
255 as I Test or E Test, the terminology of this current injection test was changed to Signal Pin
256 Test.
257 As an explicit distinction; this revision does not cover transient-induced latch-up (also known
258 as “Transient Latch-up, TLU”) which is covered in ANSI/SP5.4.1-2017. Although the
259 characterization method is in many ways similar, the purpose of this document serves as a
260 qualification standard, while transient-induced latch-up is currently a pure characterization
261 methodology of some pins specifically exposed or endangered, with no specified immunity
262 levels. To distinguish between TLU and “static” IEC60749-29 latch-up, the rise time of the
263 overstress causing latch-up in this document shall be longer than one microsecond.
IEC CDV 60749-29 © IEC:2025
265 SEMICONDUCTOR DEVICES –
266 MECHANICAL AND CLIMATIC TEST METHODS –
268 Part 29: Latch-up test
272 1 Scope
273 The objective and scope of this document is to establish test methods that replicate latch-up
274 failures during device operation while providing reliable, repeatable latch-up test results from
275 tester to tester, notwithstanding of device type. This part of IEC 60749-29 establishes the
276 procedure for testing, evaluation and classification of devices and microcircuits according to
277 their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch -up
278 stress. The document will also provide guidelines to allow the user to apply engineering
279 judgement when historical testing methods are not compatible with the integrated circuit’s
280 functionality.
281 This document applies to a current-injection test (Signal Pin Test) and an overvoltage test
282 (Supply Test). Current injection is achieved either by current forcing with voltage compliance
283 limit (I Test) or by applying voltage with current compliance limit (E Test).
284 This document will only consider direct current injection into and out of a signal pin (formerly
285 called I/O pin), and overvoltage on the power supply pins. Transient induced latch -up will not
286 be addressed. A transient-induced latch-up characterization methodology is defined in the
287 ANSI/ESD Standard Practice SP5.4.1-2017 “Latch-up Sensitivity Testing of CMOS/BiCMOS
288 Integrated Circuits – Transient Latch-up Testing, Device Level”.
289 Latch-up failures are limited to the detection of a sustained low-impedance path resulting from
290 an applied trigger condition. Other types of potential functional failures, including logic state
291 changes and spurious resets, are not considered by this document, and are not considered
292 latch-up failures.
293 All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices,
294 optoelectronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs)
295 containing any of these devices are evaluated according to this document. This test method
296 is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these
297 technologies including some Silicon-On-Insulator (SOI).
298 Transient induced latch-up is not considered; therefore, this document only considers direct
299 current injection into and out of a signal pin (formerly called I/O pin), and overvoltage on the
300 power supply pins. A transient-induced latch-up characterization methodology is defined in
301 the ANSI/ESD Standard Practice SP5.4.1-2017 “Latch-up Sensitivity Testing of
302 CMOS/BiCMOS Integrated Circuits – Transient Latch-up Testing, Device Level”.
303 Latch-up failures are limited to the detection of a sustained low-impedance path resulting from
304 an applied trigger condition. Other types of potential functional failures, including logic state
305 changes and spurious resets, are not considered by this document, and are not considered
306 latch-up failures.
307 2 Normative references
308 There are no normative references is in this document.
IEC CDV 60749-29 © IEC:2025
309 3 Terms and definitions
310 For the purposes of this document, the terms and definitions given in JEDEC JESD78 and the
311 following apply.
312 ISO and IEC maintain terminology databases for use in standardization at the following
313 addresses:
314 • ISO Online browsing platform: available at https://www.iso.org/obp
315 • IEC Electropedia: available at https://www.electropedia.org
316 3.1
317 cool-down time
318 the period of time after the post pulse measurement and before the next application of stress.
319 3.2
320 current limit
321 I
limit
322 the value of the current limit for the power supplies and pulse sources for both the Signal Pin
323 Test and Supply Test.
324 Note 1 to entry: The I is sometimes referred to as the current compliance on a power supply.
limit
325 3.3
326 current supply
327 Isupply
328 the total supply current in each V pin (or pin group) with the DUT biased.
supply
329 3.4
330 current test
331 I-test
332 a signal pin test, SPT, method using positive and/or negative current trigger pulses with a
333 voltage compliance, as an alternative to E Test, to evaluate latch-up sensitivity of an input or
334 3.5
335 device under test
336 DUT
337 the device under test
338 3.6
339 dynamic pin
340 the pin or set of pins that experience a varying voltage or current during stress to other pins,
341 for example, clock pins, crystal pins, etc.
342 Note 1 to entry: Only one note for term 2 – still needs to be numbered.A dynamic device has dynamic pin(s).
343 3.7 E-test
344 a Signal Pin Test method using positive and/or negative voltage trigger pulses with a current
345 compliance, as an alternative to I Test, to evaluate latch-up sensitivity of an input or an output
346 of a device.
347 3.8
348 electrically induced physical damage
349 EIPD
350 the damage to an integrated circuit due to electrical/thermal stress beyond the level which the
351 materials could sustain. This would include melting of silicon, fusing of metal interconnects,
IEC CDV 60749-29 © IEC:2025
352 thermal damage to package material, fusing of bond wires and other damage caused by
353 excess current or voltage. (Ref: JEDEC JEP174)
354 Note 1 to entry: Refer to JEDEC JEP174 for detailed guidance on excess current
355 3.9
356 ground
357 GND
358 the common or zero-potential pin(s) of the DUT
359 NOTE 1 Ground pins are not latch-up tested.
360 NOTE 2 A ground pin is sometimes called V . In some cases, there can be multiple V pins, in which case these
SS
ss
361 pins can be referenced to a common ground.
362 3.10
363 input pins
364 the subgroup of signal pins that is designed or can be configured to receive an external signal
365 during latch-up testing. Examples of DUT pins that are typically defined as input pins for
366 latch-up testing are address, data-in, control, clock, or similar pins.
367 Note 1 to entry: An input pin gets tied to a specific logic-low voltage level (V ) or a specific logic-high voltage
minOP
368 level (V ) during latch-up testing.
maxOP
369 Note 2 to entry: Input pins are typically in a high-impedance state. There may be exceptions, for example, high-
370 speed input pins with on-chip impedance matching/termination or input pins that have a weak-pull function enabled.
371 Note 3 to entry: Pins defined in a datasheet as bi-directional (I/O) pins would also be defined as input pins for
372 latch-up testing if they can be configured to receive an input signal.
373 Note 4 to entry: This definition reflects the usage within this latch-up test specification. Datasheets may use a
374 different definition of input pins focusing on actual system applications
375 3.11
376 latch-up
377 a sustained high-current event within an integrated circuit caused by the triggering of any
378 structure resulting in a sustained low impedance path that persists even after the removal of
379 the triggering condition.
380 Note 1 to entry: Examples of structures causing latch-up include thyristors (PNPN), BJTs (PNP or NPN) and
381 similar structures that are either of a parasitic nature or part of the electrical protection structures. Other structures
382 causing latch-up include active ESD clamp circuits that remain in a triggered condition. Most changes in a
383 functional state related to normal chip operation (for example switching of power modes due to the triggering
384 condition) are not considered latch-up.
385 Note 2 to entry: The classical definition of latch-up explicitly refers to a parasitic thyristor (PNPN), whereas this
386 specification document uses a more generic definition to include other latching structures that can be identified by
387 the described test method.
388 Note 3 to entry: Latch-up typically occurs between power and ground, but could also involve signal pins as
389 described in Annex H.
390 Note 4 to entry: The applied triggering condition can be a voltage or current impulse, an excessive rate of change
391 of current or voltage, or any other abnormal condition that causes latch-up.
392 3.12
393 latch-up immunity
394 the ability of an integrated circuit to resist any impulses of current or voltage that might create
395 a latch-up condition.
396 3.13
397 logic-high
398 the valid voltage level within the more positive (less-negative) of the two ranges of logic levels
399 chosen representing the logic states during setting high and low levels.
IEC CDV 60749-29 © IEC:2025
400 3.14
401 logic low
402 the valid voltage level within the more negative (less positive) of the two ranges of logic levels
403 chosen to represent the logic states during setting high and low levels.
404 3.15
405 maximum stress voltage
406 MSV
407 the maximum voltage (duration dependent) allowed to be placed on a given pin during latch -
408 up immunity testing without causing irreversible damage to the device from a permanent
409 physical breakdown of the silicon device or circuit not caused by latch -up.
410 Note 1 to entry: A positive MSV is higher than the maximum operating voltage and a negative MSV is lower than
411 the minimum operating voltage.
412 Note 2 to entry: MSV is NOT the same as the absolute maximum voltage rating (AMR) from the device datasheet.
413 MSV applies to latch-up testing only, protecting the DUT from physical damage from stress mechanisms not
414 directly related to latch-up. An example of an unrelated stress is one exceeding the destructive breakdown voltage
415 of a pin resulting in non-latch-up induced catastrophic breakdown of the silicon device/circuit.
416 Note 3 to entry: MSV may be different for each pin and each polarity during testing, depending on process
417 technology and circuit topology. In many medium and high voltage designs, MSV is very rarely the same value as
418 AMR.
419 Note 4 to entry: The MSV value depends on the pulse width used during latch-up testing. Shorter pulse widths
420 may allow a higher value for MSV. Therefore, the MSV value chosen should consider the pulse width as well as
421 process technology and circuit topology.
422 3.16
423 no connect pin
424 the pin(s) that have no internal electrical connection to the die.
425 Note 1 to entry: All “no connect” pins are to be left in an open (floating) state and should not be stressed during
426 latch up testing.
427 3.17
428 nominal supply current
429 I (I )
supply nom
430 the measured dc supply current for each V supply pin (or pin group) with the DUT biased at the
431 maximum operating conditions.
432 3.18
433 output pins
434 the subgroup of signal pins that are not configured to receive an external signal during latch -
435 up testing because they drive out a signal or a voltage level.
436 Note 1 to entry: Output pins, though left in an open (floating) state during testing of other pin types, should be
437 latch-up tested.
438 Note 2 to entry: Output pins are typically in a low-impedance state.
439 Note 3 to entry: This definition reflects the usage within this latch-up test specification. Datasheets may use a
440 different definition of output pins focusing on actual system applications
441 3.19
442 preconditioned pin
443 a device pin that has been placed in a defined state or condition by applying static or dynamic
444 control signals to the DUT or biasing the appropriate steady state control pin(s) in order to put
445 the device into a known, controlled and stable state.
IEC CDV 60749-29 © IEC:2025
446 3.20
447 preconditioning vectors
448 a series of commands sent to an integrated circuit instructing the circuit to perform a specified
449 series of functions or place it into a known state.
450 3.21
451 pre-stress / post-stress current
452 I / I
psPRE psPOST
453 the pulse supply current corresponding to the signal pin test or supply test before (pre -stress)
454 & after (post-stress) pulse application.
455 Note 1 to entry: I & I can either be a forced value or the limit value depending on the mode of the
psPRE psPOST
456 source (I-Test or E-Test).
457 Note 2 to entry: It is also known as parking current in some commercial systems.
458 3.22
459 pre-stress / post-stress voltage
460 V / V
psPRE psPOST
461 the pulse supply voltage corresponding to the Signal Pin Test or Supply Test before (pre -
462 stress) & after (post-stress) pulse application. It is not dependent on polarity.
463 Note 1 to entry: VpsPRE & VpsPOST can either be a forced value or the limit value depending on the mode of the
464 source (I-Test or E-Test).
465 Note 2 to entry: VpsPRE & VpsPOST are typically either VmaxOP or VminOP for these systems.
466 Note 3 to entry: It is also known as parking voltage in some commercial systems.
467 3.23
468 pin under test
469 PUT
470 the pin under test
471 3.24
472 signal pins
473 the device pins that carry an electrical signal (information) during stable operation of the
474 device and are not used as supply pins.
475 3.25
476 signal pin test
477 a test that injects positive and negative current pulses to the pin under test (PUT) by either
478 injecting a current pulse (I Test) with a voltage limit or injecting a voltage pulse (E Test) with a
479 current limit.
480 3.26
481 steady state control pins
482 the pins used to place the DUT in the desired configuration (IO configuration pins, reset,
483 power good/OK, enable, other control pins) whose logic or bias state remains constant for the
484 duration of the test.
485 Note 1 to entry: Steady state control pins, though remaining in a constant state, may still be latch -up tested with a
486 stress pulse polarity that does not alter their logic state.
487 3.27
488 supply test
489 a latch-up test that supplies overvoltage pulses to the supply pin (or pin group) under test.
490 Note 1 to entry: Previously V overvoltage test
supply
IEC CDV 60749-29 © IEC:2025
491 3.28
492 temperature, maximum operating junction
493 Tjmax
494 the maximum junction temperature of a device to operate within its specifications, as listed in
495 its data sheet and to avoid damage (latent or otherwise).
496 Note 1 to entry: Frequently specified by device manufacturers for a specific device and/or technology.
497 3.29
498 temperature, junction
499 Tj
500 the temperature of a semiconductor junction in a device.
501 3.30
502 temperature, ambient
503 Ta
504 the local air temperature surrounding the device, in an environment controlled only by natural
505 air convection and not materially affected by reflective and radiant surfaces.
506 3.31
507 temperature, c
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