IEC TS 62878-2-10:2024
(Main)Device embedding assembly technology - Part 2-10: Design specification for cavity substrate
Device embedding assembly technology - Part 2-10: Design specification for cavity substrate
IEC TS 62878-2-10:2024 provides a general specification for the design of cavity substrates.
General Information
- Status
- Published
- Publication Date
- 30-Jan-2024
- Technical Committee
- TC 91 - Electronics assembly technology
- Drafting Committee
- WG 6 - TC 91/WG 6
- Current Stage
- PPUB - Publication issued
- Start Date
- 31-Jan-2024
- Completion Date
- 16-Feb-2024
Overview
IEC TS 62878-2-10:2024 is a critical Technical Specification developed by the International Electrotechnical Commission (IEC) that focuses on the design specification for cavity substrates in device embedding assembly technology. As part of the IEC 62878 series, this document provides a comprehensive framework for designing cavity substrates used in System in Package (SiP) applications. It addresses the increasing industry demands for smaller form factor packages, particularly by enabling reduced thickness in embedded device packages while maintaining cost-effectiveness and reliable assembly processes.
This standard is essential for professionals engaged in electronic assembly and printed board design, offering guidance on the structural and dimensional parameters of cavity substrates, including cavity formation methods and design rules.
Key Topics
- Cavity Substrate Design Principles: Establishes general specifications for cavity substrate dimensions and geometry necessary for optimizing embedded device assembly.
- Cavity Formation Methods: Details three primary types of cavity formation:
- Milling type: Creates deep cavities through mechanical milling.
- Etching type: Produces isotropic, shallow cavities by chemical etching of dielectric materials.
- Laser type: Utilizes laser cutting and detachment for shallow cavity fabrication.
- Design Guidelines: Defines critical design parameters such as:
- Top and bottom cavity sizes (A and B)
- Cavity wall proximity to internal patterns (C)
- Cavity opening clearances to solder resist and inner layers (D and E)
- Cavity taper and depth (F and G)
- Drawing Designators: Specifies standardized designator codes for easy identification of cavity substrate features, enhancing communication and documentation accuracy.
- Examples and Visuals: Includes schematic representations and practical cavity formation examples for both etching and laser types to aid understanding and implementation.
Applications
IEC TS 62878-2-10:2024 is instrumental in the design and manufacture of advanced electronic packages, particularly where embedding devices reduce overall package thickness and improve integration density. Key applications include:
- System in Package (SiP) Solutions: Supports faster development cycles and cost reduction in small form factor electronic modules that require embedded components.
- Wafer-Level Package (WLP) and Panel-Level Package (PLP) Manufacturing: Serves as a design foundation for cavity substrates catering to ultra-thin packaging needs.
- Embedded Component Assembly: Enables reliable substrate design that improves embedding processes, thus enhancing device performance and assembly yield.
- Printed Circuit Board (PCB) Technology: Provides integrated requirements to PCB manufacturers to ensure compliance with state-of-the-art embedding technologies.
Related Standards
To fully apply IEC TS 62878-2-10:2024, the following standards are pertinent:
- IEC 60194-2 – Printed boards design, manufacture and assembly – Vocabulary relevant to electronic technologies and assembly, ensuring consistent terminology and comprehension.
- IEC 62878 Series – Covers other parts of device embedding assembly technology essential for holistic design and production practices.
- ISO/IEC Directives – Provide overarching guidelines for standard development and document presentation aligned with this technical specification.
Practical Value
By implementing IEC TS 62878-2-10:2024, manufacturers and design engineers can achieve:
- Optimized cavity substrate designs that meet modern electronic packaging demands.
- Enhanced cost-efficiency by selecting appropriate cavity formation techniques tailored to thin package development.
- Increased reliability and reproducibility in embedding assembly through standardized design schemes.
- Reduced product form factor, enabling more compact and high-performance electronic devices.
- Seamless collaboration and communication across international manufacturing and design teams, thanks to standardized designators and terminology.
IEC TS 62878-2-10:2024 empowers the electronics industry to meet evolving packaging challenges, ensuring that cavity substrate design supports future-ready embedded device assembly technologies.
Frequently Asked Questions
IEC TS 62878-2-10:2024 is a technical specification published by the International Electrotechnical Commission (IEC). Its full title is "Device embedding assembly technology - Part 2-10: Design specification for cavity substrate". This standard covers: IEC TS 62878-2-10:2024 provides a general specification for the design of cavity substrates.
IEC TS 62878-2-10:2024 provides a general specification for the design of cavity substrates.
IEC TS 62878-2-10:2024 is classified under the following ICS (International Classification for Standards) categories: 31.180 - Printed circuits and boards; 31.190 - Electronic component assemblies. The ICS classification helps identify the subject area and facilitates finding related standards.
IEC TS 62878-2-10:2024 is available in PDF format for immediate download after purchase. The document can be added to your cart and obtained through the secure checkout process. Digital delivery ensures instant access to the complete standard document.
Standards Content (Sample)
IEC TS 62878-2-10 ®
Edition 1.0 2024-01
TECHNICAL
SPECIFICATION
colour
inside
Device embedding assembly technology –
Part 2-10: Design specification for cavity substrate
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IEC TS 62878-2-10 ®
Edition 1.0 2024-01
TECHNICAL
SPECIFICATION
colour
inside
Device embedding assembly technology –
Part 2-10: Design specification for cavity substrate
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 31.180; 31.190 ISBN 978-2-8322-8165-9
– 2 – IEC TS 62878-2-10:2024 © IEC 2024
CONTENTS
FOREWORD . 3
1 Scope . 5
2 Normative references . 5
3 Terms and definitions . 5
4 Objective . 5
5 Cavity formation . 5
6 Design guideline . 6
Annex A (informative) Cavity formation examples . 8
A.1 General . 8
A.2 Etching type example . 8
A.3 Laser type example . 9
Figure 1 – Schematic of cavity substate . 6
Figure A.1 – Etching type . 8
Figure A.2 – Laser type . 9
Table 1 – Cavity formation types . 6
Table 2 – Cavity substrate drawing designators . 7
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
DEVICE EMBEDDING ASSEMBLY TECHNOLOGY –
Part 2-10: Design specification for cavity substrate
FOREWORD
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