EN 16602-70-11:2015

SLOVENSKI STANDARD
01-april-2015
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Space product assurance - Procurement of printed circuit boards
Raumfahrtproduktsicherung - Beschaffung von Leiterplatten
Assurance produit des projets spatiaux - Approvisionnement des circuits imprimés
Ta slovenski standard je istoveten z: EN 16602-70-11:2015
ICS:
31.180 7LVNDQDYH]MD7,9LQWLVNDQH Printed circuits and boards
SORãþH
49.140 Vesoljski sistemi in operacije Space systems and
operations
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

EUROPEAN STANDARD
EN 16602-70-11
NORME EUROPÉENNE
EUROPÄISCHE NORM
January 2015
ICS 31.180; 49.140
English version
Space product assurance - Procurement of printed circuit
boards
Assurance produit des projets spatiaux - Raumfahrtproduktsicherung - Beschaffung von Leiterplatten
Approvisionnement des circuits imprimés
This European Standard was approved by CEN on 11 October 2014.

CEN and CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving
this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning
such national standards may be obtained on application to the CEN-CENELEC Management Centre or to any CEN and CENELEC
member.
This European Standard exists in three official versions (English, French, German). A version in any other language made by translation
under the responsibility of a CEN and CENELEC member into its own language and notified to the CEN-CENELEC Management Centre
has the same status as the official versions.

CEN and CENELEC members are the national standards bodies and national electrotechnical committees of Austria, Belgium, Bulgaria,
Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece,
Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Romania, Slovakia,
Slovenia, Spain, Sweden, Switzerland, Turkey and United Kingdom.

CEN-CENELEC Management Centre:
Avenue Marnix 17, B-1000 Brussels
© 2015 CEN/CENELEC All rights of exploitation in any form and by any means reserved Ref. No. EN 16602-70-11:2015 E
worldwide for CEN national Members and for CENELEC
Members.
Table of contents
Foreword . 4
1 Scope . 5
2 Normative references . 6
3 Terms, definitions and abbreviated terms . 7
3.1 Terms from other standards . 7
3.2 Terms specific to the present standard . 7
3.3 Abbreviated terms. 10
4 Principles . 11
5 Requirements . 12
5.1 Procurement of PCBs . 12
5.1.1 General . 12
5.1.2 Design and layout . 12
5.2 Base materials . 13
5.2.1 Base laminate materials . 13
5.2.2 Basic metallic layer . 14
5.2.3 Plated metallic layers and finishes . 14
5.2.4 Special materials . 15
5.3 PCB delivery . 16
5.3.1 Marking . 16
5.3.2 Associated test coupons . 16
5.3.3 Outgoing inspection and PCB manufacturer data package . 17
5.4 Packaging . 17
5.4.1 Handling and storage . 17
5.4.2 Packaging . 17
5.5 Supplier acceptance of PCBs . 18
5.5.1 Supplier acceptance inspection . 18
5.5.2 Electrical test . 18
6 Inspection of PCBs . 19
6.1 General . 19
6.2 Visual inspection and non-destructive test . 19
6.2.1 Verification of marking . 19
6.2.2 Visual aspects . 19
6.2.3 External dimensions . 22
6.2.4 Warp . 23
6.2.5 Twist . 23
6.3 Microsection inspection criteria . 24
6.3.1 General . 24
6.3.2 Thickness of metal-plating . 25
6.3.3 Aspect of plated-through holes . 27
7 Requirements for PCBs . 30
7.1 Rigid single-sided and double-sided PCBs . 30
7.2 Rigid single-sided and double-sided PCBs for high frequency application . 32
7.3 Flexible PCBs . 35
7.4 Rigid-flex PCBs . 36
7.5 Rigid multilayer PCBs . 37
7.6 Sequential rigid multilayer PCBs . 39
Annex A (normative) PCB Certificate of conformance (CoC) – DRD . 43
Bibliography . 45

Figures
Figure 6-1: Arbitrary defects on conductors . 22
Figure 6-2: Arbitrary defects on spacing between conductors. 22
Figure 6-3: Misalignment of cover layer (for flexible PCBs) . 22
Figure 6-4: Warp . 23
Figure 6-5: Twist. 24
Figure 6-6: Dimensional parameters to be measured . 24
Figure 6-7: Microsection of a PTH . 26
Figure 6-8: Undercut for PCBs with fused SnPb finish . 27
Figure 6-9: Undercut for PCBs with Au/Ni or Au finish . 27
Figure 6-10: Overhang for PCBs with Au/Ni or Au finish . 27
Figure 6-11: Microsection in PTH: Possible defects . 28
Figure 6-12: Microsection of PTH: Possible defects . 29
Figure 6-13: Voids in resin inside buried vias . 29
Figure A-1 : Example of a PCB CoC . 44

Foreword
This document (EN 16602-70-11:2015) has been prepared by Technical
Committee CEN/CLC/TC 5 “Space”, the secretariat of which is held by DIN.
This standard (EN 16602-70-11:2015) originates from ECSS-Q-ST-70-11C.
This European Standard shall be given the status of a national standard, either
by publication of an identical text or by endorsement, at the latest by July 2015,
and conflicting national standards shall be withdrawn at the latest by July 2015.
Attention is drawn to the possibility that some of the elements of this document
may be the subject of patent rights. CEN [and/or CENELEC] shall not be held
responsible for identifying any or all such patent rights.
This document has been prepared under a mandate given to CEN by the
European Commission and the European Free Trade Association.
This document has been developed to cover specifically space systems and has
therefore precedence over any EN covering the same scope but with a wider
domain of applicability (e.g. : aerospace).
According to the CEN-CENELEC Internal Regulations, the national standards
organizations of the following countries are bound to implement this European
Standard: Austria, Belgium, Bulgaria, Croatia, Cyprus, Czech Republic,
Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France,
Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania,
Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Romania,
Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and the United
Kingdom.
Scope
This Standard defines the requirements imposed on the customer, the supplier
and the qualified PCB manufacturer for PCB procurement.
The requirements of clause 7 apply to both qualification and procurement of
finished PCBs and do not include the manufacturing tolerances.
This Standard is applicable for the following type of boards:
• Rigid PCBs (single-sided, double-sided, multilayer, sequential multilayer
and PCBs with metal core)
• Flexible PCBs (single-sided and double-sided)
• Rigid-flex PCBs (multilayer and sequential multilayer)
• High frequency PCBs
• Special PCBs.
PCBs are used for the mounting of components in order to produce PCB
assemblies performing complex electrical functions. The PCBs are subjected to
thermo-mechanical stresses during their assembly such as mounting of
components by soldering, rework and repair under normal terrestrial
conditions. In addition the assembled PCB is subjected to the environment
imposed by launch and space flights. Therefore the qualification of a PCB
supplier to ECSS-Q-ST-70-10 is of extreme importance before the procurement
of PCB for space usage.
This standard may be tailored for the specific characteristics and constraints of a
space project in conformance with ECSS-S-ST-00.
Normative references
The following normative documents contain provisions which, through
reference in this text, constitute provisions of this ECSS Standard. For dated
references, subsequent amendments to, or revision of any of these publications
do not apply. However, parties to agreements based on this ECSS Standard are
encouraged to investigate the possibility of applying the more recent editions of
the normative documents indicated below. For undated references, the latest
edition of the publication referred to applies.

EN reference Reference in text Title
EN 16601-00-01 ECSS-S-ST-00-01 ECSS system — Glossary of terms
EN 16602-70 ECSS-Q-ST-70 Space product assurance — Material, mechanical
parts and processes
EN 16602-70-02 ECSS-Q-ST-70-02 Space product assurance — Thermal vacuum
outgassing test for the screening of space materials
EN 16602-70-07 ECSS-Q-ST-70-07 Space product assurance — Verification and
approval of automatic machine wave soldering
EN 16602-70-08 ECSS-Q-ST-70-08 Space product assurance — Manual soldering of
high-reliability electrical connections
EN 16602-70-10 ECSS-Q-ST-70-10 Space product assurance — Qualification of printed
circuit boards
EN 16602-70-28 ECSS-Q-ST-70-28 Space product assurance — Repair and modification
of printed circuit board assemblies for space use
EN 16602-70-38 ECSS-Q-ST-70-38 Space product assurance — High-reliability soldering
for surface-mount and mixed technology
printed-circuit boards
IEC 60249 (1993-05) Base materials for printed circuits
IEC 60326-2-am 1 Printed boards. Part 2: Test methods
(1992-06)
IPC-4101 Specification for base materials for rigid and
mulitlayer printed boards
IPC-MF-150F Metal foil for printed wiring applications
IPC-CF-152B Composite metallic material specification for printed
wiring board
Terms, definitions and abbreviated terms
3.1 Terms from other standards
For the purpose of this Standard, the terms and definitions from ECSS-S-ST-00-01
apply.
3.2 Terms specific to the present standard
3.2.1 associated test coupon
small piece of PCB designated to have a limited specific set of tests performed
NOTE The associated test coupon is manufactured as
part of a PCB and at the final manufacturing
stage it is separated from it. The associated test
coupon is thus associated with the PCB, with
which it was simultaneously manufactured.
3.2.2 blister
delamination in the form of a localized swelling and separation between any of
the layers of a lamination base material, or between base material and
conductive foil or protective coating
[IEC 60194 (1999-04)]
3.2.3 cover layer (flexible circuit)
layer of insulating material that is applied covering totally or partially over a
conductive pattern on the outer surfaces of a PCB
[IEC 60194 (1999-04)]
3.2.4 crazing
internal condition that occurs in reinforced base material whereby glass fibres
are separated from the resin at the weave intersections
NOTE 1 This condition manifests itself in the form of
connected white spots or crosses that are below
the surface of the base material. It is usually
related to mechanically induced stress.
NOTE 2 See also “measling”.
[IEC 60194 (1999-04)]
3.2.5 delamination
separation between plies within a base material, between base material and a
conductive foil, or any other planar separation with a PCB
NOTE See also “blister”.
[IEC 60194 (1999-04)]
3.2.6 dewetting
condition that results when molten solder coats a surface and then recedes to
leave irregularly-shaped mounds of solder that are separated by areas that are
covered with a thin film of solder and with the basis metal not exposed
[IEC 60194 (1999-04)]
3.2.7 flexible PCB
PCB either single, double sided or multilayer consisting of a printed circuit or
printed wiring using flexible base materials only
[IEC 60194 (1999-04)]
3.2.8 haloing
mechanically-induced fracturing or delamination, on or below the surface of a
base material, that is usually exhibited by a light area around holes or other
machined features
[IEC 60194 (1999-04)]
3.2.9 high frequency PCB
PCB used for high frequency applications, that has specific requirements to the
dielectric properties of the base laminates as well as special dimensional
requirements to the lay-out for electrical purposes
3.2.10 inclusions
foreign particles, metallic or non-metallic, that may be entrapped in an
insulating material, conductive layer, plating, base material or solder
connection
[IEC 60194 (1999-04)]
3.2.11 key personnel
personnel with specialist knowledge responsible for defined production or
product assurance areas
3.2.12 measling
condition that occurs in laminated base material in which internal glass fibres
are separated from the resin at the weave intersection
NOTE 1 This condition manifests itself in the form of
discrete white spots or “crosses” that are below
the surface of the base material. It is usually
related to thermally-induced stress.
NOTE 2 See also “crazing”.
[IEC 60194 (1999-04)]
3.2.13 metal core PCB
PCB using a metal core base material
[IEC 60194 (1999-04)]
3.2.14 multilayer PCB
PCB that consist of rigid or flexible insulation materials and three or more
alternate printed wiring and/or printed circuit layers that have been bonded
together and electrically interconnected
[IEC 60194 (1999-04)]
3.2.15 prepreg
sheet of material that has been impregnated with a resin and cured to an
intermediate stage
NOTE B-staged resin.
[IEC 60194 (1999-04)]
3.2.16 printed circuit board (PCB)
printed board that provides both point-to-point connections and printed
components in a predetermined arrangement on a common base
NOTE This includes single-sided, double sided and
multilayer PCBs with rigid, flexible, and
rigid-flex base materials.
[IEC 60194 (1999-04)]
3.2.17 rigid double-sided PCB
double-sided PCB, either printed circuit or printed wiring, using rigid base
materials only
[IEC 60194 (1999-04)]
3.2.18 rigid-flex PCB
PCB with both rigid and flexible base materials
[IEC 60194 (1999-04)]
3.2.19 rigid-flex double-sided PCB
double-sided PCB, either printed circuit or printed wiring, using combinations
of rigid and flexible base materials
[IEC 60194 (1999-04)]
3.2.20 rigid-flex multilayer PCB
multilayer PCB, either printed circuit or printed wiring, using combinations of
rigid multilayer and flexible single and double-sided base materials
3.2.21 rigid PCB
PCB using rigid base materials only
[IEC 60194 (1999-04)]
3.2.22 rigid single-sided PCB
single-sided PCB, either printed circuit or printed wiring, using rigid base
materials only
[IEC 60194 (1999-04)]
3.2.23 rigid multilayer PCB
multilayer PCB, either printed circuit or printed wiring, using rigid base
materials only
[IEC 60194 (1999-04)]
3.2.24 scratch
narrow furrow or grove in a surface
NOTE It is usually shallow and caused by the marking
or rasping of the surface with a pointed or
sharp object.
[IEC 60194 (1999-04)]
3.2.25 sequentially laminated multilayer PCB
multilayer PCB that is formed by laminating together through hole plated
double-sided or multilayer PCBs
NOTE Thus, some of its conductive layers are
interconnected with blind or buried vias.
[IEC 60194 (1999-04)]
3.2.26 test pattern
part of the PCB that refers to the copper pattern on and within the PCB
substrate for a specific test
3.3 Abbreviated terms
For the purpose of this Standard, the abbreviated terms from ECSS-S-ST-00-01
and the following apply:
Abbreviation Meaning
certificate of conformance
CoC
declared material list
DML
not applicable
n.a.
printed circuit board
PCB
plated-through hole
PTH
polytetrafluoroethylene
PTFE
root-mean-square
r.m.s.
to be defined
TBD
Principles
For the need of this Standard the role “PCB manufacturer” as lowest level
supplier has been explicitly introduced to allow proper allocation of
requirements.
Requirements
5.1 Procurement of PCBs
5.1.1 General
a. The supplier shall procure PCBs from a PCB manufacturer with a
qualification approval for an identified technology in conformance with
ECSS-Q-ST-70-10.
NOTE The supplier can procure space quality PCBs
from a PCB manufacturer with qualification
approval according to ECSS-ST-Q-70-10 during
the valid period of the approval.
b. The supplier shall perform the incoming inspection and control of the
delivered PCBs.
5.1.2 Design and layout
a. The supplier and PCB manufacturer shall agree on the following issues:
1. The transfer of the plotting, drilling and routing data from the
supplier to the PCB manufacturer;
2. The numbering system for the different issues;
NOTE This is done to avoid mistakes.
3. Construction data, such as hole sizes, contours and thickness
dimensions, as well as specific requirements regarding electrical
requirements and dielectric properties.
NOTE The agreement between the supplier and the
PCB manufacturer can be described in the
specific procurement document.
b. The supplier shall provide the PCB manufacturer with the net list
documentation with a suitable format.
NOTE The net list is used to verify that the supplier’s
data files are correctly transferred to the PCB
manufacturer and to set up the electrical
functional testing of the finished PCBs.
c. The supplier shall include the manufacturing tolerances given by the
PCB manufacturer when designing the PCB layout.
NOTE The tolerances and requirements for the various
finished PCBs are specified in clause 7.
d. Multilayer PCBs shall have a layout and be built as symmetrical as
possible to avoid excessive wrapage and twist.
e. The supplier shall use a minimum of two prepregs, between layers.
f. The number of electrical layers shall be an even number.
g. For rigid-flex PCBs the customer shall order the PCB with its frame
attached.
NOTE 1 This is done in order not to stress the flexible
parts during handling and mounting of
components.
NOTE 2 The frame can be detached after the assembly
of the PCBs.
h. The PCB may be procured without the frame providing that stressing of
the flexible connection is avoided.
i. The PCB manufacturer shall define during the design together with the
supplier the amount of copper and its distribution.
NOTE An even distribution is preferred.
j. For surface mount technology and circuits to be wave soldered, only
pads on the external layer should be used.
NOTE This is done because high density circuitry on
external layers is not reliable.
k. The supplier shall use teardrop design for fine lines and small annular
rings.
l. The PCB manufacturer shall not use hot air solder levelling (HAL or
HASL) and infrared reflow.
NOTE These techniques can be destructive because of
overheating of the PCB. Also it does not appear
possible to fulfil the requirement for the tin-
lead surface finish with regard to dimensions.
m. Before any installation of components or soldering or desoldering
operations a bake-out shall be performed as specified in ECSS-Q-ST-70-08.
5.2 Base materials
5.2.1 Base laminate materials
a. The PCB manufacturer shall use materials which conform to ECSS-Q-ST-
70, IEC 60249 (1993-05) and IPC-4101 Standards.
NOTE All base materials are mentioned in clause 7.
5.2.2 Basic metallic layer
a. The supplier shall design the external layer using basic copper thickness
of 70 µm, 35 µm, 17,5 µm and 9 µm.
b. The supplier shall design the internal layers using basic copper thickness
of 70 µm, 35 µm and 17,5 µm.
c. For Cu-foil the PCB manufacturer shall use copper quality “HTE” (IPC-
MF-150F).
5.2.3 Plated metallic layers and finishes
5.2.3.1 Copper (electrolytic)
a. The PCB shall be manufactured with copper of purity of at least 99,5 %.
b. The copper ductility shall be at least 12 %.
NOTE A ductility of 18 % is recommended.
c. The PCB manufacturer shall plate the plated-through holes with the
following copper thickness:
1. For soldering holes at least 25 µm
2. Via holes at least 20 µm.
d. The total basic and plated copper on surface layers for soldering pads
shall have a thickness of at least 40 µm.
e. The total basic and plated copper for internal layers shall have a
thickness of at least 17,5 µm.
5.2.3.2 Electroplated tin-lead thickness over copper
a. The fused tin-lead shall have a minimum thickness of 8 µm in the highest
part of the pad and tracks.
NOTE Before reflow the thickness of (15 ± 7) µm is
recommended.
b. The fused tin-lead shall have a minimum thickness of 2 µm on the corner
of the PTH.
NOTE A fused tin-lead thickness of 1 µm on the corner
of the PTH can be tolerated provided that the
solderability is acceptable.
c. The fused tin-lead shall have a thickness of 8 µm on half of the height of
the hole wall.
d. The fused tin-lead shall have a thickness of 2 µm on the remaining two
quarters of the hole wall.
e. The fused tin-lead should reflow over the edges of the copper pads and
tracks.
5.2.3.3 Nickel electrolytic plating (optional) over copper
plating
a. The electrolytic nickel plating over copper shall have a thickness from
2 µm to 10 µm.
5.2.3.4 Gold (electrolytic)
a. The PCB manufacturer shall use gold for high frequency circuits or other
assembly methods when specified by the supplier.
b. When gold finish is needed the PCB shall be manufactured with gold of a
purity of at least 99,8 %.
c. When gold finish is needed the PCB shall be manufactured with gold that
does not contain more than 0,2 % of silver.
NOTE Alternative types of gold (e.g. for high
frequency circuits) can be used, provided that
the gold is proven to be satisfactory during
execution of the qualification programme.
d. The thickness of gold over bare copper shall be between 3 µm and 7 µm.
e. The thickness of gold over nickel plating shall be between 1 µm and
7 µm.
f. If tin-lead plating is applied together with gold plating on the same PCB,
a tin-lead overlap on gold of minimum 200 µm shall be used on the
surface of the PCB.
NOTE This is done in order to ensure protection of the
plated copper layer.
g. The tin-lead overlap area shall be a minimum of 200 µm distance from the
termination pad designated for soldering as given in ECSS-Q-ST-70-08
clause 8.4.
5.2.4 Special materials
5.2.4.1 Metal core
a. The PCB manufacturer shall use copper - invar – copper or copper -
molybdenum – copper in conformance with IPC-CF-152B.
5.2.4.2 Heat-sinks: material and surface treatment
a. For copper, aluminium and brass heat-sinks, the PCB manufacturer shall
use the material as specified by the supplier’s DML.
5.3 PCB delivery
5.3.1 Marking
a. The PCB manufacturer shall mark the PCBs as follows:
1. PCB manufacturer’s logo
2. PCB reference code and serial number
NOTE In the event that there is not sufficient space on
the PCBs for the marking, the PCB
manufacturer can ensure traceability by other
means or request for waiver.
3. Number of layers.
b. Marking inks shall be as follows:
1. Permanent polymer inks
2. Specified in the procurement documentation
3. Capable of withstanding fluxes, cleaning solvents, soldering,
cleaning and coating processes encountered in later manufacturing
processes according to ECSS-Q-ST-70-07, ECSS-Q-ST-70-08, ECSS-
Q-ST-70-28, ECSS-Q-ST-70-38
4. Conform to the outgassing requirements of ECSS-Q-ST-70-02.
c. If a conductive marking is used, the marking shall be treated as a
conductive element on the PCB.
5.3.2 Associated test coupons
a. The PCB manufacturer shall produce one associated test coupon per
panel to be delivered to the supplier.
b. The design of the associated test coupon shall be representative of the
PCBs to be delivered to the supplier.
c. The supplier and the PCB manufacturer shall agree on the design of the
associated test coupon.
d. The associated test coupon shall enable:
1. Testing as defined in clause 6
2. Testing of insulation resistance as defined in ECSS-Q-ST-70-10
clause 7.2.8
3. Continuity testing as defined in ECSS-Q-ST-70-10 clause 7.2.8
4. Dielectric withstanding voltage as defined in ECSS-Q-ST-70-10
clause 7.2.8.
5.3.3 Outgoing inspection and PCB manufacturer
data package
a. The PCB manufacturer shall test an in house associated test coupon to
demonstrate the compliance to the inspection criteria of microsections as
described in clause 6.3.
b. The PCB manufacturer shall not deliver a PCB for which the results on
the associated test coupon present any major nonconformance as per
clauses 6 and 7.
c. The PCB manufacturer shall deliver the data package to the supplier.
d. The data package shall contain the following items:
1. The Certificate of conformance (CoC) in conformance with Annex A;
2. Supplier specification.
5.4 Packaging
5.4.1 Handling and storage
a. PCBs shall be stored in a dry environment until they are soldered.
b. If assembly involves two or more steps, the supplier shall store the PCBs
in between the assembly steps in containers either with desiccant or in
dry nitrogen environment.
c. The PCBs shall be handled only with clean lint-free gloves.
5.4.2 Packaging
a. The PCBs and their associated test coupons shall be packed in order to
prevent any degradation due to corrosion, deterioration or physical
damage.
b. The PCBs shall be individually packed in a non-corrosive material.
c. The PCB manufacturer shall ensure safe delivery to the supplier.
d. The packaging shall consist of individual, air tight plastic containers.
e. PVC packaging shall not be used.
f. Desiccant or dry nitrogen filling shall be used in the packaging.
g. The PCB shall not be in direct contact with the desiccant.
h. If a desiccant is used, means for indication of moisture content shall be
provided.
i. The PCBs and their associated test coupon shall be packed in order to
avoid pressure on, or friction between the PCBs.
j. The containers used to ship the PCBs and the associated test coupon shall
be of type and size that ensure acceptance by common carrier.
k. Each shipment shall include for every delivered PCB the Certificate of
conformance (CoC) established in conformance with Annex A.
l. Each shipping container shall be marked according to supplier
requirements.
5.5 Supplier acceptance of PCBs
5.5.1 Supplier acceptance inspection
a. The supplier shall inspect each of the delivered PCBs according to PCB
delivery clause 5.3.
b. The supplier shall visually inspect each of the delivered PCBs in
conformance with the procedure shown in clause 6.
c. The supplier shall reject a PCB in case of a major nonconformance.
d. The supplier shall retain the associated test coupon for at least 10 years or
as otherwise specified in the project requirements.
NOTE The associated test coupon can be used for
supplementary testing.
5.5.2 Electrical test
a. The supplier and the PCB manufacturer shall agree on the electrical test
to be performed by the PCB manufacturer.
b. The PCB manufacturer shall use either the test bed electrical tester or the
flying probe tester to measure the continuity and the insulation as part of
functional testing.
Inspection of PCBs
6.1 General
The tests specified in this clause are a subset of the tests in ECSS-Q-ST-70-10
clause 7.
6.2 Visual inspection and non-destructive test
6.2.1 Verification of marking
a. Each board shall be inspected with the naked eye for correct marking.
b. The marking shall be legible and resistant to test stresses.
c. The nonconformance criteria shall be as follows:
1. Identification impossible .M
2. Marking not conforming to supplier’s specification .M
3. Defects not affecting identifications. .m
6.2.2 Visual aspects
a. Each board shall be inspected by magnification ≥ ×10 with suitable
lighting conditions to verify that construction and workmanship meet the
requirements.
b. In case of any irregularity, the area shall be examined under ×20 - ×40
magnification.
c. The nonconformance criteria for the general cleanliness and
contamination shall be as follows:
1. Contamination visible to the naked eye and not
removable by cleaning according to ECSS-Q-ST-70-08 .M
2. Contamination visible to the naked eye and removable
by cleaning according to ECSS-Q-ST-70-08 .m
d. The nonconformance criteria for the substrate shall be as follows:
1. Not in conformance with PCB manufacturer’s
trademark and required quality .M
2. Scratches cutting glass fibre or leaving marks in the
dielectric laminate that are affecting reliability .M
3. Scratches not affecting reliability .m
4. Dents, crazing and haloing:
(a) Visible to the naked eye . M
(b) Only visible with magnification aids . m
5. Non-homogeneity regarding colouring and opacity . m/M
6. Discoloured copper oxide layer on internal layer is acceptable
7. Inclusion of foreign matter, blistering or air bubbles:
(a) Visible to the naked eye . M
(b) Only visible with magnification aids . m
8. Delamination . M
9. Measling:
(a) General measling spread over the whole PCB
surface . M
(b) Local measling that causes reduction of the
insulation distance in the outer layer to below
the requirement . M
(c) Local measling that does not cause reduction
of the insulation distance in the outer layer to
below the requirement . m
10. Fungus growth; . M
11. Delamination of cover layer (only for flexible PCB). . m/M
e. The nonconformance criteria for non-plated-through holes
shall be as follows:
1. Holes plated unintentionally . m/M
2. Incompletely drilled holes, missing or additional holes . m/M
f. The nonconformance criteria for the routing shall be as follows:
1. Incomplete routing of board, such that dimensional or
mechanical requirements are not met . M
2. Arbitrary cutting defects that remain acceptable
within the dimensional requirements . m
g. The nonconformance criteria for the surface metallization shall be as
follows:
1. Conductors or pads not conforming to
supplier’s specification . M
2. Terminal pads or conductors partially or completely
missing . M
3. Terminal pads or conductors that are cut . M
4. Terminal pads or conductors forming a short circuit . M
5. Lifting/delamination of conductive pattern from substrate . M
6. Scratches in the SnPb metallisation exposing the
underlaying copper plating . M
7. Copper or nickel visible on top surface plated areas . M
NOTE Exposed copper can be accepted on the side of
tracks or on the side of soldering pads.
8. Large number of superficial scratches not attributed to a
manufacturing process evidencing bad workmanship . M
9. Dewetting of fused tin lead finish on solder pads . M
10. Granular surface structure of fused tin lead finish on
solder pads . m/M
11. Corrosion of exposed copper . M
12. Migration of underlaying copper through gold coating . M
h. The nonconformance criteria for plated-through holes shall be as follows:
1. Incompletely drilled, additional or missing holes . M
2. Partially or completely missing metallization . M
3. Component holes ≥ 0,6 mm filled or partially filled with
solder resulting in a diameter smaller than the requirement . m/M
i. The nonconformance criteria for arbitrary defects of conductors and
terminal pads shall be as follows:
1. a ≤ 20 % of x
and minimum conductor width > requirement . m
2. a > 20 % of x. M
3. minimum conductor width < requirement . M
4. b ≤ x . m
5. b > x . M
6. Opposite peaks: if z < 80 % of y . M
7. Isolated peaks or valleys: h > 20 % of x
and z < requirement . M
8. Conducting island: a + h > 20 % of y
and the isolation spacing < requirement . M
9. Minimum remaining spacing y - a < requirement . M
10. a > 20 % of y . M
11. b > y . M
12. Cover layer (flexible PCBs) covering part of solder pad
(see Figure 6-3) . M
NOTE Intermittent and irregular metallisation defects
on conductors are edge roughness (peak or
valley), pits, pin holes, voids, protrusions or
indentations, as shown in Figure 6-1, Figure 6-2
and Figure 6-3.
x: nominal conductor width
Figure 6-1: Arbitrary defects on conductors
x
y: nominal spacing between conductors

Figure 6-2: Arbitrary defects on spacing between conductors
e
δ
r
coverlay
component hole
r  : rest of metal
pad
e : annular ring
δ
Figure 6-3: Misalignment of cover layer (for flexible PCBs)
6.2.3 External dimensions
a. Each board shall be measured by means of suitable standard measuring
equipment to verify that the physical dimensions, including board
thickness and external dimensions meet the supplier’s specification.
b. The nonconformance criteria for the thickness of base laminate (average
of 4 measurements on the board) shall be as follows:
1. Thickness not conforming to tolerance limits of the
supplier’s specification . M
c. The nonconformance criteria for the length and width of board (average
of 2 measurements on the board) shall be as follows:
1. Length or width not conforming to tolerance limits of the
supplier’s specification . M
6.2.4 Warp
a. The PCBs shall be placed unrestrained on a plane horizontal surface with
the convex side upward.
b. The warp shall be expressed in percentage terms.
c. The maximum bow between the plane horizontal surface and the PCB
shall be measured as defined in Figure 6-4.
d. The length of the PCB shall be measured.
e. The warp percentage shall be calculated as defined in equation [6-1]:
Max.blow (mm)
Warp (%) = ×100
[6-1]
Lengthof the PCB (mm)
f. The nonconformance criteria shall be as follows:
1. Warp > requirement . M
max.
bow
Figure 6-4: Warp
6.2.5 Twist
a. The PCB shall be placed on a plane horizontal surface so that it rests on
three corners.
b. The twist shall be expressed in percentage terms.
c. The distance between the plane horizontal surface and the fourth corner
of the PCB shall be measured as defined in Figure 6-5.
d. The length of the diagonal shall be measured.
e. The twist percentage shall be calculated as defined in equation [6-2].
Max.twist (mm)
Twist (%) = ×100
[6-2]
Length of the diagonal (mm)
f. The nonconformance criteria shall be as follows:
1. Twist > requirement . M
max. twist
A, B and C are touching base
Figure 6-5: Twist
6.3 Microsection inspection criteria
6.3.1 General
a. The test shall be carried out in conformance with tests 1c and 15b of
IEC 60326-2-am 1 (1992-06).
b. For high frequency conductors the customer shall specify at which height
of the conductor the width shall be measured (see Figure 6-6).

w width of conductor
δe minimum annular erring on external layer
δe minimum annular erring on internal layer
d diameter of plated-through hole
h height of conductor
Figure 6-6: Dimensional parameters to be measured
6.3.2 Thickness of metal-plating
a. The test shall be carried out on a microsection.
b. Observations shall be made with magnification greater than or equal to ×250.
c. The nonconformance criteria for the thickn
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