SIST-TP CEN/TR 17602-60-02:2022

SLOVENSKI STANDARD
01-februar-2022
Zagotavljanje kakovosti proizvodov v vesoljski tehniki - Priročnik za tehnike
blaženja učinkov sevanja na vezja ASIC in FPGA
Space product assurance - Techniques for radiation effects mitigation in ASICs and
FPGAs handbook
Raumfahrtproduktsicherung - Handbuch zu Minderungsmethoden von
Strahlungseffekten auf ASICs und FPGAs
Ingénierie spatiale - Guide sur les techniques de durcissement des ASICs et FPGAs vis-
à-vis des effets des radiations
Ta slovenski standard je istoveten z: CEN/TR 17602-60-02:2021
ICS:
03.120.99 Drugi standardi v zvezi s Other standards related to
kakovostjo quality
49.140 Vesoljski sistemi in operacije Space systems and
operations
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

TECHNICAL REPORT CEN/TR 17602-60-02

RAPPORT TECHNIQUE
TECHNISCHER BERICHT
December 2021
ICS 49.140
English version
Space product assurance - Techniques for radiation effects
mitigation in ASICs and FPGAs handbook
Ingénierie spatiale - Guide sur les techniques de Raumfahrtproduktsicherung - Handbuch zu
durcissement des ASICs et FPGAs vis-à-vis des effets Minderungsmethoden von Strahlungseffekten auf
des radiations ASICs und FPGAs

This Technical Report was approved by CEN on 22 November 2021. It has been drawn up by the Technical Committee
CEN/CLC/JTC 5.
CEN and CENELEC members are the national standards bodies and national electrotechnical committees of Austria, Belgium,
Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy,
Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia,
Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and United Kingdom.

CEN-CENELEC Management Centre:
Rue de la Science 23, B-1040 Brussels
© 2021 CEN/CENELEC All rights of exploitation in any form and by any means Ref. No. CEN/TR 17602-60-02:2021 E
reserved worldwide for CEN national Members and for
CENELEC Members.
Table of contents
European Foreword . 14
1 Scope . 15
2 References . 16
3 Terms, definitions and abbreviated terms . 17
3.1 Terms from other documents . 17
3.2 Terms specific to the present document . 17
3.3 Abbreviated terms. 19
4 Radiation environment and integrated circuits . 25
4.1 Overview . 25
4.2 Radiation environment in space . 25
4.3 Radiation Effects in ICs . 26
4.3.1 Overview . 26
4.3.2 Cumulative effects. 26
4.3.3 Single Event Effects (SEEs) . 27
4.3.3.1 Overview. 27
4.3.3.2 Non-destructive SEE . 28
4.3.3.3 Destructive SEE . 29
4.3.3.4 Summary . 30
5 Choosing a device hardening strategy . 31
5.1 The optimal strategy . 31
5.2 How to use this handbook . 32
6 Technology selection and process level mitigation . 35
6.1 Overview . 35
6.2 Mitigation techniques . 36
6.2.1 Epitaxial layers . 36
6.2.2 Silicon On Insulator . 37
6.2.3 Triple wells . 40
6.2.4 Buried layers . 42
6.2.5 Dry thermal oxidation . 43
6.2.6 Implantation into oxides . 45
6.3 Technology scaling and radiation effects . 46
7 Layout . 49
7.1 Overview . 49
7.2 Mitigation techniques . 50
7.2.1 Ringed or Enclosed Layout Transistor . 50
7.2.2 Contacts and guard rings . 52
7.2.3 Dummy transistors . 55
7.2.4 Transistors Gate W/L ratio sizing . 57
8 Analogue circuits . 58
8.1 Overview . 58
Mitigation techniques . 59
8.2
8.2.1 Node Separation and Inter-digitation . 59
8.2.2 Analogue redundancy (averaging) . 63
8.2.3 Resistive decoupling . 64
8.2.4 Filtering . 67
8.2.5 Modifications in bandwidth, gain, operating speed, and current
drive . 68
8.2.6 Reduction of window of vulnerability . 71
8.2.7 Reduction of high impedance nodes . 75
8.2.8 Differential design . 77
8.2.9 Dual path hardening . 80
9 Embedded memories . 85
9.1 Overview . 85
9.2 Mitigation techniques . 86
9.2.1 Hardening of individual memory cells . 86
9.2.1.1 Overview. 86
9.2.1.2 Resistive hardening . 86
9.2.1.3 Capacitive hardening . 87
9.2.1.4 IBM hardened memory cell . 89
9.2.1.5 HIT hardened memory cell . 91
9.2.1.6 DICE hardened memory cell . 92
9.2.1.7 NASA-Whitaker hardened memory cell . 94
9.2.1.8 NASA-Liu hardened memory cell . 95
9.2.2 Bit-interleaving in memory arrays . 97
9.2.3 Data scrubbing . 99
9.3 Comparison between hardened memory cells . 100
10 Radiation-hardened ASIC libraries . 101
10.1 Introduction . 101
10.2 IMEC Design Against Radiation Effects (DARE) library . 102
10.3 CERN 0,25 µm radiation hardened library . 103
10.4 BAE 0,15 µm radiation hardened library . 103
10.5 Ramon Chips 0,18 µm and 0,13 µm radiation hardened libraries . 103
10.6 Cobham (former Aeroflex) 600, 250, 130 and 90 nm radiation hardened
libraries . 104
10.7 Microchip Atmel MH1RT 0,35 µm and ATC18RHA 0,18 µm CMOS and
ATMX150RHA 0,15 µm SOI CMOS radiation hardened libraries . 104
10.8 ATK 0,35 µm radiation hardened cell library . 105
10.9 ST Microelectronics C65SPACE 65 nm radiation hardened library . 105
10.10 RedCat Devices radiation hardened libraries . 105
11 Digital circuits . 106
11.1 Overview . 106
11.2 Mitigation techniques . 107
11.2.1 Spatial redundancy . 107
11.2.1.1 Description of the concept . 107
11.2.1.2 Duplex architectures . 108
11.2.1.3 Triple Modular Redundancy architectures . 109
11.2.1.3.1 General . 109
11.2.1.3.2 Basic TMR . 109
11.2.1.3.3 Full TMR . 110
11.2.2 Temporal redundancy . 113
11.2.2.1 Description of the concept . 113
11.2.2.1.1 Overview . 113
11.2.2.1.2 Triple Temporal Redundancy combined with spatial redundancy 114
11.2.2.1.3 Minimal level sensitive latch . 115
11.2.3 Fail-safe, deadlock-free finite state machines . 117
11.2.4 Selective use of logic cells, clock and reset lines hardening . 121
12 System on a chip . 123
12.1 Overview . 123
12.2 Mitigation techniques . 124
12.2.1 Error Correcting Codes . 124
12.2.1.1 Introduction to multiple options . 124
12.2.1.1.1 General . 124
12.2.1.1.3 Cyclic Redundancy Check . 126
12.2.1.1.4 BCH codes . 127
12.2.1.1.5 Hamming codes . 127
12.2.1.1.6 SEC-DED codes . 128
12.2.1.1.7 Reed-Solomon codes . 128
12.2.1.1.8 Arithmetic codes . 128
12.2.1.1.9 Low Density Parity Codes . 129
12.2.2 Mitigation for Memory Blocks . 130
12.2.3 Filtering SET pulses in data paths . 131
12.2.4 Watchdog timers . 133
12.2.5 TMR in mixed-signal circuits . 135
13 Field programmable gate arrays . 138
13.1 Overview . 138
13.2 Mitigation techniques . 140
13.2.1 Local Triple Modular Redundancy . 140
13.2.2 Global Triple Modular Redundancy . 142
13.2.3 Large grain Triple Modular Redundancy . 144
13.2.4 Embedded user memory Triple Modular Redundancy . 146
13.2.5 Additional voters in TMR data-paths to minimise DCE . 148
13.2.6 Reliability-oriented place and Route Algorithm (RoRA) . 151
13.2.7 Embedded processor protection . 153
13.2.8 Partial reconfiguration or Scrubbing of configuration memory . 155
13.2.8.1 Description of the concept . 155
13.2.8.1.1 Overview . 155
13.2.8.1.2 Full scrubbing . 156
13.2.8.1.3 Partial scrubbing . 156
13.2.8.1.4 Partial reconfiguration . 157
14 Software-implemented hardware fault tolerance . 160
14.1 Overview . 160
14.2 Mitigation techniques . 161
14.2.1 Redundancy at instruction level. 161
14.2.2 Redundancy at task level . 167
14.2.3 Redundancy at application level: using a hypervisor . 171
15 System architecture . 174
15.1 Overview . 174
15.2 Mitigation techniques . 175
15.2.1 Shielding . 175
15.2.2 Watchdog timers . 179
15.2.3 Power cycling and reset . 180
15.2.4 Latching current limiters . 180
15.2.5 Spatial Redundancy . 181
15.2.5.1 Overview. 181
15.2.5.2 Duplex architectures . 181
15.2.5.2.1 Description of the concept . 181
15.2.5.2.2 Lockstep . 182
15.2.5.2.3 Double duplex . 183
15.2.5.2.4 Double Duplex Tolerant to Transients . 183
15.2.5.3 Triple Modular Redundant system . 185
15.2.6 Error Correcting Codes . 187
15.2.7 Off-chip SET filters . 187
16 Validation methods . 188
16.1 Introduction . 188
16.2 Fault injection . 188
16.2.1 Fault injection at transistor level . 188
16.2.1.1 Overview. 188
16.2.1.2 Physical level 2D/3D device simulation . 189
16.2.1.3 Transient fault injection simulations at electrical level . 190
16.2.2 Fault injection at gate level . 190
16.2.3 Fault injection at device level . 191
16.2.3.1 Overview. 191
16.2.3.2 Fault injection in processors . 191
16.2.3.3 Fault injection in FPGAs . 193
16.2.3.4 Analytical methods for predicting effects of soft errors on SRAM-
based FPGAs . 195
16.2.4 Fault injection at system level . 195
16.3 Real-life radiation tests . 196
16.3.1 Overview . 196
16.3.2 Tests on-board scientific satellites . 196
16.3.3 On-board stratospheric balloons . 196
16.3.4 Ground level tests . 196
16.4 Ground accelerated radiation tests . 197
16.4.1 Overview . 197
16.4.2 Standards and specifications . 197
16.4.3 SEE test methodology . 198
16.4.4 TID test methodology . 200
16.4.5 TID and SEE test facilities . 202
16.4.5.1 Overview. 202
16.4.5.2 Total ionizing dose . 203
16.4.5.3 Single event effects . 204
16.4.6 Complementary SEE test strategies . 207
16.4.6.1 Overview. 207
16.4.6.2 Laser beams SEE tests . 207
16.4.6.3 Ion-Microbeam SEE tests. 209
16.4.6.4 Californium-252 and Americium-241 SEE tests . 210
Annex A (informative) Vendor/institute-ready solutions that include
mitigation or help to mitigate . 211
Bibliography . 212

Figures
Figure 4-1: Schematic showing how galactic cosmic rays deposit energy in an
electronic device, after Lauriente and Vampola [321] . 27
Figure 4-2: Two upsets in the same word induced by a single particle (MBU) . 29
Figure 4-3: Two upsets in the different words induced by a single particle (MCU) . 29
Figure 5-1: Different abstraction levels where mitigation techniques can be applied and
naming convention for this Handbook. . 33
Figure 6-1: Example of epitaxial layer in CMOS technology . 36
Figure 6-2: a) Conventional bulk NMOS transistor, b) Partially depleted SOI, c) Fully
depleted SOI . 38
Figure 6-3: a) single-well technology, b) twin-well technology, c) triple-well technology
implementing a deep n-well to isolate the p-well forming the NMOS from
the substrate . 41
Figure 6-4: Schematic view of a P-type buried layer in a P-well . 42
Figure 6-5: Radiation-induced back channel threshold voltage shifts for different SOI
substrates types, SOI layer thickness and hardening process conditions
[1] . 45
Figure 7-1: Gate oxide and STI oxide in CMOS technology . 49
Figure 7-2: a) Conventional two edge NMOS, b) Enclosed Layout Transistor NMOS . 50
Figure 7-3: Two examples of NMOS transistor layout eliminating radiation-induced
leakage current between source and drain . 51
Figure 7-4: Parasitic thyristor responsible for SEL (top), introduction of P+ guard ring
around NMOS transistor (bottom). 53
Figure 7-5: CMOS transistors with guard rings . 54
Figure 7-6: RHBD technique using dummy transistors. (a) The circuits, (b) the layouts
(layout1 on the left, layout2 on the right), after J. Chen [286]. . 56
Figure 8-1: Cross-section of two adjacent NMOS devices in a bulk CMOS technology
(From [109]) . 60
Figure 8-2: (a) Upset sensitivity data for basic DICE topology implemented in 90 nm
CMOS at three angles of incidence [114] and (b) measured upset cross-
sections as a function of azimuth angle for the Kr ion (LET of approximately
30 MeV*cm /mg) in improved DICE implementing nodal spacing [114] . 60
Figure 8-3: Charge collected on an adjacent transistor for a) PMOS and, b) transistors
as a function of the distance separating them ([112]) . 61
Figure 8-4: (a) Comparison of collected charge for the active and passive NMOS
devices following laser-induced charge deposition at the active device. (b)
Collected charge for passive NMOS devices verifies the charge sharing
effect and shows a nodal spacing dependence for the passive device
charge collection ([95]) . 61
Figure 8-5: Analogue averaging through the use of N identical resistors. A perturbation
(∆V) due to a particle strike on any one copy of the circuit is reduced to
∆V/N . 63
Figure 8-6: (a) A standard current-based charge pump configuration for phase-locked
loop circuits. (b) Single-event hardened voltage-based charge pump
configuration . 64
Figure 8-7: (a) A standard LC Tank Voltage-Controlled Oscillator (VCO) and (b) Single-
event hardened configuration utilizing decoupling resistor R (From
[118]). . 65
Figure 8-8: Brokaw bandgap reference circuit with an output low-pass filter for
improved noise, isolation, and transient suppression (From[128]). . 67
Figure 8-9: Transient PLL error response as a function of PLL bandwidth . 70
Figure 8-10: Simulated windows of vulnerability over one data conversion cycle in a 2-
bit flash ADC (From [130]). . 72
Figure 8-11: The number of errors with respect to cycle time following laser-induced
charge deposition in a phase-locked loop (From [131]). . 72
Figure 8-12: Simulated windows of vulnerability over one data conversion cycle for un-
hardened and hardened 2-bit flash ADCs (From [132]) . 73
Figure 8-13: Simplified view of the auto-zeroed comparator (From [134] ) . 73
Figure 8-14: (a) Simplified schematic of a typical LC Tank VCO and (b) an
experimentally observed transient resulting from laser-induced charge
injection on transistor M1 (From [135]) . 75
Figure 8-15: Schematic of RHBD CMOS LC Tank VCO (From [134]) . 76
Figure 8-16: Two-dimensional slice of three PMOS transistors depicting the electrical
signal and the charge-sharing signal caused by an ion strike, i.e. pulse
quenching (From [142]). . 78
Figure 8-17: Basic differential pair . 78
Figure 8-18: Differential pair including devices A and B before and after DCC layout for
maximizing charge sharing (From [143]) . 79
Figure 8-19: Charge collected by a single transistor for single (left) and parallel (right)
transistor configuration, is shown in the top row. Differential charge is
shown in the bottom row for single (left) and parallel (right) transistor
configuration (From [143]) . 79
Figure 8-20: (a) The switched-capacitor comparator operates in two phases: (b) reset
phase and (c) evaluation phase (From [142]) . 81
Figure 8-21: Simplified circuit schematic of the differential amplifier showing the split
input paths (From [142]) . 81
Figure 8-22: The switched-capacitor comparator with split differential amplifier input
paths to harden the floating nodes against single-event upsets (From
[142]) . 82
Figure 8-23: Simulated output error voltage versus deposited charge of a sample and
hold amplifier with and without dual path hardening (From [141]) . 82
Figure 8-24: Simulated deposited charge required to generate a SEU at the output of
the comparator for various differential input voltages for the (a) unhardened
design, (b) the design with increased capacitors (2x), and (c) the design
implementing dual path hardening (From [142]) . 83
Figure 9-1:Resistor memory cell . 86
Figure 9-2: Hardened SRAM cell using a capacitor (SRAM-C cell) . 88
Figure 9-3: The SRAM-tct cell . 88
Figure 9-4: IBM hardened memory cell (after original picture in [177]) . 90
Figure 9-5: HIT memory cell . 91
Figure 9-6: DICE hardened cell structure . 93
Figure 9-7: NASA-Whitaker hardened memory cell . 94
Figure 9-8: NASA-Liu hardened memory cell (after original picture in [186] . 96
Figure 9-9: Standard memory topology . 98
Figure 9-10: Example of memory topology with scrambling . 98
Figure 10-1: Hardened 2 input NOR gate . 102
Figure 11-1: Block diagram of the spatial redundancy architecture . 108
Figure 11-2: (a) SET and (b) SEU detection with a duplex architecture . 108
Figure 11-3: Fault detection by a duplex architecture . 109
Figure 11-4: Hot backup (a) and duplication with backup (b) approaches . 109
Figure 11-5: SET (a) and SEU (b) detection with a TMR architecture . 110
Figure 11-6: Fault detection and correction in the full TMR architecture . 111
Figure 11-7: SEU-tolerant latch based on DMR (CE1 and CE2) and a Muller-C element
(CE3) . 112
Figure 11-8: Typical topology for a sequential circuit . 114
Figure 11-9: Temporal sampling using delays on clocks and TMR . 114
Figure 11-10: Temporal sampling using delays on data . 115
Figure 11-11: Minimal temporal sampling latch replicating itself in time . 115
Figure 11-12: 4 states FSM bubble-diagram showing legal and illegal states, and states
transitions . 119
Figure 12-1: Example of a CRC computation on a binary message “1101011011” . 127
Figure 12-2: An arithmetic function using an arithmetic code as error detection
mechanism . 129
Figure 12-3: Logical masking of a transient in two logical gates . 131
Figure 12-4: Electrical masking along a path in combinatorial logic . 132
Figure 12-5: Temporal masking . 132
Figure 12-6: SET Filter proposed by Actel Corporation for their Flash-based FPGAs, as
per S. Rezgui et al. in [329] . 132
Figure 12-7: Watchdog Timer . 134
Figure 12-8: Functional block diagram of the IS139ASRH SEE-hardened voltage
comparator . 135
Figure 12-9: Signal-to-noise (SNR) ratio improvement when increasing use of
Comparator TMR in a 10-bit pipelined ADC . 136
Figure 13-1: High-level description of an FPGA structure . 138
Figure 13-2: Schematic representation of the two layers composing an FPGA . 139
Figure 13-3: Local TMR – single combinatorial logic but triplicated registers . 140
Figure 13-4: RTAX-S/SL/DSP R-cell Implementation of D Flip-Flop Using Voter Gate
Logic . 141
Figure 13-5: Global TMR implemented in an FPGA . 143
Figure 13-6: Physical implementation of global TMR inside an FPGA . 143
Figure 13-7: Large grain TMR . 145
Figure 13-8: Physical implementation of a large grain TMR inside an FPGA . 145
Figure 13-9: BRAM TMR . 147
Figure 13-10: Routing defect within the same module . 149
Figure 13-11: Domain Crossing Event as a consequence of routing defect affecting
two different modules . 149
Figure 13-12: Inserting voters reduces the risk of domain crossing events . 150
Figure 13-13: RoRA’s design flow . 152
Figure 13-14: Hybrid architecture using a fault detection-oriented I-IP . 154
Figure 13-15: Organization of the configuration memory for the Xilinx Virtex family . 156
Figure 13-16: Simple configuration and SEU correction design . 156
Figure 14-1: Temporal redundancy at instruction level . 162
Figure 14-2: Optimized architecture for temporal redundancy applied at instruction
level . 164
Figure 14-3: Example of code. 164
Figure 14-4: Example of code with instruction level redundancy . 165
Figure 14-5: Task-level redundancy . 168
Figure 14-6: Architecture for temporal redundancy applied at task level . 168
Figure 14-7: DMT architecture . 169
Figure 14-8: Scheduling and fault detection in DMT architecture . 170
Figure 14-9: Time redundancy at application level . 172
Figure 15-1: TID for the L1 orbit with indication of the typical shielding range and the
failure regions of commercial and semi-hard components (after [315]) . 176
Figure 15-2: Typical annual mission doses (spherical Al shield) for various orbits, from
ECSS-E-10-04A . 176
Figure 15-3: Example of a dose depth curve (C. Poivey, NSREC 2002 short
course) . 177
Figure 15-4: Figure Contributions of protons, electrons, and bremsstrahlung to total
dose as a function of aluminum shielding. The data were taken after a 139-
day exposure during the Explorer 55 space mission. (After [313]) . 178
Figure 15-5: Block diagram of a LCL . 180
Figure 15-6: Block diagram of a duplex architecture . 182
Figure 15-7: Lockstep architecture . 182
Figure 15-8: UCTM-C/D architecture . 183
Figure 15-9: DT2 hardware architecture . 184
Figure 15-10: Triple Modular Redundancy. 185
Figure 15-11: Full Triple Modular Redundancy . 186
Figure 16-1: Flow chart for fault injections in FPGAs . 194
Figure 16-2: Flow chart of a typical static test . 199
Figure 16-3: Flow chart for a typical dynamic test . 200
Figure 16-4: Example of TID proposed test flow of test vehicle . 202
Figure 16-5: Neutron fluxes in NY City and at LANL . 205
Figure 16-6: Californium-252 fragments energy spectrum (left) and LET spectrum
(right) . 210

Tables
Table 4-1: Summary of single event effects (SEE) as a function of component
technology and family. 30
Table 6-1: Summary of mitigation techniques at manufacturing process level and the
radiation effects they address . 35
Table 6-2: Summary of key characteristics for epitaxial layers. 37
Table 6-3: Summary of key characteristics for silicon on insulator . 40
Table 6-4: Summary of key characteristics for triple wells . 42
Table 6-5: Summary of key characteristics for buried layers . 43
Table 6-6: Impact of thermal oxidation process parameters on TID hardness . 44
Table 6-7: Summary of key characteristics for dry thermal oxidation . 45
Table 6-8: Summary of key characteristics for implantation into oxides . 46
Table 7-1: Summary of mitigation techniques at physical layout level and the radiation
effects they address . 50
Table 7-2: Summary of key characteristics for enclosed layout transistor . 52
Table 7-3: Summary of key characteristics for contacts and guard rings . 55
Table 7-4: Summary of key characteristics for dummy transistors . 57
Table 7-5: Summary of key characteristics for large W/L ration transistors . 57
Table 8-1: Summary of mitigation techniques at analogue design circuit architecture
level and the radiation effects they address . 59
Table 8-2: Summary of key characteristics for node separation and inter-digitation . 62
Table 8-3: Summary of key characteristics for analogue redundancy . 64
Table 8-4:Summary of key characteristics for resistive decoupling . 66
Table 8-5: Summary of key characteristics for filtering . 68
Table 8-6: Summary of key characteristics for modifications in bandwidth, gain,
operating speed and current drive . 71
Table 8-7: Summary of key characteristics for reduction of window of vulnerability . 75
Table 8-8: Summary of known issue for reduction of high impedance nodes . 77
Table 8-9: Summary of key characteristics for differential design . 80
Table 8-10: Summary of key characteristics for dual path hardening . 84
Table 9-1: Summary of mitigation techniques for embedded memories and the
radiation effects they address . 85
Table 9-2: Summary of key characteristics for resistive hardening . 87
Table 9-3: Summary of key characteristics for capacitive hardening. 89
Table 9-4: Summary of key characteristics for IBM hardened memory cell . 91
Table 9-5: Summary of key characteristics for HIT hardened memory cell . 92
Table 9-6: Summary of key characteristics for DICE hardened memory cell . 94
Table 9-7: Summary of key characteristics for NASA-Whitaker hardened memory
cell . 95
Table 9-8: Summary of key characteristics for NASA-Liu hardened memory cell. 97
Table 9-9:Summary of key characteristics for bit-interleaving in memory arrays . 99
Table 9-10: Comparison between state-of-the-art SEU hardened memory cells . 100
Table 11-1: Summary of mitigation techniques at digital design circuit architecture level
and the radiation effects they address . 107
Table 11-2: Summary of key characteristics for spatial redundancy . 113
Table 11-3: Summary of key characteristics for temporal redundancy . 116
Table 11-4: Summary of key characteristics for fail-safe, deadlock-free finite state
machines . 120
Table 11-5: Summary of key characteristics for selective use of logic cells . 121
Table 12-1: Summary of mitigation techniques at System-on-Chip level and the
radiation effects they address . 123
Table 12-2: Error detection and correction capability for some ECC . 125
Table 12-3: Examples of parity check applied to a 7-bit word . 126
Table 12-4: Example of commonly used CRCs .
...