SIST EN 61188-5-2:2004

SLOVENSKI STANDARD
01-marec-2004
Printed boards and printed board assemblies - Design and use - Part 5-2:
Attachment (land/joint) considerations - Discrete components
Printed boards and printed board assemblies - Design and use -- Part 5-2: Attachment
(land/joint) considerations - Discrete components
Leiterplatten und Flachbaugruppen - Konstruktion und Anwendung -- Teil 5-2:
Betrachtungen zur Montage (Anschlussfläche/Verbindung) - Einzelbauelemente
Cartes imprimées et cartes imprimées équipées - Conception et utilisation -- Partie 5-2:
Considérations sur les liaisons pistes-soudures - Composants discrets
Ta slovenski standard je istoveten z: EN 61188-5-2:2003
ICS:
31.180 7LVNDQDYH]MD7,9LQWLVNDQH Printed circuits and boards
SORãþH
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

EUROPEAN STANDARD EN 61188-5-2
NORME EUROPÉENNE
EUROPÄISCHE NORM September 2003

ICS 31.180; 31.190
English version
Printed boards and printed board assemblies -
Design and use
Part 5-2: Attachment (land/joint) considerations -
Discrete components
(IEC 61188-5-2:2003)
Cartes imprimées et cartes imprimées Leiterplatten und Flachbaugruppen -
équipées - Konstruktion und Anwendung
Conception et utilisation Teil 5-2: Betrachtungen zur Montage
Partie 5-2: Considérations sur les liaisons (Anschlussfläche/Verbindung) -
pistes-soudures - Einzelbauelemente
Composants discrets (IEC 61188-5-2:2003)
(CEI 61188-5-2:2003)
This European Standard was approved by CENELEC on 2003-09-01. CENELEC members are bound to
comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European
Standard the status of a national standard without any alteration.

Up-to-date lists and bibliographical references concerning such national standards may be obtained on
application to the Central Secretariat or to any CENELEC member.

This European Standard exists in three official versions (English, French, German). A version in any other
language made by translation under the responsibility of a CENELEC member into its own language and
notified to the Central Secretariat has the same status as the official versions.

CENELEC members are the national electrotechnical committees of Austria, Belgium, Czech Republic,
Denmark, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Lithuania, Luxembourg, Malta,
Netherlands, Norway, Portugal, Slovakia, Spain, Sweden, Switzerland and United Kingdom.

CENELEC
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung

Central Secretariat: rue de Stassart 35, B - 1050 Brussels

© 2003 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.

Ref. No. EN 61188-5-2:2003 E
Foreword
The text of document 91/382/FDIS, future edition 1 of IEC 61188-5-2, prepared by IEC TC 91,
Electronics assembly technology, was submitted to the IEC-CENELEC parallel vote and was approved
by CENELEC as EN 61188-5-2 on 2003-09-01.

This European Standard is to be read in conjunction with EN 61188-5-1:2002.

The following dates were fixed:

– latest date by which the EN has to be implemented
at national level by publication of an identical
national standard or by endorsement (dop) 2004-06-01

– latest date by which the national standards conflicting
with the EN have to be withdrawn (dow) 2006-09-01

Annexes designated "normative" are part of the body of the standard.
In this standard, annex ZA is normative.
Annex ZA has been added by CENELEC.
__________
Endorsement notice
The text of the International Standard IEC 61188-5-2:2003 was approved by CENELEC as a European
Standard without any modification.

In the official version, for Bibliography, the following notes have to be added for the standards indicated:

IEC 60051 NOTE Harmonized as EN 60051 series (not modified).
IEC 61191-1 NOTE Harmonized as EN 61191-1:1998 (not modified).
IEC 61191-2 NOTE Harmonized as EN 61191-2:1998 (not modified).
__________
- 3 - EN 61188-5-2:2003
Annex ZA
(normative)
Normative references to international publications
with their corresponding European publications
This European Standard incorporates by dated or undated reference, provisions from other
publications. These normative references are cited at the appropriate places in the text and the
publications are listed hereafter. For dated references, subsequent amendments to or revisions of any
of these publications apply to this European Standard only when incorporated in it by amendment or
revision. For undated references the latest edition of the publication referred to applies (including
amendments).
NOTE When an international publication has been modified by common modifications, indicated by (mod), the relevant
EN/HD applies.
Publication Year Title EN/HD Year
1) 2)
IEC 60068-2-58 - Environmental testing EN 60068-2-58 1999
Part 2-58: Tests - Test Td: Test
methods for solderability, resistance to
dissolution of metallization and to
soldering heat of surface mounting
devices (SMD)
1) 2)
IEC 60115-1 - Fixed resistors for use in electronic EN 60115-1 2001
(mod) equipment
Part 1: Generic specification
1) 2)
IEC 60286-3 - Packaging of components for automatic EN 60286-3 1998
handling
Part 3: Packaging of surface mount
components on continuous tapes

1) 2)
IEC 60286-4 - Part 4: Stick magazines for electronic EN 60286-4 1998
components encapsulated in packages
of form E and G
1) 2)
IEC 60286-5 - Part 5: Matrix trays EN 60286-5 1997
(mod)
1) 2)
IEC 60286-6 - Part 6: Bulk case packaging for surface EN 60286-6 1998
mounting components
1)
IEC 60384-3 - Fixed capacitors for use in electronic - -
equipment. Part 3: Sectional
specification: Fixed tantalum chip
capacitors
1)
IEC 60384-18 - Part 18: Sectional specification: Fixed - -
aluminium electrolytic chip capacitors
with solid and non-solid electrolyte

1)
Undated reference.
2)
Valid edition at date of issue.

Publication Year Title EN/HD Year
1) 2)
IEC 60384-20 - Part 20: Sectional specification: Fixed EN 60384-20 1999
metallized polyphenylene sulfide film
dielectric surface mount d.c. capacitors

1) 2)
IEC 61188-5-1 - Printed boards and printed board EN 61188-5-1 2002
assemblies - Design and use
Part 5-1: Attachment (land/joint)
considerations - Generic requirements

1) 2)
IEC 61605 - Fixed inductors for use in electronic and EN 61605 1997
telecommunication equipment - Marking
codes
NORME
CEI
INTERNATIONALE IEC
61188-5-2
INTERNATIONAL
Première édition
STANDARD
First edition
2003-06
Cartes imprimées et cartes imprimées équipées –
Conception et utilisation –
Partie 5-2:
Considérations sur les liaisons pistes-soudures –
Composants discrets
Printed boards and printed board assemblies –
Design and use –
Part 5-2:
Attachment (land/joint) considerations –
Discrete components
© IEC 2003 Droits de reproduction réservés ⎯ Copyright - all rights reserved
Aucune partie de cette publication ne peut être reproduite ni No part of this publication may be reproduced or utilized in any
utilisée sous quelque forme que ce soit et par aucun procédé, form or by any means, electronic or mechanical, including
électronique ou mécanique, y compris la photocopie et les photocopying and microfilm, without permission in writing from
microfilms, sans l'accord écrit de l'éditeur. the publisher.
International Electrotechnical Commission, 3, rue de Varembé, PO Box 131, CH-1211 Geneva 20, Switzerland
Telephone: +41 22 919 02 11 Telefax: +41 22 919 03 00 E-mail: inmail@iec.ch  Web: www.iec.ch
CODE PRIX
XA
Commission Electrotechnique Internationale PRICE CODE
International Electrotechnical Commission
ɆɟɠɞɭɧɚɪɨɞɧɚɹɗɥɟɤɬɪɨɬɟɯɧɢɱɟɫɤɚɹɄɨɦɢɫɫɢɹ
Pour prix, voir catalogue en vigueur
For price, see current catalogue

61188-5-2 © IEC:2003 – 3 –
CONTENTS
FOREWORD . 9
INTRODUCTION .13
1 Scope .15
2 Normative references.15
3 Packaging.17
4 Fixed rectangular chip resistors .17
4.1 Introductory remark .17
4.2 Component description .17
4.3 Component dimensions .19
4.4 Solder joint fillet design .21
4.5 Land pattern dimensions.25
5 Fixed cylindrical chip resistors .29
5.1 Introductory remark .29
5.2 Component description .29
5.3 Component dimensions .31
5.4 Solder joint fillet design .31
5.5 Land pattern dimensions.35
6 Fixed multilayer ceramic chip capacitors.39
6.1 Introductory remark .39
6.2 Component description .39
6.3 Component dimensions .43
6.4 Solder joint fillet design .43
6.5 Land pattern dimensions.47
7 Fixed tantalum chip capacitors.51
7.1 Introductory remark .51
7.2 Component description .51
7.3 Component dimensions .53
7.4 Solder joint fillet design .53
7.5 Land pattern dimensions.57
8 Fixed aluminium electrolytic chip capacitors with non-solid electrolyte
(vertical type).61
8.1 Introductory remark .61
8.2 Component description .61
8.3 Component dimensions .63
8.4 Solder joint fillet design .65
8.5 Land pattern dimensions.67
9 Fixed aluminium electrolytic chip capacitors with non-solid electrolyte
(horizontal type).71
9.1 Introductory remark .71
9.2 Component description .71
9.3 Component dimensions .73
9.4 Solder joint fillet design .75
9.5 Land pattern dimensions.77

61188-5-2 © IEC:2003 – 5 –
10 Fixed film chip capacitors .81
10.1 Introductory remark .81
10.2 Component description .81
10.3 Component dimensions .83
10.4 Solder joint fillet design .85
10.5 Land pattern dimensions.42
11 Fixed chip inductors (multilayer type).91
11.1 Introductory remark .91
11.2 Component description .91
11.3 Component dimensions .93
11.4 Solder joint fillet design .93
11.5 Land pattern dimensions.97
12 Fixed chip inductors (wire wound type) .101
13 SC-59/TO-236 – Transistors .101
14 SC-62/TO-243 – Transistors .101
15 SC-61/TO-253 – Transistors .101
16 SC-73 – Diodes .101
17 SC-63/TO-252 – Transistors .101
18 SC-77 – Transistors.101
Bibliography.103
Figure 1 – Packaging .17
Figure 2 – Fixed rectangular chip resistor construction.19
Figure 3 – Fixed rectangular chip resistor dimensions .21
Figure 4 – Solder joint protrusion .25
Figure 5 – Fixed rectangular chip resistor land pattern dimensions .27
Figure 6 – Fixed cylindrical chip resistor construction.29
Figure 7 – Fixed cylindrical chip resistor dimensions .31
Figure 8 – Solder joint protrusion .35
Figure 9 – Fixed cylindrical chip resistor land pattern dimensions .37
Figure 10 – Fixed multilayer ceramic chip capacitor construction .39
Figure 11 – Fixed multilayer ceramic chip capacitor component dimensions.43
Figure 12 – Solder joint protrusion .47
Figure 13 – Fixed multilayer ceramic chip capacitor land pattern dimensions .49
Figure 14 – Fixed tantalum chip capacitor construction .51
Figure 15 – Fixed tantalum chip capacitor component dimensions.53
Figure 16 – Solder joint protrusion .57
Figure 17 – Fixed tantalum chip capacitor land pattern dimensions .59

61188-5-2 © IEC:2003 – 7 –
Figure 18 – Fixed aluminium electrolytic chip capacitor with non-solid electrolyte
(vertical type) construction .61
Figure 19 – Fixed aluminium electrolytic chip capacitor (vertical type) dimensions .63
Figure 20 – Solder joint protrusion .67
Figure 21 – Fixed aluminium electrolytic chip capacitor (vertical type) land pattern
dimensions.71
Figure 22 – Fixed aluminium electrolytic chip capacitor with non-solid electrolyte
(horizontal type) construction .71
Figure 23 – Fixed aluminium electrolytic chip capacitor (horizontal type) dimensions .73
Figure 24 – Solder joint protrusion .77
Figure 25 – Fixed aluminium electrolytic chip capacitor (horizontal type)
land pattern dimensions .79
Figure 26a – Stacked type.38
Figure 26b – Wound type .81
Figure 27a – Stacked type.83
Figure 27b – Wound type .39
Figure 28 – Solder joint protrusion .87
Figure 29 – MPPS film chip capacitor land pattern dimensions.89
Figure 30 – Fixed chip inductor construction .91
Figure 31 – Fixed chip inductor (multilayer type) component dimensions.93
Figure 32 – Solder joint protrusion .97
Figure 33 – Fixed chip inductor land pattern dimensions .99

61188-5-2 © IEC:2003 – 9 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
PRINTED BOARDS AND PRINTED BOARD ASSEMBLIES –
DESIGN AND USE –
Part 5-2: Attachment (land/joint) considerations –
Discrete components
FOREWORD
1) The IEC (International Electrotechnical Commission) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, the IEC publishes International Standards. Their preparation is
entrusted to technical committees; any IEC National Committee interested in the subject dealt with may
participate in this preparatory work. International, governmental and non-governmental organizations liaising
with the IEC also participate in this preparation. The IEC collaborates closely with the International
Organization for Standardization (ISO) in accordance with conditions determined by agreement between the
two organizations.
2) The formal decisions or agreements of the IEC on technical matters express, as nearly as possible, an
international consensus of opinion on the relevant subjects since each technical committee has representation
from all interested National Committees.
3) The documents produced have the form of recommendations for international use and are published in the form
of standards, technical specifications, technical reports or guides and they are accepted by the National
Committees in that sense.
4) In order to promote international unification, IEC National Committees undertake to apply IEC International
Standards transparently to the maximum extent possible in their national and regional standards. Any
divergence between the IEC Standard and the corresponding national or regional standard shall be clearly
indicated in the latter.
5) The IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with one of its standards.
6) Attention is drawn to the possibility that some of the elements of this International Standard may be the subject
of patent rights. The IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 61188-5-2 has been prepared by IEC technical committee 91:
Electronics assembly technology.
The text of this standard is based on the following documents:
FDIS Report on voting
91/382/FDIS 91/397/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
This International Standard is to be read in conjunction with IEC 61188-5-1:2002.

61188-5-2 © IEC:2003 – 11 –
This standard forms Part 5-2 of IEC 61188 which is published under the general title Printed
boards and printed board assemblies – Design and use :
Part 5-1: Attachment (land/joint) considerations – Generic requirements
Part 5-2: Attachment (land/joint) considerations – Discrete components
Part 5-3: Attachment (land/joint) considerations – Gull-wing leads, two sides
Part 5-4: Attachment (land/joint) considerations – J leads, two sides
Part 5-5: Attachment (land/joint) considerations – Components with gull-wing leads,
four sides
Part 5-6: Attachment (land/joint) considerations – J leads, four sides
Part 5-7: Attachment (land/joint) considerations – Post (DIP) leads, two sides
The committee has decided that the contents of this publication will remain unchanged
until 2004. At this date, the publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition, or
• amended.
———————
At the time of writing, some of these parts are still under consideration.

61188-5-2 © IEC:2003 – 13 –
INTRODUCTION
This part of IEC 61188 covers land patterns for discrete components such as chip resistors,
chip capacitors, and various diode and transistor types.
The proposed land pattern dimensions are based upon the fundamental tolerance calculation
combined with the given land protrusions and courtyard excesses (see IEC 61188-5-1,
Generic requirements). The courtyard includes all issues relating to normal manufacturing
requirements.
The land pattern dimensions given in this standard are generally applicable for reflowed
solder paste processes. For immersion soldering processes (e.g. wave, jet, drag soldering),
lands may have to be modified to prevent shadowing and shorting (e.g. by extending land
length parallel to the direction of motion of the board and/or provision of solder thieves).
This standard offers a threefold land pattern dimensioning (levels 1, 2 and 3) on the basis of
a threefold set of land protrusions and courtyard excesses: maximum (max.), median (mdn)
and minimum (min.). Each land pattern has been assigned an identification number to indicate
the characteristics of the specific robustness of the land patterns. Users also have the
opportunity to organize the information so that it is most useful for their particular design.
This standard assumes that land dimensions are always larger than component termination or
lead outlines. If a user has good reason to use solder resist to limit wetting on a land, or to
use lands smaller than component terminations, or to apply a concept different from that of
IEC 61188-5-1, then this standard may not apply.
It is the responsibility of the user to verify the SMD land patterns used for achieving an
undisturbed mounting process, including testing, and an ensured reliability for the product
stress conditions in use.
Dimensions of the components listed in this standard are those available on the market and
are for reference only.
61188-5-2 © IEC:2003 – 15 –
PRINTED BOARDS AND PRINTED BOARD ASSEMBLIES –
DESIGN AND USE –
Part 5-2: Attachment (land/joint) considerations –
Discrete components
1 Scope
This part of IEC 61188 provides information on land pattern geometries used for the surface
attachment of discrete electronic components.
The purpose of this standard is to provide the appropriate size, shape and tolerances of
surface mount land patterns to ensure sufficient area for the appropriate solder fillet, and also
allow for inspection, testing and rework of resulting solder joints.
Each clause contains a specific set of clearly presented criteria providing information on the
component, the component dimensions, the solder joint design and the land pattern
dimensions.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 60068-2-58, Environmental testing – Part 2-58: Tests – Test Td: Test methods for
solderability, resistance to dissolution of metallization and to soldering heat of surface
mounting devices (SMD)
IEC 60115-1, Fixed resistors for use in electronic equipment – Part 1: General specification
IEC 60286-3, Packaging of components for automatic handling – Part 3: Packaging of
leadless components on continuous tapes
IEC 60286-4, Packaging of components for automatic handling – Part 4: Stick magazines for
electric components encapsulated in packages of form E and G
IEC 60286-5, Packaging of components for automatic handling – Part 5: Matrix trays
IEC 60286-6, Packaging of components for automatic handling – Part 6: Bulk case packaging
for surface mounting compounds
IEC 60384-3, Fixed capacitors for use in electronic equipment – Part 3: Sectional
specification: Fixed Tantalum chip capacitors
IEC 60384-18, Fixed capacitors for use in electronic equipment – Part 18: Sectional
specification – Fixed aluminium electrolytic chip capacitors with solid and non-solid electrolyte

61188-5-2 © IEC:2003 – 17 –
IEC 60384-20, Fixed capacitors for use in electronic equipment – Part 20: Sectional
specification – Fixed metallized polyphenylene sulfide film dielectric chip d.c. capacitors
IEC 61188-5-1, Printed boards and printed board assemblies – Design and use – Part 5-1:
Attachment (land/joint) considerations – Generic requirements
IEC 61605, Fixed inductors for use in electronic and telecommunication equipment – Marking
codes
3 Packaging
The following IEC standards shall be referred to:
− IEC 60286-3 (see figure 1);
− IEC 60286-4;
− IEC 60286-5;
− IEC 60286-6.
Top cover tape
Sprocket hole
Component cavity
Embossed carrier tape
Sprocket hole
Embossed carrier tape
Component cavity
IEC  1662/03
Figure 1 – Packaging
4 Fixed rectangular chip resistors
4.1 Introductory remark
This clause specifies the dimensions of components and land patterns for fixed rectangular
chip resistors, together with an analysis of tolerance and solder joint assumptions for the land
pattern dimensions.
4.2 Component description
A variety of values exist for the dimensions of resistors. The following subclauses describe
the most common types.
61188-5-2 © IEC:2003 – 19 –
4.2.1 Basic construction
Figure 2 shows a typical construction example. The resistive material is coated to a ceramic
substrate and terminated symmetrically at both ends with a "wrap around" metal U-shaped
band. The resistive material is face-up. Since most equipment uses a vacuum-type pick-up
head, it is important that the surface of the resistor is made flat, otherwise vacuum pick-up
might be difficult.
Passivation
Resistor element
Alumina substrate
Wrap-around
Inner electrode
termination
IEC  1663/03
Figure 2 – Fixed rectangular chip resistor construction
4.2.2 Termination materials
Electrodes should be coated with a material suited to the solder and method of soldering to be
used.
The terminations shall be symmetrical, and shall not have nodules, lumps, protrusions, etc.,
that degrade the symmetry or dimensional tolerances of the part. The end termination shall
cover the end of a component, and shall extend out to the top and bottom of the component.
Solder finish applied over precious metal electrodes shall have a diffusion-barrier layer
between the electrode metallization and the solder finish. The barrier layer material should be
nickel or a similar metal effective as a diffusion barrier.
4.2.3 Marking
Chip resistors are generally not marked on the body. If some marking can be applied, the chip
resistor shall be clearly marked with the rated resistance, and as many of the remaining items
as possible from 2.4 of IEC 60115-1.
4.2.4 Carrier package format
Refer to IEC 60286-3.
4.2.5 Solderability and resistance to dissolution of metallization and to soldering heat
Refer to IEC 60068-2-58.
4.3 Component dimensions
Figure 3 shows the component dimensions for fixed rectangular chip resistors.

61188-5-2 © IEC:2003 – 21 –
L
T
W
S
H
IEC  1664/03
Dimensions in millimetres
LS W T H
Component
identifier
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
1005 0,95 1,05 0,35 0,75 0,45 0,55 0,15 0,30 0,30 0,40
1608 1,50 1,70 0,50 1,50 0,70 0,90 0,10 0,50 0,35 0,55
2012 1,90 2,10 0,70 1,70 1,15 1,35 0,20 0,60 0,45 0,65
3216 3,00 3,40 1,50 2,90 1,45 1,75 0,25 0,75 0,45 0,65
3225 3,00 3,40 1,50 2,90 2,30 2,70 0,25 0,75 0,45 0,65
5025 4,80 5,20 3,10 4,50 2,30 2,70 0,35 0,85 0,35 0,75
6332 6,10 6,50 4,40 5,80 3,00 3,40 0,35 0,85 0,35 0,75
Figure 3 – Fixed rectangular chip resistor dimensions
4.4 Solder joint fillet design
Figure 4 shows the shape and dimensions of the solder fillet after the soldering process. The
minimum, median and maximum dimensions of each of toe, heel, and side fillet are
determined by taking into consideration solder joint reliability and also quality and productivity
in the parts mount process. Designing land patterns needs consideration of three factors in
accuracy: parts dimensions accuracy (C), parts mount accuracy on PWBs (P) and land shape
accuracy on PWBs (F), in addition to fillet dimensions. The formulae to obtain the tolerance
resulting from these factors are as follows:
a. Design consideration when soldered without self-alignment effect (level 1)
In flow soldering process, there is no self-alignment effect. Thus, the formulae cannot be
simplified but remain the same as follows:
2 2 2
Z = L + 2J + T T = + +
T F P C
max min T max T L1 L1 L
2 2 2
G = S – 2J – T T = + +
H F P C
min max H max H L1 L1 S
2 2
X = W + 2J + T T = + +
S F P C
max min S max S L1 L1 W
61188-5-2 © IEC:2003 – 23 –
b. Design consideration when soldered without self-alignment effect (level 2)
2 2 2
Z = L + 2J + T
T = + +
max min Tmdn T
T F P C
L2 L2 L
2 2 2
G = S – 2J – T T = + +
H F P C
min max Hmdn H L2 L2 S
2 2 2
X = W + 2J + T T = + +
S F P C
max min Smdn S L2 L W
c. Design consideration when soldered with self-alignment effect (level 3)
2 2 2
Z = L + 2J + T
max min Tmin T T = + +
T F P C
L3 L3 L
2 2 2
G = S – 2J –T T = + +
H F P C
L3 L3 S
min max Hmin H
2 2 2
X = W + 2J + T T = + +
S F P C
L3 L3 W
max min Smin S
In a reflow soldering process, there is a self-alignment effect because adhesives are not used
to hold components. In the surface mount process of reflow soldering, parts mount
displacement and the land shape accuracy on PWBs, when soldered, can be corrected by
self-alignment effect (therefore factor P and F can be regarded as 0). Thus, the formulae can
be simplified as follows:
T = C , Z = L + 2J + C = L + 2J
L
T L max min T min max Tmin
T = C , G = S – 2J – C = S – 2J
H S min max H min S min Hmin
T = C , X = W + 2J + C = W + J
S W max min S min W max Smin
Any tolerance other than the above may be used depending on the soldering strength
required, the capability of the production process used, etc.

61188-5-2 © IEC:2003 – 25 –
Side fillet
Toe fillet Heel fillet
J
S
J J
T H
G
min. X
max.
Z
max.
IEC  1665/03
NOTE Where resistors have no side termination material, the 'side fillet' or J dimension refers to the tapered
S
portion of the end fillet.
Dimensions in millimetres
Solder joint
Tolerance
assumptions
Toe Heel Side
Component
identifier
FP J J J
T H S
L-1 L-2 L-3 L-1 L-2 L-3 C Max. Mdn Min. C Max. Mdn Min. C Max. Mdn Min.
L S W
1005 0,3 0,2 0,1 0,2 0,15 0,1 0,1 0,6 0,4 0,2 0,4 0 0 0 0,1 0 0 0
1608 0,3 0,2 0,1 0,4 0,2 0,1 0,2 0,6 0,4 0,2 1 0 0 0 0,2 0 0 0
2012 0,3 0,2 0,1 0,4 0,2 0,1 0,2 0,6 0,4 0,2 1 0 0 0 0,2 0 0 0
3216 0,3 0,2 0,1 0,4 0,2 0,1 0,4 0,6 0,4 0,2 1,4 0 0 0 0,3 0 0 0
3225 0,3 0,2 0,1 0,4 0,2 0,1 0,4 0,6 0,4 0,2 1,4 0 0 0 0,4 0 0 0
5025 0,3 0,2 0,1 0,4 0,2 0,1 0,4 0,6 0,4 0,2 1,4 0 0 0 0,4 0 0 0
6332 0,3 0,2 0,1 0,4 0,2 0,1 0,4 0,6 0,4 0,2 1,4 0 0 0 0,4 0 0 0
Figure 4 – Solder joint protrusion
4.5 Land pattern dimensions
Figure 5 shows the land pattern dimensions for fixed rectangular chip resistors for reflow and
flow soldering. These values are calculated based on the formulae for the solder joint fillet
design given in 4.4. G values for chip resistor of 1005 are larger than the calculated values
min
to prevent the solder from forming a bridge between neighbouring lands.
The courtyard is calculated using the following formulae and rounded up (round-up factor is
nearest 0,05 for min. and 0,5 for max).
2 2
CY = {whichever is larger [L + + + ] or [Z]}
F P C
1 min L
+ (courtyard excess × 2)
2 2
CY = {whichever is larger [W + + + ] or [X]}
F P
C
2 min W
+ (courtyard excess × 2)
61188-5-2 © IEC:2003 – 27 –
CY
C
Y G
Z
IEC  1666/03
Level 1 Dimensions in millimetres
Pattern Component
ZG X Y C CY CY
1 2
identifier identifier
2010M 1005 2,55 0,5 0,85 1,05 1,55 4 2
2011M 1608 3,25 0,5 1,25 1,4 1,9 5 3
2012M 2012 3,65 0,55 1,7 1,55 2,1 5 3
2013M 3216 4,85 1,6 2,05 1,65 3,25 6 4
2014M 3225 4,85 1,6 2,95 1,65 3,25 6 4
2015M 5025 6,65 3,2 2,95 1,75 4,95 8 4
2016M 6332 7,95 4,5 3,65 1,75 6,25 9 5
Level 2
Pattern Component
ZG X Y C CY CY
1 2
identifier identifier
2010N 1005 2,05 0,5 0,75 0,8 1,3 2,6 1,3
2011N 1608 2,65 0,5 1,05 1,1 1,6 3,2 1,6
2012N 2012 3,05 0,65 1,5 1,2 1,85 3,6 2
2013N 3216 4,3 1,65 1,9 1,35 3 4,8 2,4
2014N 3225 4,3 1,65 2,8 1,35 3 4,8 3,3
2015N 5025 6,1 3,25 2,8 1,45 4,7 6,6 3,3
2016N 6332 7,4 4,55 3,5 1,45 6 7,9 4
Level 3
Pattern Component
ZG X Y C CY CY
1 2
identifier identifier
2010L 1005 1,45 0,5 0,55 0,5 1,0 1,6 0,8
2011L 1608 2,1 0,5 0,9 0,8 1,3 2,2 1,1
2012L 2012 2,5 0,7 1,35 0,9 1,6 2,6 1,5
2013L 3216 3,8 1,5 1,75 1,15 2,65 3,9 1,9
2014L 3225 3,8 1,5 2,7 1,15 2,65 3,9 2,9
2015L 5025 5,6 3,1 2,7 1,25 4,35 5,7 2,9
2016L 6332 6,9 4,4 3,4 1,25 5,65 7,0 3,6
Figure 5 – Fixed rectangular chip resistor land pattern dimensions
X
CY
61188-5-2 © IEC:2003 – 29 –
5 Fixed cylindrical chip resistors
5.1 Introductory remark
This clause specifies the dimensions of components and land patterns for fixed cylindrical
chip resistors, together with an analysis of tolerance and solder joint assumptions for the land
pattern dimensions.
5.2 Component description
A variety of values exist for the dimensions of resistors. The following subclauses describe
the most common types.
5.2.1 Basic construction
Figure 6 shows a typical construction example.
Resistor element
Insulative coating
End cap
Colour code
Ceramic core
Spiraling turns
IEC  1667/03
Figure 6 – Fixed cylindrical chip resistor construction
5.2.2 Termination materials
Electrodes should be coated with a material suited to the solder and method of soldering to be
used.
The terminations shall be symmetrical and shall not have nodules, lumps, protrusions, etc.
that degrade the symmetry or dimensional tolerances of the part. The end termination shall
cover the ends of the components and shall extend around the entire periphery.
5.2.3 Marking
Chip resistors are generally not marked on the body. If some marking can be applied, the chip
resistor shall be clearly marked with the rated resistance, and as many of the remaining items
as possible from 2.4 of IEC 60115-1.

61188-5-2 © IEC:2003 – 31 –
5.2.4 Carrier package format
Refer to IEC 60286-3 or IEC 60286-6.
5.2.5 Solderability and resistance to dissolution of metallization and to soldering heat
Refer to IEC 60068-2-58.
5.3 Component dimensions
Figure 7 shows the component dimensions for fixed cylindrical chip resistors.
S
L
IEC  1668/03
Dimensions in millimetres
LS W T
Component
identifier
Min. Max Min. Max. Min. Max. Min. Max.
1610 1,50 1,65 0,50 1,35 0,95 1,15 0,15 0,50
2012 1,90 2,10 0,60 1,50 1,15 1,35 0,30 0,65
3514 3,30 3,70 1,10 3,10 1,30 1,50 0,30 1,10
5922 5,70 6,10 2,70 5,10 2,10 2,30 0,50 1,50
Figure 7 – Fixed cylindrical chip resistor dimensions
5.4 Solder joint fillet design
Figure 8 shows the shape and dimensions of the solder fillet after soldering process. The
minimum, median and maximum dimensions of each of toe, heel, and side fillet are
determined by taking into consideration solder joint reliability, and also quality and
productivity in parts mount process. Designing land patterns needs consideration of three
factors in accuracy: parts dimensions accuracy (C), parts mount accuracy on PWBs (P) and
land shape accuracy on PWBs (F), in addition to fillet dimensions. The formulae to obtain the
tolerance resulted from these factors are as follows:
a. Design consideration when soldered without self-alignment effect (level 1)
In flow soldering process, there is no self-alignment effect. Thus, the formulae cannot be
simplified but remain the same as follows:
2 2 2
Z = L + 2J + T T = + +
C
FL1 PL1 L
max min T max T T
2 2 2
G = S – 2J – T T = + +
F P C
L1 L1 S
min max H max H H
2 2 2
X = W + 2J + T T = + +
F P C
L1 L1 W
max min S max S S
∅W
61188-5-2 © IEC:2003 – 33 –
b. Design consideration when soldered without self-alignment effect (level 2)
2 2 2
Z = L + 2J + T T = + +
F P C
max min T mdn T T L2 L2 L
2 2 2
G = S – 2J – T T = + +
F P C
min max H mdn H H L2 L2 S
2 2 2
X = W + 2J + T T = + +
F P C
max min S mdn S S L2 L2 W
c. Design consideration when soldered with self-alignment effect (level 3)
2 2 2
Z = L + 2J + T T = + +
F P C
L3 L3 L
max min Tmin T T
2 2 2
G = S – 2J – T T = + +
F P C
L3 L3 S
min max Hmin H H
2 2 2
X = W + 2J + T T = + +
F P C
L3 L3 W
max min Smin S S
In reflow soldering process, there is a self-alignment effect because adhesives are not used
to hold components. In the surface mount process of reflow soldering, parts mount
displacement and the land shape accuracy on PWBs, when soldered, can be corrected by
self-alignment effect (therefore factor P and F can be regarded as 0). Thus, the formulae can
be simplified as follows:
T = C , Z = L + 2J + C = L + 2J
T L max min T min L max T min
T = C , G = S – 2J – C = S – 2J
H S min max H min S min H min
T = C , X = W + 2J + C = W + 2J
S W max min S min W max S min
Any tolerance other than the above may be used depending on the soldering strength
required, the capability of the production process used, etc.

61188-5-2 © IEC:2003 – 35 –
J
S
J J
T H
Z
min.
X
max.
Z
max.
IEC  1669/03
Dimensions in millimetres
Tolerance Solder joint
assumptions
Toe Heel Side
Component
identifier
FP J J J
T H S
C
L-1 L-2 L-3 L-1 L-2 L-3 C Max. Mdn Min. Max. Mdn Min. C Max. Mdn Min.
S
L W
1610 0,3 0,2 0,1 0,4 0,2 0,1 0,15 1 0,4 0,2 0,85 0,2 0,1 0 0,2 0,2 0,1 0
2012 0,3 0,2 0,1 0,4 0,2 0,1 0,2 1 0,4 0,2 0,9 0,2 0,1 0 0,2 0,2 0,1 0
3514 0,3 0,2 0,1 0,4 0,2 0,1 0,4 1 0,4 0,2 2 0,2 0,1 0 0,2 0,2 0,1 0
5922 0,3 0,2 0,1 0,4 0,2 0,1 0,4 1 0,4 0,2 2,4 0,2 0,1 0 0,2 0,2 0,1 0
Figure 8 – Solder joint protrusion
5.5 Land pattern dimensions
Figure 9 shows the land pattern dimensions for fixed cylindrical chip resistors for reflow and
flow soldering. These values are calculated based on the formulae for the solder joint fillet
design given in 5.4.
The courtyard is calculated using the following formulae and rounded up (round-up factor is
nearest 0,05 for min. and 0,5 for max.).
2 2
CY = {whichever is larger [L + F + P + ] or [Z]}
C
L
1 min
+ (courtyard excess × 2)
2 2 2
CY = {whichever is larger [W + + + ] or [X]}
F P C
2 min W
+ (courtyard excess × 2)
61188-5-2 © IEC:2003 – 37 –
CY
C
Y G
Z
IEC  1670/03
Level 1 Dimensions in millimetres
Pattern Component
ZG X Y C CY CY
1 2
identifier identifier
2030M 1610 4,05 0,5 1,9 1,8 2,3 6 3
2031M 2012 4,45 0,5 2,1 2,0 2,5 6 4
2032M 3514 5,95 1,2 2,25 2,4 3,6 7 4
2033M 5922 8,35 3,1 3,05 2,65 5,75 10 5
Level 2
Pattern Component
ZG X Y C CY CY
1 2
identifier identifier
2030N 1610 2,65 0,5 1,3 1,1 1,6 3,2 1,8
2031N 2012 3,05 0,5 1,5 1,3 1,8 3,6 2,0
2032N 3514 4,6 1,5 1,65 1,55 3,05 5,1 2,2
2033N 5922 7,0 3,35 2,45 1,85 5,2 7,5 3,0
Level 3
Pattern Component
ZG X Y C CY CY
1 2
identifier identifier
2030L 1610 2,05 0,5 1,15 0,8 1,3 2,2 1,3
2031L 2012 2,5 0,6 1,35
...