SIST EN 61188-5-1:2003

SLOVENSKI SIST EN 61188-5-1:2003

STANDARD
april 2003
Printed boards and printed board assemblies - Design and use - Part 5-1:
Attachment (land/joint) considerations - Generic requirements
ICS 31.180 Referenčna številka
©  Standard je založil in izdal Slovenski inštitut za standardizacijo. Razmnoževanje ali kopiranje celote ali delov tega dokumenta ni dovoljeno

NORME CEI
INTERNATIONALE IEC
61188-5-1
INTERNATIONAL
Première édition
STANDARD
First edition
2002-07
Cartes imprimées et cartes imprimées équipées –
Conception et utilisation –
Partie 5-1:
Considérations sur les liaisons pistes-soudures –
Prescriptions génériques
Printed boards and printed board assemblies –
Design and use –
Part 5-1:
Attachment (land/joint) considerations –
Generic requirements
© IEC 2002 Droits de reproduction réservés ⎯ Copyright - all rights reserved
Aucune partie de cette publication ne peut être reproduite ni No part of this publication may be reproduced or utilized in any
utilisée sous quelque forme que ce soit et par aucun procédé, form or by any means, electronic or mechanical, including
électronique ou mécanique, y compris la photocopie et les photocopying and microfilm, without permission in writing from
microfilms, sans l'accord écrit de l'éditeur. the publisher.
International Electrotechnical Commission, 3, rue de Varembé, PO Box 131, CH-1211 Geneva 20, Switzerland
Telephone: +41 22 919 02 11 Telefax: +41 22 919 03 00 E-mail: inmail@iec.ch  Web: www.iec.ch
CODE PRIX
XB
Commission Electrotechnique Internationale PRICE CODE
International Electrotechnical Commission
ɆɟɠɞɭɧɚɪɨɞɧɚɹɗɥɟɤɬɪɨɬɟɯɧɢɱɟɫɤɚɹɄɨɦɢɫɫɢɹ
Pour prix, voir catalogue en vigueur
For price, see current catalogue

61188-5-1 © IEC:2002 – 3 –
CONTENTS
FOREWORD .11
1 Scope and object .15
2 Normative references.15
3 Terms and definitions.17
4 Design requirements .29
4.1 General .29
4.1.1 Classification .31
4.1.2 Land pattern determination.31
4.2 Dimensioning systems .33
4.2.1 Component tolerancing .35
4.2.2 Land tolerancing .43
4.2.3 Fabrication allowances .43
4.2.4 Assembly tolerancing .43
4.2.5 Dimension and tolerance analysis.45
4.3 Design producibility.61
4.3.1 SMT land pattern.63
4.3.2 Standard component selection .63
4.3.3 Circuit substrate development .63
4.3.4 Assembly considerations .63
4.3.5 Provision for automated test.63
4.3.6 Documentation for SMT.63
4.4 Environmental constraint.63
4.4.1 Moisture sensitive components.63
4.4.2 End-use environment considerations .65
4.5 Design rules.67
4.5.1 Component spacing .67
4.5.2 Single- and double-sided board assembly.71
4.5.3 Solder paste stencil.71
4.5.4 Component stand-off height for cleaning .71
4.5.5 Fiducial marks.73
4.5.6 Conductors .79
4.5.7 Via guidelines .81
4.5.8 Standard fabrication allowances .85
4.5.9 Panelization .89
4.6 Outer layer finishes .95
4.6.1 Solder-mask finishes.95
4.6.2 Solder-mask clearances .95
4.6.3 Land-pattern finishes.97
5 Quality and reliability validation .97
5.1 Validation techniques .97
6 Testability .99
6.1 Five types of testing .99
6.1.1 Bare-board test .99
6.1.2 Assembled board test.101

61188-5-1 © IEC:2002 – 5 –
6.2 Nodal access .101
6.2.1 Test philosophy.101
6.2.2 Test strategy for bare boards .103
6.3 Full nodal access for assembled board.103
6.3.1 In-circuit test accommodation.105
6.3.2 Multi-probe testing .105
6.4 Limited nodal access .105
6.5 No nodal access .107
6.6 Clam-shell fixtures impact .107
6.7 Printed board test characteristics .107
6.7.1 Test land pattern spacing .107
6.7.2 Test land size and shape.107
6.7.3 Design for test parameters .109
7 Printed board structure types.111
7.1 General considerations .115
7.1.1 Categories .117
7.1.2 Thermal expansion mismatch.117
7.2 Organic base material .117
7.3 Non-organic base materials.117
7.4 Alternative PB structures.117
7.4.1 Supporting-plane PB structures .117
7.4.2 High-density PB technology.117
7.4.3 Discrete-wire interconnect .119
7.4.4 Constraining core structures.119
7.4.5 Porcelainized metal (metal core) structures .119
8 Assembly considerations for surface-mount technology (SMT).119
8.1 SMT assembly process sequence .119
8.2 Substrate preparation.121
8.2.1 Adhesive application .121
8.2.2 Conductive adhesive .123
8.2.3 Solder paste application .123
8.2.4 Solder preforms .123
8.3 Component placement .123
8.3.1 Component data transfer.123
8.4 Soldering processes.125
8.4.1 Wave soldering .125
8.4.2 Vapour-phase soldering .127
8.4.3 IR reflow .129
8.4.4 Hot air/gas convection.129
8.4.5 Laser reflow soldering .129
8.5 Cleaning .129
8.6 Repair/rework .131
8.6.1 Re-use of removed components .131
8.6.2 Heatsink effects .131
8.6.3 Dependence on printed board material type.133
8.6.4 Dependence on copper land and conductor layout .133
8.6.5 Selection of suitable rework equipment.133
8.6.6 Dependence on assembly structure and soldering processes.133

61188-5-1 © IEC:2002 – 7 –
Annex A (informative) Test patterns – Process evaluations .135
Annex B (informative) Abbreviations .141
Figure 1 – Profile tolerancing method.33
Figure 2 – Example of 3216 capacitor dimensioning for optimum solder fillet condition.37
Figure 3 – Profile dimensioning of gull-wing leaded SOIC.39
Figure 4 – Pitch for multiple leaded component.49
Figure 5 – Courtyard boundary area condition.59
Figure 6 – Component orientation for wave-solder applications .67
Figure 7 – Alignment of similar components.69
Figure 8 – Panel/local fiducials .73
Figure 9 – Local and global fiducials .75
Figure 10 – Fiducial locations on a printed board .75
Figure 11 – Fiducial clearance requirements.77
Figure 12 – Surface mounting geometries.79
Figure 13 – Conductor routing capability test pattern.81
Figure 14 – Land-pattern-to-via relationship .83
Figure 15 – Examples of via positioning concepts .83
Figure 16 – Conductor description .87
Figure 17 – Examples of modified landscapes .89
Figure 18 – Typical copper glass laminate panel .91
Figure 19 – Conductor clearance for V-groove scoring .91
Figure 20 – Breakaway (routed pattern) with routed slots .93
Figure 21 – Routed slots.93
Figure 22 – Gang solder mask window.95
Figure 23 – Pocket solder mask window .97
Figure 24 – Component temperature limits.99
Figure 25 – Test via grid concepts .105
Figure 26 – General relationship between test contact size and test probe misses.109
Figure 27 – Test probe feature distance from component.111
Figure 28 – Typical process flow for through-hole/surface-mount assembly.121
Figure 29 – Typical process flow for full surface-mount type 1b and 2b surface-mount
technology.121
Figure A.1 – General description of process validation contact pattern and interconnect.135
Figure A.2 – Photoimage of IPC-A-49 test board for primary side .137
Table 1 – Tolerance analysis elements for chip devices .51
Table 2 – Flat ribbon L and gull-wing leads (greater than 0,625 mm pitch).51
Table 3 – Flat ribbon L and gull-wing leads (less than or equal to 0,625 mm pitch) .53
Table 4 – Round or flattened (coined) leads.53
Table 5 – J leads.53
Table 6 – Rectangular or square-end components (ceramic capacitors and resistors) .53
Table 7 – Cylindrical end cap terminations (MELF).55
Table 8 – Bottom only terminations .55

61188-5-1 © IEC:2002 – 9 –
Table 9 – Leadless chip carrier with castellated terminations .55
Table 10 – Butt joints.55
Table 11 – Inward flat ribbon L and gull-wing leads (tantalum capacitors).57
Table 12 – Flat lug leads .57
Table 13 – Worst-case use environments for surface-mounted electronics and
recommended accelerated testing for surface-mount solder attachments by most
common use categories.65
Table 14 – Conductor width tolerances .87
Table 15 – Feature location accuracy.87
Table 16 – Printed board structure comparison .111
Table 17 – PB structure selection considerations .115
Table 18 – PB structure material properties .115

61188-5-1 © IEC:2002 – 11 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
___________
PRINTED BOARDS AND PRINTED BOARD ASSEMBLIES –
DESIGN AND USE –
Part 5-1: Attachment (land/joint) considerations –
Generic requirements
FOREWORD
1) The IEC (International Electrotechnical Commission) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote
international cooperation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, the IEC publishes International Standards. Their preparation is
entrusted to technical committees; any IEC National Committee interested in the subject dealt with may
participate in this preparatory work. International, governmental and non-governmental organizations liaising
with the IEC also participate in this preparation. The IEC collaborates closely with the International Organization
for Standardization (ISO) in accordance with conditions determined by agreement between the two
organizations.
2) The formal decisions or agreements of the IEC on technical matters express, as nearly as possible, an
international consensus of opinion on relevant subjects since each technical committee has representation from
all interested National Committees.
3) The documents produced have the form of recommendations for international use and are published in the form
of standards, technical specifications, technical reports or guides and they are accepted by the National
Committees in that sense.
4) In order to promote international unification, IEC National Committees undertake to apply IEC International
Standards transparently to the maximum extent possible in their national and regional standards. Any
divergence between the IEC Standard and the corresponding national or regional standard shall be clearly
indicated in the latter.
5) The IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with one of its standards.
6) Attention is drawn to the possibility that some of the elements of this International Standard may be the subject
of patent rights. The IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 61188-5-1 has been prepared by IEC technical committee 91:
Electronics assembly technology.
The text of this standard is based on the following documents:
FDIS Report on voting
91/292/FDIS 91/318/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 3.
Annexes A and B are for information only.

61188-5-1 © IEC:2002 – 13 –
IEC 61188-5 consists of the following parts, under the general title Printed boards and printed
board assemblies – Design and use – Part 5: Attachment (land/joint) considerations:
IEC 61188-5-1, Generic requirements
IEC 61188-5-2, Discrete components
IEC 61188-5-3, Components with gull-wing leads, on two sides
IEC 61188-5-4, Components with J leads, on two sides
IEC 61188-5-5, Components with gull-wing leads, on four sides
IEC 61188-5-6, Components with J leads, on four sides
IEC 61188-5-7, Components with post (DIP) leads, on two sides
The committee has decided that the contents of this publication will remain unchanged
until 2004. At this date, the publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition, or
• amended.
61188-5-1 © IEC:2002 – 15 –
PRINTED BOARDS AND PRINTED BOARD ASSEMBLIES –
DESIGN AND USE –
Part 5-1: Attachment (land/joint) considerations –
Generic requirements
1 Scope and object
This part of IEC 61188 provides information on land pattern geometries used for the surface
attachment of electronic components. The intent of the information presented herein is to
provide the appropriate size, shape and tolerance of surface-mount land patterns to insure
sufficient area for the appropriate solder fillet, and also to allow for inspection, testing, and
rework of those solder joints.
2 Normative references
The following referenced documents are indispensable for the application of this document. For
dated references, only the edition cited applies. For undated references, the latest edition of
the referenced document (including any amendments) applies.
IEC 60097, Grid systems for printed circuits
IEC 60194, Printed board design, manufacture and assembly – Terms and definitions
IEC 61188-1-1, Printed boards and printed board assemblies – Design and use – Part 1-1:
Generic requirements – Flatness considerations for electronic assemblies
IEC 61191-1, Printed board assemblies – Part 1: Generic specification – Requirements for
soldered electrical and electronic assemblies using surface mount and related assembly
technologies
IEC 61191-2, Printed board assemblies – Part 2: Sectional specification – Requirements for
surface mount soldered assemblies
1)
IEC 61192-1, Soldered electronic assemblies – Part 1: Workmanship requirements – General
IEC 61192-2, Soldered electronic assemblies – Part 2: Workmanship requirements – Surface
1)
mounted assemblies
IEC 61760-1, Surface mounting technology – Part 1: Standard method for the specification of
surface mounting components (SMDs)
IEC 62326 (all parts), Printed boards
___________
1)
To be published.
61188-5-1 © IEC:2002 – 17 –
3 Terms and definitions
For the purposes of this part of IEC 61188, the terms and definitions given in English only in
1)
IEC 60194 and the following apply.
3.1
assembly
number of parts, subassemblies or combinations thereof joined together
[IEC 60194]
3.2
assembly, double-sided
packaging and interconnecting structure with components mounted on both the primary and
secondary sides
3.3
assembly, multilayer printed circuit (wiring)
multilayer printed circuit or printed wiring board on which separately manufactured components
and parts have been added
3.4
assembly, packaging and interconnecting (P&IA)
generic term for an assembly that has electronic components mounted on either one or both
sides of a packaging and interconnecting structure
3.5
assembly, printed board
assembly of several printed circuit assemblies or printed wiring assemblies, or both
3.6
assembly, printed circuit (wiring)
printed circuit or printed wiring board on which separately manufactured components and parts
have been added
3.7
assembly, single-sided
packaging and interconnecting structure with components mounted only on the primary side
3.8
base material
insulating material upon which a conductive pattern may be formed (the base material may be
rigid or flexible, or both. It may be a dielectric or insulated metal sheet)
[IEC 60194]
3.9
basic dimension
numerical value used to describe the theoretical exact location of a feature or hole (it is the
basis from which permissible variations are established by tolerance on other dimensions in
notes or by feature-control symbols)
[IEC 60194]
___________
1)
Certain definitions of IEC 60194 have been translated into French.

61188-5-1 © IEC:2002 – 19 –
3.10
blind via
via extending only to one surface of a printed board
[IEC 60194]
3.11
buried via
via that does not extend to the surface of a printed board
[IEC 60194]
3.12
castellation
recessed metallized feature on the edge of a leadless chip carrier that is used to interconnect
conducting surfaces or planes within or on the chip carrier
[IEC 60194]
3.13
chip carrier
low-profile, usually square, surface-mount component semiconductor package whose die cavity
or die mounting area is a large fraction of the package size and whose external connections
are usually on all four sides of the package (it may be leaded or leadless)
[IEC 60194]
3.14
chip-on-board (COB)
printed board assembly technology that places unpackaged semiconductor dice and
interconnects them by wire bonding or similar attachment techniques. Silicon area density is
usually less than of the printed board
[IEC 60194 modified]
3.15
coefficient of thermal expansion (CTE)
linear dimensional change of a material per unit change in temperature (see also "thermal
expansion mismatch")
[IEC 60194]
3.16
component
individual part or combination of parts that, when together, perform a design function(s) (see
also "discrete component" in IEC 60194)
[IEC 60194]
3.17
component mounting site
location on a P&I structure that consists of a land pattern and conductor fan-out to additional
lands for testing or vias that are associated with the mounting of a single component
3.18
conductive pattern
configuration or design of the conductive material on a base material (this includes conductors,
lands, vias, heatsinks and passive components when these are an integral part of the printed
board manufacturing process)
[IEC 60194]
61188-5-1 © IEC:2002 – 21 –
3.19
conductor
single conductive path in a conductive pattern
[IEC 60194]
3.20
constraining core
supporting plane that is internal to a packaging and interconnecting structure
[IEC 60194]
3.21
courtyard
smallest rectangular area that provides a minimum electrical and mechanical clearance
(courtyard excess) around the combined component body and land pattern boundaries
3.22
courtyard excess
area between the rectangle circumscribing the land pattern and the component, and the outer
boundary of the courtyard. The courtyard excess may be different in the x and y direction
3.23
courtyard manufacturing zone
courtyard area plus an allowance, as determined by manufacturing requirements, that will
ensure
– a defect-free mounting of a surface-mounting device;
– a proper operation of the circuit, i.e. a function not impaired by too small distances of
adjacent components;
– the inspection of the electrical function and of solder joints and, if required, rework and
repair
3.24
dual in-line package (DIP)
rectangular component package that has a row of leads extending from each of the longer
sides of its body that are formed at right angles to a plane that is parallel to the base of its body
[IEC 60194]
3.25
fine-pitch technology (FPT)
surface-mount assembly technology with component terminations on less than 0,625 mm
(0,025 in) centres
[IEC 60194]
3.26
fiducial mark
datum features of the PB used to provide common measurable points for assembly and
inspection processes that require positional accuracy
3.27
flat pack
rectangular component package that has a row of leads extending from each of the longer
sides of its body that are parallel to the base of its body
[IEC 60194]
61188-5-1 © IEC:2002 – 23 –
3.28
footprint
(see preferred term "land pattern")
[IEC 60194]
3.29
grid
orthogonal network of two sets of parallel equidistant lines that is used for locating points on a
printed board
[IEC 60194]
3.30
integrated circuit (IC)
combination of inseparable associated circuit elements that are formed in place and
interconnected on or within a single base material to perform a microcircuit function
[IEC 60194]
3.31
jumper wire
discrete electrical connection that is part of the original design and is used to bridge portions of
the basic conductive pattern formed on a printed board (see also "haywire")
[IEC 60194]
3.32
land
portion of a conductive pattern usually, but not exclusively, used for the connection and/or
attachment of components
[IEC 60194]
3.33
land pattern
combination of lands that is used for the mounting, interconnection and testing of a particular
component
[IEC 60194]
3.34
leadless chip carrier
chip carrier whose external connections consist of metallized terminations that are an integral
part of the component body (see also "leaded chip carrier")
[IEC 60194]
3.35
leaded chip carrier
chip carrier whose external connections consist of leads that are around and down the side of
the package (see also "leadless chip carrier")
3.36
master drawing
document that shows the dimensional limits or grid locations that are applicable to any and all
parts of a product to be fabricated, including the arrangement of conductors and non-
conductive patterns or elements; the size, type, and location of holes; and all other necessary
information
[IEC 60194]
61188-5-1 © IEC:2002 – 25 –
3.37
mixed mounting technology
component mounting technology that uses both through-hole and surface-mounting techno-
logies on the same packaging and interconnecting structure
3.38
module
separable unit in a packaging scheme
[IEC 60194]
3.39
nominal dimension
dimension that is between the maximum and minimum size of a feature (the tolerance on a
nominal dimension gives the limits of variation of a feature size)
3.40
packaging and interconnection structure (P&IS)
general term for a completely processed combination of base materials, supporting planes or
constraining cores, and interconnection wiring that are used for the purpose of mounting and
interconnecting components
[IEC 60194]
3.41
plated-through hole (PTH)
hole with plating on its walls that makes an electrical connection between conductive patterns
on internal layers, external layers, or both, of a printed board
[IEC 60194]
3.42
primary side
side of a packaging and interconnecting structure that is so defined on the master drawing (it is
usually the side that contains the most complex or the highest number of components)
[IEC 60194]
3.43
printed board (PB)
general term for completely processed printed circuit and printed wiring configurations (this
includes single-sided, double-sided and multilayer boards with rigid, flexible, and rigid-flex base
materials)
[IEC 60194]
3.44
printed wiring
conductive pattern that provides point-to-point connections but not printed components in a
predetermined arrangement on a common base (see also "printed circuit")
[IEC 60194]
3.45
registration
degree of conformity of the position of a pattern (or portion thereof), a hole, or other feature to
its intended position on a product
[IEC 60194]
61188-5-1 © IEC:2002 – 27 –
3.46
secondary side
side of a packaging and interconnecting structure that is opposite the primary side (it is the
same as the "solder side" on through-hole mounting technology)
[IEC 60194]
3.47
single in-line package (SIP)
component package with one straight row of pins or wire leads
[IEC 60194]
3.48
static charge
electrical charge that has accumulated or built up on the surface of a material
3.49
static electricity control
technique where materials and systems are employed to eliminate/discharge static electricity
build-up by providing continuous discharge paths
3.50
supported hole
hole in a printed board that has its inside surfaces plated or otherwise reinforced
[IEC 60194]
3.51
supporting plane
planar structure that is a part of a packaging and interconnecting structure in order to provide
mechanical support, thermo-mechanical constraint, thermal conduction and/or electrical
characteristics (it may be either internal or external to the packaging and interconnecting
structure) (see also "constraining core")
[IEC 60194]
3.52
surface-mount technology (SMT)
technology where electrical connection of components is made to the surface of a conductive
pattern of a printed board and does not utilize component lead holes
3.53
tented via
blind or through-hole via that has the exposed surface of the primary or secondary or both
sides of a packaging and interconnecting structure fully covered by a masking material, such
as a dry film polymer coating (solder mask), preimpregnated glass cloth (prepreg), etc., in
order to prevent hole access by process solutions, solder, or contamination
3.54
thermal expansion mismatch
absolute difference between the thermal expansion of two components or materials (see also
"coefficient of thermal expansion (CTE)")
[IEC 60194]
3.55
through connection
electrical connection between conductive patterns in different layers of a multilayer printed
board, for example, a plated-through hole
[IEC 60194]
61188-5-1 © IEC:2002 – 29 –
3.56
through-hole technology (THT)
assembly process for mounting component packages where leads are passed through
supported (plated-through) or unsupported (bare) holes in an interconnection substrate
3.57
tooling feature
physical feature that is used exclusively to position a printed board or panel during a
fabrication, assembly or testing process (see also "locating edge", "locating edge marker",
"locating notch", "locating slot", and "tooling hole")
[IEC 60194]
3.58
via
plated-through hole that is used as an interlayer connection, but in which there is no intention
to insert a component lead or other reinforcing material (see also "blind via" and "buried via")
[IEC 60194]
4 Design requirements
4.1 General
Although, in many instances, the land pattern geometries can be different based on the type of
soldering used to attach the electronic part, wherever possible, land patterns are defined in
such a manner that they are transparent to the attachment process being used. Designers can
use the information contained herein to establish standard configurations not only for manual
designs but also for computer-aided design systems. Whether parts are mounted on one or
both sides of the board, subjected to wave, reflow, or other type of soldering, the land pattern
and part dimensions should be optimized to insure proper solder joint and inspection criteria.
Although patterns are dimensionally defined and since they are a part of the printed board
circuitry geometry, they are subject to the producibility levels and tolerances associated with
plating, etching, assembly or other conditions. The producibility aspects also pertain to the use
of solder mask and the registration required between the solder mask and the conductor
patterns.
NOTE 1 The dimensions used for component descriptions have been extracted from standards developed by
industrial and/or standards bodies. Designers should refer to these standards for additional or specific component
package dimensions.
NOTE 2 For a comprehensive description of the given printed board and for achieving the best possible solder
joints to the devices assembled, the whole set of design elements includes, beside the land pattern definition:
• solder mask;
• solder paste stencil;
• clearance between adjacent components;
• clearance between bottom of component and PCB surface, if relevant;
• keep-out areas, if relevant;
• suitable rules for adhesive applications.
The whole of design elements is commonly defined as mounting conditions. This standard defines land patterns and
includes recommendations for clearances between adjacent components and for other design elements.
NOTE 3 The land patterns and other elements of the mounting conditions, particularly the courtyard, given in this
standard are related to the reflow soldering process. Adjustments for wave or other soldering processes, if
applicable, have to be carried out by the user. This may also be relevant when solder alloys other than eutectic tin
lead solders are used.
NOTE 4 This standard assumes that the land pattern follows the principle that even under worst-case conditions,
the overlap of the component termination and the corresponding soldering land will be complete.
NOTE 5 Heat dissipation aspects have not been taken into account in this standard.
NOTE 6 Heavier components (greater mass per land) require larger lands. In some cases, the lands shown in the
standard may not be large enough; in these cases, consideration of additional measures may be necessary.

61188-5-1 © IEC:2002 – 31 –
NOTE 7 The land form may be rectangular with straight or rounded corners. In the latter case, the area of the
smallest circumscribed rectangle shall be equal to that of one with straight corners.
NOTE 8 Land patterns for lead-free solder alloys may need modifications for optimizing the assembly processes
and the reliability of the solder joint.
4.1.1 Classification
The IEC standard on soldering requirements (IEC 61191-1) recognizes that electrical and
electronic assemblies are subject to classifications by intended end-item use. Three general
end-product types have been established to reflect differences in producibility, functional
performance requirements, and verification (inspection/test) frequency. It should be recognized
that there may be overlaps of equipment between types.
The user of the assemblies is responsible for determining the type family to which the product
belongs. The contract shall specify the type required and indicate any exceptions or additional
requirements to the parameters, where appropriate.
LEVEL A: General electronic products
Includes consumer products, some computer and computer peripherals, and hardware suitable
for applications where the major requirement is function of the completed assembly.
LEVEL B: Dedicated service electronic products
Includes communications equipment, sophisticated business machines, and instruments where
high performance and extended life is required, and for which uninterrupted service is desired
but not mandatory. Typically the end-use environment would not cause failures.
LEVEL C: High-performance electronic products
Includes all equipment where continued performance or performance-on-demand is mandatory.
Equipment downtime cannot be tolerated, end-use environment may be uncommonly harsh,
and the equipment shall function when required, such as life support systems and other critical
systems.
4.1.2 Land pattern determination
This standard discusses two methods of providing information on land patterns.
1) Exact details based on industry component specifications, board manufacturing and
component placement accuracy capabilities. These land patterns are restricted to a specific
component, and have an identifying land pattern number.
2) Equations can be used to alter the given information to achieve a more robust solder
connection, when used in particular situations where the equipment for placement or
attachment are more or less precise than the assumptions made when determining the land
pattern details (see 4.1.2).
Three land pattern geometry variations are supplied for each of the device families: maximum
land protrusion (Level 1), median land protrusion (Level 2) and minimum land protrusion
(Level 3).
Before adopting the minimum land pattern variation the user should consider product
qualification testing based on the conditions shown in table 14.

61188-5-1 © IEC:2002 – 33 –
Level 1: Maximum – For low-density product applications, the maximum land pattern condition
has been developed to accommodate wave or flow solder of leadless chip devices and leaded
gull-wing devices. The geometry furnished for these devices, as well as inward and J-formed
lead contact device families, may provide a wider process window for reflow solder processes
as well.
Level 2: Median – Products with a moderate level of component density may consider
adapting the median land pattern geometry. The median land patterns furnished for all device
families will provide a robust solder attachment condition for reflow solder processes and
should provide a condition suitable for wave or reflow soldering of leadless chip and leaded
gull-wing type devices.
Level 3: Minimum – High component density typical of portable and hand-held product
applications may consider the minimum land pattern geometry variation. Selection of the
minimum land pattern geometry may not be suitable for all product use categories.
The use of levels of performance (A, B, and C) is combined with that of component density
levels (1, 2, and 3) in explaining the condition of an electronic assembly. As an example,
combining the description as levels A1 or B3 or C2, would indicate the different combinations
of performance and component density to aid in understanding the environment and the
manufacturing requirements of a particular assembly.
4.2 Dimensioning systems
This subclause describes a set of dimensional criteria for components, land patterns, positional
accuracy of the component placement capability and the opportunity to create a certain size
solder joint commensurate with reliability or product performance analysis.
Profile tolerances are used in the dimensioning system to define the size range between
maximum and minimum component/lead dimensions without ambiguity. The profile tolerance is
intended to control both size and position of the land. Figure 1 shows the profile tolerancing
method.
IEC  1771/02
Figure 1 – Profile tolerancing method
The use of the profile dimensioning system requires an understanding of the concepts. The use
of a set of requirements are adopted and invoke the following rules, unless otherwise modified.
a) All dimensions are basic (nominal).
b) Limits of size control form as well as size.
c) Perfect form is required at maximum dimensions.

61188-5-1 © IEC:2002 – 35 –
d) Datum references and position tolerances apply at maximum dimensions, and are
dependent on feature size.
e) Position dimensions originate from maximum dimensions.
f) Tolerances and their datum references other than size and position apply regardless of
feature size (RFS).
The dimensioning concepts used for this system of analysis consider the assembly/attachment
requirements as their major goal. Specification (data) sheets for components or dimensions for
land patterns on boards may use different dimensioning concepts; however, the goal is to
combine all concepts into a single syste
...