SIST EN IEC 63287-3:2026

SLOVENSKI STANDARD
01-november-2026
Polprevodniški elementi - Splošne smernice za kvalifikacijo polprevodnikov - 3.
del: Smernice za načrtovanje ocenjevanja zanesljivosti močnostnega
polprevodniškega modula (IEC 63287-3:2026)
Semiconductor devices - Generic semiconductor qualification guidelines - Part 3:
Guidelines for reliability qualification plans for power semiconductor module (IEC 63287-
3:2026)
Halbleiterbauelemente – Allgemeine Richtlinien zur Halbleiterqualifizierung - Teil 3:
Richtlinien für Zuverlässigkeitsqualifizierungspläne für Leistungshalbleitermodule (IEC
63287-3:2026)
Dispositifs à semiconducteurs - Lignes directrices génériques concernant la qualification
des semiconducteurs - Partie 3: Lignes directrices pour les plans de qualification de la
fiabilité des modules à semiconducteurs de puissance (IEC 63287-3:2026)
Ta slovenski standard je istoveten z: EN IEC 63287-3:2026
ICS:
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

EUROPEAN STANDARD EN IEC 63287-3

NORME EUROPÉENNE
EUROPÄISCHE NORM September 2026
ICS 31.080.01
English Version
Semiconductor devices - Generic semiconductor qualification
guidelines - Part 3: Guidelines for reliability qualification plans for
power semiconductor module
(IEC 63287-3:2026)
Dispositifs à semiconducteurs - Lignes directrices Halbleiterbauelemente - Allgemeine Richtlinien zur
génériques concernant la qualification des semiconducteurs Halbleiterqualifizierung - Teil 3: Richtlinien für
- Partie 3: Lignes directrices pour les plans de qualification Zuverlässigkeitsqualifizierungspläne für
de la fiabilité des modules à semiconducteurs de puissance Leistungshalbleitermodule
(IEC 63287-3:2026) (IEC 63287-3:2026)
This European Standard was approved by CENELEC on 2026-09-10. CENELEC members are bound to comply with the CEN/CENELEC
Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration.
Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC
Management Centre or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other language made by translation
under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the
same status as the official versions.
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Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia, Slovakia, Slovenia, Spain, Sweden, Switzerland,
Türkiye and the United Kingdom.

European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
CEN-CENELEC Management Centre: Rue de la Science 23, B-1040 Brussels
© 2026 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members.
Ref. No. EN IEC 63287-3:2026 E

European foreword
The text of document 47/3015/FDIS, future edition 1 of IEC 63287-3, prepared by TC 47
"Semiconductor devices" was submitted to the IEC-CENELEC parallel vote and approved by
CENELEC as EN IEC 63287-3:2026.
The following dates are fixed:
• latest date by which the document has to be implemented at national (dop) 2027-09-30
level by publication of an identical national standard or by endorsement
• latest date by which the national standards conflicting with the (dow) 2029-09-30
document have to be withdrawn
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CENELEC shall not be held responsible for identifying any or all such patent rights.
Any feedback and questions on this document should be directed to the users’ national committee. A
complete listing of these bodies can be found on the CENELEC website.
Endorsement notice
The text of the International Standard IEC 63287-3:2026 was approved by CENELEC as a European
Standard without any modification.
In the official version, for Bibliography, the following notes have to be added for the standard indicated:
IEC 60068-2-1 NOTE Approved as EN IEC 60068-2-1
IEC 60068-2-6 NOTE Approved as EN 60068-2-6
IEC 60068-2-20 NOTE Approved as EN IEC 60068-2-20
IEC 60068-2-27 NOTE Approved as EN 60068-2-27
IEC 60068-2-47 NOTE Approved as EN 60068-2-47
IEC 60191-4 NOTE Approved as EN 60191-4
IEC 60721-3-3 NOTE Approved as EN IEC 60721-3-3
IEC 60721-3-4 NOTE Approved as EN IEC 60721-3-4
IEC 60721-3-5 NOTE Approved as EN IEC 60721-3-5
IEC 60747-15 NOTE Approved as EN IEC 60747-15
IEC 60749-1 NOTE Approved as EN 60749-1
IEC 60749-5 NOTE Approved as EN IEC 60749-5
IEC 60749-6 NOTE Approved as EN 60749-6
IEC 60749-15 NOTE Approved as EN IEC 60749-15
IEC 60749-21 NOTE Approved as EN IEC 60749-21
IEC 60749-23 NOTE Approved as EN IEC 60749-23
IEC 60749-25 NOTE Approved as EN 60749-25
IEC 60749-26 NOTE Approved as EN IEC 60749-26
IEC 60749-28 NOTE Approved as EN IEC 60749-28
IEC 60749-34 NOTE Approved as EN 60749-34
Annex ZA
(normative)
Normative references to international publications
with their corresponding European publications
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies. For
undated references, the latest edition of the referenced document (including any amendments)
applies.
NOTE 1  Where an International Publication has been modified by common modifications, indicated by (mod),
the relevant EN/HD applies.
NOTE 2  Up-to-date information on the latest versions of the European Standards listed in this annex is available
here: www.cencenelec.eu.
Publication Year Title EN/HD Year
IEC 63287-1 2021 Semiconductor devices - Generic EN IEC 63287-1 2021
semiconductor qualification guidelines -
Part 1: Guidelines for IC reliability
qualification
IEC 63287-3 ®
Edition 1.0 2026-08
INTERNATIONAL
STANDARD
Semiconductor devices - Generic semiconductor qualification guidelines -
Part 3: Guidelines for reliability qualification plans for power semiconductor
module
ICS 31.080.01  ISBN 978-2-8327-1402-7

IEC 63287-3:2026-08(en)
IEC 63287-3:2026 © IEC 2026
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative references . 6
3 Terms and definitions . 6
4 Product categories and applications . 7
4.1 Quality grade by application . 7
4.2 Quality grades and preconditions (Example) . 8
5 Failure . 8
5.1 Failure distribution . 8
5.2 Early failure period . 10
5.2.1 Description . 10
5.2.2 Early failure rate . 11
5.2.3 Screening (reduction of early failure) . 11
5.3 Random failure period . 11
5.3.1 Description . 11
5.3.2 Failure rate in the random failure period . 12
5.4 Wear-out failure period . 12
5.4.1 Description . 12
5.4.2 Wear-out failure verification . 12
6 Reliability test . 15
6.1 Reliability test methods . 15
6.2 Acceleration models for reliability tests . 17
7 Stress test methods . 17
8 Summary table of assumptions . 18
9 Summary . 19
Annex A (informative) Gate screening (TDDB measurement and screening method of
gate oxide) . 21
A.1 General . 21
A.2 TDDB of gate oxide. 21
A.2.1 TDDB . 21
A.2.2 Gate oxide breakdown mechanism . 21
A.2.3 TDDB lifetime estimation equation . 22
A.3 The TDDB measurement method and the lifetime estimation method . 22
A.3.1 General. 22
A.3.2 Ambient temperature, stress voltage, sample size and test method . 23
A.4 Voltage screening . 25
A.4.1 General. 25
A.4.2 Breakdown voltage distribution of gate oxide and screening . 25
A.4.3 Screening technique of power MOSFETs . 26
A.4.4 Comparison between the voltage screening and the burn-in test . 27
A.4.5 The method to calculate the early failure rate of gate oxide breakdown. 27
A.4.6 Example of the TDDB lifetime estimation by using the voltage step
stress method . 30
Bibliography . 32

IEC 63287-3:2026 © IEC 2026
Figure 1 – Bath-tub curve . 9
Figure 2 – Failure process of power semiconductor module manufacturing lots during
the early failure period . 10
Figure 3 – Conceptual diagram of the wear-out failure . 12
Figure 4 – Conceptual diagram of the accelerated reliability test . 13
Figure A.1 – The gate oxide breakdown mechanism . 21
Figure A.2 – Relationship between electric field strength and lifetime . 22
Figure A.3 – Relationship between the stress application time and the gate oxide
breakdown time . 23
Figure A.4 – TDDB Weibull plot. 24
Figure A.5 – Relationship between the electric field strength 1/E and the oxide
breakdown lifetime t . 24
BD
Figure A.6 – Relationship between the gate oxide lifetime and the failure rate . 25
Figure A.7 – Relationship between the gate oxide lifetime and the cumulative failure
probability . 26
Figure A.8 – The breakdown voltage distribution of gate oxide . 26
Figure A.9 – Voltage screening flow of gate oxide of power MOSFETs . 27
Figure A.10 – An example of the Weibull plot before and after screening . 28
Figure A.11 – Flow of the test using the voltage step stress method . 30
Figure A.12 – Example of the TDDB evaluation of semiconductor devices found
acceptable in the screening, using the voltage step stress method . 31

Table 1 – Quality grades and preconditions . 8
Table 2 – Accelerated lifetime test methods and purpose . 16
Table 3 – Stress test methods and purpose . 17
b
Table 4 – Accelerating factors, calculation formulae and numerical values . 18
Table A.1 – Comparison between the voltage screening and the burn-in test . 27

IEC 63287-3:2026 © IEC 2026
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
Semiconductor devices -
Generic semiconductor qualification guidelines -
Part 3: Guidelines for reliability qualification plans
for power semiconductor module

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and
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consensus of opinion on the relevant subjects since each technical committee has representation from all
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3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) IEC draws attention to the possibility that the implementation of this document may involve the use of (a)
patent(s). IEC takes no position concerning the evidence, validity or applicability of any claimed patent rights in
respect thereof. As of the date of publication of this document, IEC had not received notice of (a) patent(s), which
may be required to implement this document. However, implementers are cautioned that this may not represent
the latest information, which may be obtained from the patent database available at https://patents.iec.ch. IEC
shall not be held responsible for identifying any or all such patent rights.
IEC 63287-3 has been prepared by IEC technical committee 47: Semiconductor devices. It is
an International Standard.
The text of this International Standard is based on the following documents:
Draft Report on voting
47/3015/FDIS 47/3026/RVD
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.
IEC 63287-3:2026 © IEC 2026
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/publications.
A list of all parts in the IEC 63287 series, published under the general title Semiconductor
devices - Generic semiconductor qualification guidelines, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
– reconfirmed,
– withdrawn, or
– revised.
IEC 63287-3:2026 © IEC 2026
INTRODUCTION
When performing qualification tests, semiconductor device vendors prepare a specific reliability
test plan upon consultation with semiconductor device users in order to efficiently carry out the
reliability test.
This guideline presents examples of methods for preparing test plans to determine appropriate
reliability test conditions, based on the level of quality required in the operating environments
of various applications of power semiconductor modules. As a target of reliability, grades have
been specified for each of the following applications: automotive, industrial and consumer
electronics. Based on the number of annual operating hours, use period and other parameters
assumed for each grade, this guideline defines verification methods for the wear-out failure,
and proposes appropriate reliability tests. This guideline defines the concept of quality
assurance from early failure to wear-out failure. It also presents approaches to appropriately
ensure the reliability of power semiconductor modules.
The test conditions and the acceleration factor values presented in this guideline are only
examples used for setting reliability test conditions to verify a required level of quality.
NOTE Qualification tests are tests performed by power semiconductor device vendors, taking into account the
quality required by the users of their products.

IEC 63287-3:2026 © IEC 2026
1 Scope
This part of IEC 63287 specifies guidelines for a reliability qualification plan for power
semiconductor modules to assure reliability targets over the entire product life.
Power semiconductor modules with incorporated control circuits are excluded. Clamped
packages that need external pressure for being mounted in a system are excluded, e.g. disc-
type pressure pack devices.
This document is not intended for medical, military, aeronautics and astronautics-related
applications.
NOTE Throughout the document, the term power semiconductor module refers to multichip semiconductor power
modules as defined in 3.3.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies.
For undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 63287-1:2021, Semiconductor devices - Generic semiconductor qualification guidelines -
Part 1: Guidelines for IC reliability qualification
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminology databases for use in standardization at the following
addresses:
– IEC Electropedia: available at https://www.electropedia.org/
– ISO Online browsing platform: available at https://www.iso.org/obp
3.1
failure mode
classification of a fault phenomenon which causes product failure
Note 1 to entry: Disconnection, a short circuit, occasional loss, abrasion, characteristic deterioration, etc., are
typical items considered as failure modes.
3.2
failure mechanism
physical, chemical or other process that results in a failure mode, which leads to a product that
fails to meet functional requirements
3.3
power module
isolated or non-isolated semiconductor module with two or more semiconductor chips,
according to the package outline style code “MP” specified in IEC 60191-4
Note 1 to entry: The predominantly used package body material is plastic (including epoxy) according to
IEC 60191-4 and both the frame based and resin based embodiment are possible.
3.4
mode A failure
early failure with a decreasing failure rate due to extrinsic defects
IEC 63287-3:2026 © IEC 2026
3.5
mode B failure
random failure with relatively constant failure rate
Note 1 to entry: End of mode B regime limits the use period of a power semiconductor module.
3.6
mode C failure
wear-out failure with increasing failure rate due to intrinsic limitation of lifetime
3.7
bathtub curve
plot of failure rate versus time or cycles that exhibits three phases of life: infant mortality
(decreasing failure rate), random failure period (relatively constant failure rate), and intrinsic
wear-out (increasing failure rate)
4 Product categories and applications
4.1 Quality grade by application
Level of quality, operating hours and operating environment required for power semiconductor
modules in the market are varied, depending on the application of products for which power
semiconductor modules are used. As an example of a method for preparing test plans, this
guideline has grouped the applications into three major grades of requirements, namely the
automotive, the industrial and the consumer electronics application. For each grade, the
required level of quality and its preconditions are defined, as shown in Table 1.
IEC 63287-3:2026 © IEC 2026
4.2 Quality grades and preconditions (Example)
Table 1 – Quality grades and preconditions
Grade I II III
Description of Automotive application Industrial application Consumer electronics
grade application
Example of Powertrains, DC/DC Motor controls, power Air conditioners, home
application converter, on board charger converters, robots, machine appliances, etc.
(OBC), power steering, etc. tools, railway, etc.
Annual 500 h (driving hours) Up to 8 760 h; Up to 8 760 h;
operating hours
The operation differs varies depending on varies depending on
between when it works with application. application.
KEY ON/OFF and when it
does not work with KEY
ON/OFF.
Use period 15 years (cumulative failure 10 years to 20 years 5 years to 10 years
probability: < 1 %) (cumulative failure (cumulative failure
probability:1 %); probability:1 %);
varies depending on varies depending on
application. application.
Operating For engine compartment: T = -40 °C (min)/100 °C T = 0 °C (min)/70 °C (max)
a a
environment
T = -40 °C (min)/125 °C
(max) T = 70 °C (typ)/105 °C
assumed a
j
(max)
(varies (max) T = 70 °C (typ)/125 °C (max)
j
depending on
RH = 10 (min)/80 (max)%
T = 100 °C (typ)/150 °C
a
j RH = 10 (min)/80 (max)%
application)
RH typ. (20 % when being
(max) RH typ. (20 % when being
energized)
energized)
RH = 0 (min)/100 (max)%
(60 % when being de-
(60 % when being de-
energized)
RH typ. (10 % when driving)
energized)
(70 % when stopping)
b
Early failure rate 50 ppm/year to 100 ppm/year 100 ppm/year or less;
1 ppm /year or less
or less;
varies depending on
varies depending on application.
application.
Failure rate in 1 failure in time (FIT) or less 50 FIT to 100 FIT or less; 100 FIT or less;
the random
varies depending on varies depending on
failure period
application. application.
NOTE The values shown in Table 1 are only examples. In real business life, these conditions are set according
to market and customer requirements.
a
As an alternative, the limiting values according to the climatic classes reported in the IEC 60721 series should
be used as boundary conditions for a mission profile of climatic conditions (T , RH).
a
b
ppm stands for parts per million.

5 Failure
5.1 Failure distribution
The failure distribution of power semiconductor modules has been divided into three major
areas: early failure, random failure and wear-out failure. Figure 1 shows the bathtub curve
representing the relationship between the field use time and the instantaneous failure rate.
Each of the three areas is described in detail in 5.2 to 5.4.
IEC 63287-3:2026 © IEC 2026
In the case of power semiconductor modules, most modules that can cause early failures are
rejected in the power semiconductor modules vendors’ screening process, such as in the burn-
in test. However, some defective power semiconductor modules fail to be sorted out, and cause
failures relatively soon after they start operating in the market. In semiconductor products, it is
known that mode A failures, mode B failures, and mode C failures can occur. It is generally
known that with power semiconductor modules, more mode B failures take place than early
failures (failure mechanism analysis results). This is because the gate oxide of power
semiconductor modules is thicker than that of integrated circuits (ICs) or large scale integration
devices (LSIs). There are cases in which both the early failure rate and the mode-B failure rate
keep declining. When there are few early failures due to adequate pre-shipment screening, and
there are only limited mode B failures, however, random failures will become dominant failures
in the random failure period. In this case, the Weibull shape parameter m often gets closer to 1.
In reality, the instantaneous failure rate in the random failure period should be considered as a
superposition of:
a) early failures, whose instantaneous failure rate declines according to the theory, and
b) random failures, whose instantaneous failure rate is kept constant. Depending on the
proportion between the early failures and the random failures, it is often observed that the
instantaneous failure rate in the random failure period continues to decline. The random
failures have been attributed not only to internal factors, but also to external factors
including electrostatic discharge (ESD) and electrical overstress (EOS).
The wear-out failure period has been defined as the period in which failures are caused by the
end-of-life of wire bonding, solder bonding and the like of power semiconductor modules and
other parts that compose a power module. Other causes for wear-out failures include the end-
of-life of cells, interconnects, etc., that compose a semiconductor device such as a power metal-
oxide-semiconductor field effect transistor (MOSFET) or insulated-gate bipolar transistor (IGBT). In
other words, the wear-out failure period is a period when the end-of-life of the power modules
themselves has been observed. The number of failures increases over the course of time, and
eventually all power semiconductor modules will fail. For wear-out failures, there has been no
concept for setting upper limits or criteria for the failure rate. It is important to design power
semiconductor modules in such a way as not to allow any wear-out failures to take place during
their use period. In general, the criterion for determining the life of a power semiconductor
module is the period up until the start of wear failure until the cumulative failure probability rises.

Figure 1 – Bath-tub curve
IEC 63287-3:2026 © IEC 2026
5.2 Early failure period
5.2.1 Description
Power semiconductor modules are susceptible to defects derived from their manufacturing
process, as they are highly integrated and complex. The ratio of these power semiconductor
modules, which conform to their specification, is referred to as “yield”. In the sorting, all possible
parameters relating to the characteristic and functional requirements have been measured to
select conforming semiconductor devices. Even if they function normally in the sorting process,
however, some of the selected conforming semiconductor devices can have minor hidden
defects that do not have any electrical effects (latent failures). When a high yield is achieved,
it is less likely that power semiconductor modules with latent failures have been mixed into
conforming semiconductor devices.
When a small quantity of conforming power semiconductor modules with latent failures are
included in a production lot, the failure rate will decrease over the course of time. This is
because defect-free semiconductor devices with low-failure probability remain in the batch even
after power semiconductor modules with latent failures fail and are removed. In such a case,
the Weibull shape parameter m, on the assumption that the Weibull distribution applies, is less
than 1 (m < 1).
To be more specific, as shown in Figure 2, when a small quantity of conforming power
semiconductor modules with latent failures is contained in a production lot, electronic equipment
using these modules becomes defective in operation during the early failure period. Hence, the
broken semiconductor devices will be removed in the repair of the electronic equipment (part
replacement). Eventually, highly reliable power semiconductor modules will remain.

Figure 2 – Failure process of power semiconductor module
manufacturing lots during the early failure period
A primary countermeasure against such early failures is to reduce defects generated in the
manufacturing process. When practicable, design change could work as an effective
countermeasure to make power semiconductor modules unsusceptible to defects. Defect
reduction in semiconductor device manufacturing can be proactive, such as in-line defect
inspection stages of random lots, or reactive, correlating end-of-life (EOL) failures to isolate the
process step(s) likely to be the source of defect introduction.
IEC 63287-3:2026 © IEC 2026
5.2.2 Early failure rate
5.2.2.1 Early failure rate definition
The early failure rate represents the rate of failures taking place in the defined early failure
period in terms of % or parts per million (ppm).
The early failure probability represents the probability of degradation failures derived from
manufacturing defects that take place after shipment from semiconductor device manufacturers,
within one year from the start of operation in the market (end users) or in the manufacturing
process of system manufacturers (the defined early failure period).
In some cases, the term “mean early failure rate” has been used. The mean failure rate is
obtained by dividing the number of failures taking place during the defined failure period by
total operating time. The mean early failure rate is obtained by converting the cumulative failure
probability in the defined early failure period to the probability per unit time, and it is mainly
−9
expressed in terms of FIT (failures in time: 10 /h).
5.2.2.2 Cumulative fail probability
There are two methods to calculate the mean early failure rate, including the following:
a) a method to use actual market data acquired during the early failure period (for one year
after the start of shipment of mass-produced power semiconductor modules);
b) a method to perform calculation in a short period of time by conducting reliability tests
accelerated by applying an acceleration factor to actual operating conditions.
5.2.3 Screening (reduction of early failure)
Power semiconductor modules are used in a variety of applications, and it is important to ensure
the right quality level for each application. Under such circumstances, customers and the market
demand the reduction of early failures as an improvement in quality level.
In the case of IGBTs, failures in the low breakdown voltage region due to gate oxide film defects
have been reported as early failures of power semiconductor modules, and in the case of power
MOSFETs, avalanche failures due to device defects have been reported. As a method to reduce
these early failures, there are gate oxide screening for IGBTs and avalanche screening for
power MOSFETs.
In this guideline, the IGBT gate screening method is described in Annex A as an example of
the early failure reduction method.
5.3 Random failure period
5.3.1 Description
In general, the random failure period has been defined as the period from end of the early failure
period to start of the wear-out failure period. It is appropriate to consider that failures caused
after the end of the defined early failure period are attributed not only to those remaining
defective power semiconductor modules, which were not removed in the pre-shipment sorting,
but also to disturbance or random factors, which are not related to manufacturing defects. In
the case of power semiconductor modules, however, there are extremely few remaining
defective semiconductor devices to cause early failures which were not removed in the sorting.
The shape parameter of the Weibull distribution is usually almost constant (m is approximatively
equal to 1).
IEC 63287-3:2026 © IEC 2026
5.3.2 Failure rate in the random failure period
The mean failure rate in the random failure period can be calculated by using the same methods
as the mean early failure rate described below:
a) a method to use actual market data acquired during the random failure period (for the end
of the early failure period to the end of use period),
b) a method of calculation based on the data obtained from the evaluation of accelerated tests.
5.4 Wear-out failure period
5.4.1 Description
Wear-out failures represent the end of the lifetime of semiconductor devices themselves. All
power semiconductor modules fail sooner or later when they enter the wear-out period. In other
words, the wear-out failures shall not be allowed to take place before the end of use period.
Every power semiconductor device vendor adopts “reliability design” so as to take actions at
the design stage to prevent occurrence of wear-out failures during the use period. In the wear-
out failure period, the shape parameter m of the Weibull distribution is above 1 (m > 1), which
reflects the end of the lifetime of power semiconductor modules.
5.4.2 Wear-out failure verification
The following contents of 5.4.2 explain a methodology to calculate the sample size and the test
duration, which are needed to verify that the wear out regime is not entered during the use
period by means of a product reliability qualification. The methodology can be applied, if the
mission profile, the acceleration model and the end-of-life failure distribution are known or if at
least reasonable assumptions can be made. If this information is missing, the application of a
standardized test duration according to Clause 8 and sample sizes according to Clause 9 is
recommended.
Based on the conceptual diagrams (Figure 3, Figure 4), the method to calculate the number of
samples taken in an accelerated reliability test and the duration of an accelerated reliability test
is described below.
Figure 3 – Conceptual diagram of the wear-out failure
IEC 63287-3:2026 © IEC 2026
Figure 4 – Conceptual diagram of the accelerated reliability test
The time to reach a failure probability in the accelerated reliability test t , which is equivalent
to the actual operating time up to the end of the use period t , can be expressed as:
l
t
I
t =
(1)
A
CC
where
t = t + t
l s u;
is the value of actual operating time converted from pre-shipment screening time;
t
s
t is the use period;
u
A is the acceleration factor.
cc
By using the level of confidence of g % (CL = g %) and the number of samples n，the maximum
i
failure rate F – the estimated cumulative failure probability – as calculated from the binominal
i
distribution (with the number of failures equals 0) can be expressed as:
 g  1
F=11−−
)
(2
i  
100 n
 
i
Equation (2) can also be expressed as:
g
ln(1)－
100 (3)
n＝
i
ln(1－F )
i
The cumulative failure probability for the failure distribution assumed in the accelerated
reliability test can be expressed as:
m
t
i
F=1−−exp( ) (4)
i
m
η
IEC 63287-3:2026 © IEC 2026
m
t
F=1−−exp( )
(5)
m
η
where
t is the duration of pre-shipment tests including screening;
i
F is the cumulative failure probability to be checked during the use period;
η is the scale parameter of the Weibull distribution.
The following equation is obtained from the above Weibull equations:
mm
In(1− Ft)    A 
ii cc
(6)
t×
   
i
In(1− Ft) t
00   i 
Once the level of confidence g % (CL = g %) and the number of samples n is determined, the
i
estimated cumulative failure rate F can be obtained. By using the cumulative failure probability
i
that is checked during the use period F and Equation (6), the duration of pre-shipment tests
including screening t can be calculated as:
i
I (1−−F ) t I (1 F )
ni i ni
tt
  (7)
i 0
I (1−−Fm) A I (1 Fm)
n 00cc n
 
When the binominal distribution has been applied with the number of failures of 0, the duration
of pre-shipment tests including screening t can be expressed as:
i
gg
   
I (1−−l (1
nn
   
t
100 1 100
tt
    (8)
i 0'
n×I (1− Fm) A n×−l (1 Fm)
 i n 0  cc i n 0 
   
   
When the test is performed using samples for which pre-shipment screening equivalent to actual
operating time t has been conducted, the duration of the test excluding the pre-shipment
s
screening T can be expressed as:
i
t
s
Tt＝－
(9)
ii
A
cc
By using the duration of the test excluding the pre-shipment screening T , the cumulative failure
i
probability that is checked during the useful time F and Equation (6), the estimated cumulative
failure rate F , can be obtained. The number of samples n can be calculated based on the level
i i
of confidence of g % (CL = g %).
==
==
= =
IEC 63287-3:2026 © IEC 2026
t
s
tT＝－
(10)
ii
A
cc
m

A

cc
Ft＝－1 exp ××ln()1－F (11)

i
i 0
t
1

When the binominal distribution is applied with the number of failures of 0, the number of
samples n can be expressed as:
i
gg
mm
ln(1−−) ln(1 )
  
t t
0 100 1 100 (12)
n=×= ×
  
i
t ln(1− F ) At× ln(1− F )
i 00 cc i
6 Reliability test
6.1 Reliability test methods
Table 2 shows reliability test items for products (in the form of finished products). This guideline
presents a common scope of tests, taking account of the industrial standards and the JEDEC
standards. However, the test scope can be changed as long as it is large enough to verify that
the cumulative wear out failure probability in the use period is 1 % or less. For an assessment
of the random failure probability both methods mentioned in 5.3.2 can be applied. In most tests,
stress conditions can be accelerated by changing parameters such as voltage, temperature and
humidity. Through acceleration of stress conditions, reliability in the use period can be verified
in a short period of time.
Power semiconductor modules are operated at high voltage and high current. The reliability test
should be performed after the packaging process, partly because high voltage and high current
cannot be applied to the wafers, and partly because heat dissipation of the packages has an
impact on the reliability test results. For time dependent dielectric breakdown measurement
(TDDB), however, the reliability test can be performed on the wafers in order to make the total
duration of the TDDB reliability test, including the time to prepare test sample, reasonably short.
IEC 63287-3:2026 © IEC 2026
Table 2 – Accelerated lifetime test methods and purpose
Referenced test
Test item Objective Failure phenomena Remark
standard
To evaluate durability
by applying electrical Junction leakage,
IEC 60749-23
High-temperature
and thermal off-state breakdown voltage

reverse bias test
IEC 60747-9
static load to degradation
semiconductor devices
To evaluate durability
IEC 60749
...