Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language

Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>

General Information

Status
Published
Publication Date
06-Nov-2007
Current Stage
DELPUB - Deleted Publication
Completion Date
19-May-2011
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IEC 62530:2007 - Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language Released:11/7/2007 Isbn:2831893496
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IEC 62530
Edition 1.0 2007-11

IEEE 1800
INTERNATIONAL
STANDARD
Standard for SystemVerilog – Unified Hardware Design, Specification, and
Verification Language
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IEC 62530
Edition 1.0 2007-11

IEEE 1800
INTERNATIONAL
STANDARD
Standard For SystemVerilog – Unified +ardware 'esign, 6pecification, and
Verification Language
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
XH
ICS 25.040 ISBN 2-8318-9349-6
– 2 – IEC 62530:2007(E)
IEEE 1800-2005(E)
CONTENTS
IEEE introduction. 10
FOREWORD . 13
1. Overview. 14
1.1 Scope. 14
1.2 Purpose. 14
1.3 Conventions used in this standard . 16
1.4 Syntactic description. 16
1.5 Use of color in this standard . 17
1.6 Contents of this standard. 17
1.7 Examples. 20
1.8 Prerequisites. 20
2. Normative references. 22
3. Literal values. 24
3.1 Introduction. 24
3.2 Literal value syntax. 24
3.3 Integer and logic literals . 25
3.4 Real literals . 25
3.5 Time literals . 25
3.6 String literals. 25
3.7 Array literals . 26
3.8 Structure literals. 26
4. Data types . 22
4.1 Introduction. 28
4.2 Data type syntax. 29
4.3 Integer data types . 30
4.4 Real and shortreal data types . 31
4.5 Void data type. 31
4.6 Chandle data type. 31
4.7 String data type . 32
4.8 Event data type. 37
4.9 User-defined types . 37
4.10 Enumerations . 39
4.11 Structures and unions. 44
4.12 Class. 50
4.13 Singular and aggregate types . 50
4.14 Casting . 50
4.15 $cast dynamic casting . 51
4.16 Bit-stream casting . 52
4.17 Default attribute type . 55
5. Arrays. 56
5.1 Introduction. 56
5.2 Packed and unpacked arrays . 56
5.3 Multiple dimensions . 57
5.4 Indexing and slicing of arrays. 58
5.5 Array querying functions . 59
5.6 Dynamic arrays . 59
5.7 Array assignment . 61
5.8 Arrays as arguments. 62
5.9 Associative arrays . 63
Published by IEC under licence from IEEE. © 2005 IEEE. All rights reserved.
IEEE 1800-2005(E)
5.10 Associative array methods .66
5.11 Associative array assignment.68
5.12 Associative array arguments.69
5.13 Associative array literals.69
5.14 Queues .69
5.15 Array manipulation methods .72
6. Data declarations.78
6.1 Introduction.78
6.2 Data declaration syntax.78
6.3 Constants.79
6.4 Variables . 83
6.5 Nets . 84
6.6 Scope and lifetime .85
6.7 Nets, regs, and logic.86
6.8 Signal aliasing.87
6.9 Type compatibility.89
6.10 Type operator.92
7. Classes .94
7.1 Introduction.94
7.2 Syntax .94
7.3 Overview.95
7.4 Objects (class instance).96
7.5 Object properties.96
7.6 Object methods .97
7.7 Constructors .97
7.8 Static class properties.98
7.9 Static methods.99
7.10 This .99
7.11 Assignment, renaming, and copying. 100
7.12 Inheritance and subclasses . 101
7.13 Overridden members. 101
7.14 Super . 102
7.15 Casting . 103
7.16 Chaining
...

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