Delay and power calculation standards - Part 4: Design and Verification of Low-Power, Energy-Aware Electronic Systems

IEC 61523-4:2023 defines the syntax and semantics of a format used to express power intent in energy-aware electronic system design. Power intent includes the concepts and information required for specification and validation, implementation and verification, and modeling and analysis of power-managed electronic systems. This standard also defines the relationship between the power intent captured in this format and design intent captured via other formats (e.g., standard hardware description languages and cell libraries). This is an IEC/IEEE dual logo standard.
The contents of the corrigendum 1 (2024-02) have been included in this copy.

General Information

Status
Published
Publication Date
10-Oct-2023
Drafting Committee
Current Stage
PPUB - Publication issued
Start Date
11-Oct-2023
Completion Date
08-Sep-2023
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Standard
IEC 61523-4:2023 - Delay and power calculation standards - Part 4: Design and Verification of Low-Power, Energy-Aware Electronic Systems Released:11. 10. 2023
English language
547 pages
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IEC 61523-4 ®
Edition 2.0 2023-10

IEEE Std 1801
INTERNATIONAL
STANDARD
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Delay and power calculation standards –
Part 4: Design and Verification of Low-Power, Energy-Aware Electronic Systems
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IEC 61523-4 ®
Edition 2.0 2023-10
IEEE Std 1801™
INTERNATIONAL
STANDARD
colour
inside
Delay and power calculation standards –
Part 4: Design and Verification of Low-Power, Energy-Aware Electronic Systems
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 25.040.01, 35.060 ISBN 978-2-8322-7540-5
– i – IEEE Std 1801™-2018
IEEE Std 1801-2018
IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems
Contents
1. Overview . 13
1.1 Scope . 13
1.2 Purpose . 13
1.3 Key characteristics of the Unified Power Format . 13
1.4 Contents of this standard . 15
2. Normative references . 16
3. Definitions, acronyms, and abbreviations. 16
3.1 Definitions . 16
3.2 Acronyms and abbreviations . 22
4. Concepts . 23
4.1 Introduction . 23
4.2 Design structure . 24
4.3 Design representation . 24
4.4 Power architecture . 28
4.5 Power distribution . 31
4.6 Power management . 39
4.7 Supply states and power states. 44
4.8 Simstates . 51
4.9 Power intent specification . 52
5. Language basics . 58
5.1 UPF is Tcl . 58
5.2 Conventions used . 59
5.3 Lexical elements . 61
5.4 Boolean expressions . 65
5.5 Object declaration . 67
5.6 Attributes of objects . 67
5.7 Precedence . 72
5.8 Generic UPF command semantics . 75
5.9 effective_element_list semantics . 76
5.10 Command refinement . 79
5.11 Error handling . 80
5.12 Units . 80
5.13 SystemC language basic . 80
6. Power intent commands. 81
6.1 Introduction . 81
6.2 Categories . 81
6.3 add_parameter . 82
6.4 add_port_state (legacy) . 83
6.5 add_power_state . 84
6.6 add_pst_state (legacy) . 91
6.7 add_state_transition . 92
6.8 add_supply_state . 94
6.9 apply_power_model . 95
6.10 associate_supply_set . 97
6.11 begin_power_model (legacy) . 99
6.12 bind_checker . 100

Published by IEC under licence from IEEE. © 2018 IEEE. All rights reserved.

IEEE Std 1801™-2018 – ii –
IEEE Std 1801-2018
IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems
6.13 connect_logic_net . 102
6.14 connect_supply_net . 104
6.15 connect_supply_set . 106
6.16 create_composite_domain . 107
6.17 create_hdl2upf_vct . 109
6.18 create_logic_net . 110
6.19 create_logic_port . 111
6.20 create_power_domain . 112
6.21 create_power_state_group . 119
6.22 create_power_switch . 121
6.23 create_pst (legacy) . 128
6.24 create_supply_net . 129
6.25 create_supply_port . 133
6.26 create_supply_set . 134
6.27 create_upf2hdl_vct . 136
6.28 define_power_model . 137
6.29 describe_state_transition (deprecated) . 139
6.30 end_power_model (legacy) . 139
6.31 find_objects . 140
6.32 load_simstate_behavior . 144
6.33 load_upf . 145
6.34 load_upf_protected (deprecated) . 146
6.35 map_power_switch . 146
6.36 map_repeater_cell . 147
6.37 map_retention_cell . 148
6.38 name_format . 152
6.39 save_upf . 153
6.40 set_correlated . 154
6.41 set_design_attributes . 155
6.42 set_design_top . 156
6.43 set_domain_supply_net (legacy) . 157
6.44 set_equivalent . 158
6.45 set_isolation . 160
6.46 set_level_shifter . 167
6.47 set_partial_on_translation . 173
6.48 set_port_attributes. 175
6.49 set_repeater . 181
6.50 set_retention . 185
6.51 set_retention_elements . 189
6.52 set_scope . 190
6.53 set_simstate_behavior . 191
6.54 set_variation . 194
6.55 sim_assertion_control . 195
6.56 sim_corruption_control . 197
6.57 sim_replay_control . 200
6.58 upf_version . 202
6.59 use_interface_cell . 203
7. Power-management cell definition commands . 205
7.1 Introduction . 205
7.2 define_always_on_cell . 206
7.3 define_diode_clamp . 207
7.4 define_isolation_cell . 208
7.5 define_level_shifter_cell . 211
7.6 define_power_switch_cell . 216
7.7 define_retention_cell . 218

Published by IEC under licence from IEEE. © 2018 IEEE. All rights reserved.

– iii – IEEE Std 1801™-2018
IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems
8. UPF processing . 220
8.1 Overview . 220
8.2 Data requirements . 221
8.3 Processing phases . 221
8.4 Error checking . 225
9. Simulation semantics . 225
9.1 Supply network creation . 225
9.2 Supply network simulation . 227
9.3 Power state simulation . 228
9.4 Power state transition detection . 231
9.5 Simstate simulation . 232
9.6 Transitioning from one simstate state to another . 234
9.7 Simulation of retention . 235
9.8 Simulation of isolation . 241
9.9 Simulation of level-shifting . 242
9.10 Simulation of repeaters . 242
10. UPF information model . 242
10.1 Overview . 242
10.2 Components of UPF information model . 243
10.3 Identifiers in information model (IDs) . 244
10.4 Classification of objects . 247
10.5 Example of design hierarchy . 253
10.6 Object definitions. 254
11. Information model application programmable interface (API) . 313
11.1 Tcl interface . 313
11.2 HDL interface . 323
Annex A (informative) Bibliography . 387
Annex B (normative) Value conversion tables . 388
B.1 Overview . 388
B.2 VHDL_SL2UPF . 388
B.3 UPF2VHDL_SL . 388
B.4 VHDL_SL2UPF_GNDZERO. 388
B.5 UPF_GNDZERO2VHDL_SL. 389
B.6 SV_LOGIC2UPF . 389
B.7 UPF2SV_LOGIC . 389
B.8 SV_LOGIC2UPF_GNDZERO . 389
B.9 UPF_GNDZERO2SV_LOGIC . 389
B.10 VHDL_TIED_HI . 390
B.11 SV_TIED_HI . 390
B.12 VHDL_TIED_LO . 390
B.13 SV_TIED_LO . 390
Annex C (informative) UPF query examples . 391
C.1 Overview . 391
C.2 Utility procs . 391
C.3 High-level procs . 392
C.4 Superseded UPF queries . 394
Annex D (informative) Replacing deprecated and legacy commands and options . 396
D.1 Overview. 396
D.2 Deprecated and legacy constructs . 396

Published by IEC under licence from IEEE. © 2018 IEEE. All rights reserved.

IEEE Std 1801™-2018 – iv –
IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems
D.3 Recommendations for replacing deprecated and legacy constructs . 398
Annex E (informative) Low-power design methodology . 401
E.1 Overview . 401
E.2 Simple System on Chip (SoC) example design . 401
E.3 Design, verification, and implementation flow . 404
E.4 Power intent of the example design . 407
Annex F (informative) Power-management cell definitions in UPF and Liberty . 428
F.1 Introduction . 428
F.2 define_always_on_cell . 428
F.3 define_diode_clamp . 430
F.4 define_isolation_cell. 431
F.5 define_level_shifter_cell . 434
F.6 define_power_switch_cell . 436
F.7 define_retention_cell . 438
Annex G (informative) Power-management cell modeling examples . 442
G.1 Overview. 442
G.2 Modeling always-on cells . 442
G.3 Modeling cells with internal diodes . 448
G.4 Modeling isolation cells . 450
G.5 Modeling level-shifters . 467
G.6 Modeling power-switch cells . 484
G.7 Modeling state retention cells . 494
Annex H (informative) IP power modeling for system-level design . 506
H.1 Introduction. 506
H.2 Overview of system-level IP power models . 506
H.3 Content of system-level IP power models . 507
H.4 Power calculation using power functions . 508
H.5 Power model structure . 510
H.6 Power model instantiation—example approach . 511
Annex I (normative) Switching Activity Interchange Format . 513
I.1 Syntactic conventions . 514
I.2 Lexical conventions . 515
I.3 Backward SAIF file . 518
I.4 Library forward SAIF file . 534
I.5 RTL forward SAIF file . 542
Annex J (informative) Participants . 547

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– v – IEEE Std 1801™-2018
DELAY AND POWER CALCULATION STANDARDS –
Part 4: Design and Verification of Low-Power, Energy-Aware Electronic
Systems
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IEC 61523-4/IEEE Std 1801 was processed through IEC technical committee 91: Electronics
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IEEE Std 1801™-2018
IEEE Standard for Design and
Verification of Low-Power, Energy-
Aware Electronic Systems
Sponsor
Design Automation Standards Committee
of the
IEEE Computer Society
Approved 27 September 2018
IEEE-SA Standards Board
Published by IEC under licence from IEEE. © 2018 IEEE. All rights reserved.

IEEE Std 1801™-2018
Abstract: A method is provided for specifying power intent for an electronic design, for use in
verification of the structure and behavior of the design in the context of a given power-
management architecture, and for driving implementation of that power-management
architecture. The method supports incremental refinement of power intent specifications required
for IP-based design flows.
Keywords: corruption semantics, IEEE 1801™, interface specification, IP reuse, isolation,
level-shifting, power-aware design, power domains, power intent, power modes, power states,
progressive design refinement, retention, retention strategies

Published by IEC under licence from IEEE. © 2018 IEEE. All rights reserved.

IEEE Std 1801™-2018
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