IEC 63501-2416:2023

IEC 63501-2416 ®
Edition 1.0 2023-10
™
IEEE Std 2416
INTERNATIONAL
STANDARD
colour
inside
Power Modeling to Enable System Level Analysis
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IEC 63501-2416 ®
Edition 1.0 2023-10
IEEE Std 2416™
INTERNATIONAL
STANDARD
colour
inside
Power Modeling to Enable System Level Analysis
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 25.040.01, 35.060 ISBN 978-2-8322-7505-4
IEEE Std 2416™-2019
– 1 –
Contents
1. Overview . 9
1.1 Scope .10
1.2 Purpose .10
1.3 Key aspects and considerations .10
1.4 Typographic conventions .11
2. Normative references .11
3. Definitions, acronyms, and abbreviations .12
3.1 Definitions .12
3.2 Acronyms and abbreviations .12
4. Model architecture .12
4.1 Two modeling levels .13
4.2 Four modeling representations.14
5. Library-level semantics .15
5.1 Library .15
5.2 Technology .15
5.3 Units .16
5.4 ModelParameters .17
5.5 ModelExpressions .17
5.6 ModelConditions .18
5.7 ModelContributors .18
6. Cell declaration semantics .20
6.1 Cell .20
6.2 Pins .21
6.3 Modes .22
6.4 Events .23
6.5 CellParameters .25
6.6 States.25
6.7 DynamicPower and StaticPower .26
7. Contributors .27
7.1 PowerContributor .27
7.2 EnergyContributor .28
8. Tables .28
8.1 separator, RowSeparator, and ArraySeparator .28
8.2 valueType .29
8.3 Indices.30
8.4 Data array .30
9. Expressions .31
9.1 Expression types .32
9.2 Expression element .32
9.3 ExpressionParameters .33
9.4 Global and local expressions .33
Annex A (informative) Bibliography .36
Annex B (informative) Example models .37
Annex C (informative) Participants  .62
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IEEE Std 2416™-2019 – ii –
POWER MODELING TO ENABLE SYSTEM LEVEL ANALYSIS
FOREWORD
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– 3 –
IEEE Std 2416™-2019
The text of this International Standard is based on the following documents:
IEEE Std FDIS Report on voting
2416 (2019) 91/1867A/FDIS 91/1888/RVD
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
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IEEE Std 2416™-2019
IEEE Standard for Power Modeling
to Enable System-Level Analysis
Developed by the
Design Automation Committee
of the
IEEE Computer Society
Approved 21 May 2019
IEEE-SA Standards Board
Published by IEC under licence from IEEE. © 2019 IEEE. All rights reserved.

IEEE Std 2416™-2019
Abstract: In this standard, a parameterized and abstracted power model enabling system,
software, and hardware intellectual property (IP)–centric power analysis and optimization are
described. Concepts and constructs are defined for the development of parameterized, accurate,
efficient, and complete power models for systems and hardware IP blocks usable for system
power analysis and optimization. Process, voltage, and temperature (PVT) independence;
power and thermal management interface; and workload and architecture parameterization are
some of the concepts included.
TM
Keywords: IEEE 2416 , intellectual property (IP) blocks, modeling standards, models,
optimization, parameterization, power contributors, power data, process, voltage, and
temperature (PVT)
•
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IEEE Std 2416™-2019
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IEEE Std 2416™-2019
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IEEE Std 2416™-2019
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IEEE Std 2416™-2019
IEEE Introduction
This introduction is not part of IEEE Std 2416-2019, IEEE Standard for Power Modeling to Enable
System-Level Analysis.
All System-on-Chip (SoC) designs today face power issues of one sort or another—maximizing battery
life, sizing power grids, controlling leakage power, verifying power sequencing, estimating and modeling
power at various abstractions, analyzing electro-thermal effects, and so on.
Despite growing industry and societal concerns with power consumption and significant industry attention,
there has not been a standard way of representing power data for use at the system level, especially across a
range of process, voltage, and temperature (PVT) points in a single model.
The lack of a complete and robust modeling standard has led to a paucity of power models. Intellectual
property (IP) vendors, if they produce any power models at all, produce models that are limited in use and
application. As a result, designers and other model users struggle with reliably estimating power during
system-level design, ultimately producing SoCs that are less power efficient than they could be. To address
this situation, a modeling standard addressing data representation is needed to enable modeling accurate
and efficient power and thermal analyses early in the design cycle.
Finally, this standard has incorporated several prior technologies and specifications developed and released
by Si2, including Leakage Power Contributor Modeling, Liberty Mode Extensions for Atomic Power
Modeling, Standards for Efficient System Level Power Analysis, and Multi-level Power Modeling.
Acknowledgments
Grateful acknowledgment is made for permission to use the following source material:
Silicon Integration Initiative, Inc. (Si2)—System Level Power Model Interface and
Data Representation™, V3.0.
Published by IEC under licence from IEEE. © 2019 IEEE. All rights reserved.

IEEE Std 2416™-2019 – 9 –
IEEE Standard for Power Modeling
to Enable System-Level Analysis
1. Overview
Even though IEEE Std 1801™-2015 added power- state modeling capabilities to the most recently
released specification, data representation was not included as that capability was explicitly left out of
scope during the IEEE 1801 standardization process. Instead, IEEE Std 1801-2015 assumes another
standard will supply the power data to the state-based model defined in IEEE Std 1801-2015. Figure 1
illustrates the power data flow between IEEE Std 1801-2015 and this standard.
Figure 1 —Relationship between this standard and IEEE Std 1801-2015
Information on references can be found in Clause 2.
Published by IEC under licence from IEEE. © 2019 IEEE. All rights reserved.

– 10 – IEEE Std 2416™-2019
1.1 Scope
This standard describes a parameterized and abstracted power model enabling system, software, and
hardware intellectual property (IP)–centric power analysis and optimization. It defines concepts for the
development of parameterized, accurate, efficient, and complete power models for systems and hardware
IP blocks usable for system power analysis and optimization. These concepts include, but are not limited
to, process, voltage, and temperature (PVT) independence; power and thermal management interface; and
workload and architecture parameterization. Such models are suitable for use in software development
flows and hardware design flows, as well as for representing both pre–silicon-estimated
and post–silicon-measured data. This standard also defines the necessary requirements for the information
content of parameterized, accurate, efficient, and complete power models to help guide
development and usage of other related power, workload, and functional modeling standards, such as
UPF IEEE Std 1801™-2015, SystemC IEEE Std 1666™-2011, and SystemVerilog
IEEE Std 1800™-2012. Beyond defining the concepts and related standard requirements, this standard also
recommends the use of other relevant design flow standards (e.g., IP-XACT
IEEE Std 1685™-2014 [B2] ), with the objective of enabling more complete and usable power-aware
design flows.
1.2 Purpose
This standard supports the ability to develop accurate, efficient, and interoperable power models for
complex designs, to be used with a variety of commercial products throughout an electronic system design,
analysis, and verification flows.
1.3 Key aspects and considerations
This standard describes a PVT-independent modeling capability that can serve up power data throughout
the entire System-on-Chip (SoC) development flow from IEEE 1801 system-level power estimation all the
way down to gate-level power calculation. Contributor-based modeling techniques are employed to
achieve PVT independence, and multilevel modeling concepts enable a single model to serve various
abstraction levels. Contributors are separable, summable components of power consumption that depend
on parameters such as transistor widths and stacks, as well as on charging capacitances. Contributors offer
the capability to do a “late binding” of specific PVT conditions to an IP model, avoiding the need to
characterize the target IP up front under particular PVT conditions.
This standard addresses three separate, but related, modeling concerns: 1) interfaces to other modeling
standards, such as IEEE Std 1801-2015, as well as to existing electronic design automation (EDA) tools;
2) persistent data representation and storage; and 3) model evaluation—the conversion of contributor data
into energy and power data.
In addition, the following requirements have been identified as being essential to improving both model
generation and model usage:
 Direct support for IEEE 1801 IP component power-state model data and interface definitions
 PVT independence: Power data need not be generated at specific PVT points prior to
model evaluation
 Ability to coexist with legacy power data formats, such as Liberty [B3]
 Ability to model IP blocks of arbitrary complexity as well as logic primitives, such as NANDs,
NORs, and Flip-Flops
The numbers in brackets correspond to those of the bibliography in Annex A.
Published by IEC under licence from IEEE. © 2019 IEEE. All rights reserved.

IEEE Std 2416™-2019 – 11 –
 Ability for a single model to be used in the earliest phases of system design, the latest
implementation phases, and all phases in between
The development and standardization of modeling capabilities addressing these issues can provide benefits
to both model generators, such as foundries and IP providers, and model consumers, such as IP and SoC
architects, SoC verification teams, and energy-aware software developers. For model generators, this
development enables efficiency in the model generation and support process (in terms of time, compute
resources, and resulting costs). For model consumers, it enables more efficient, reliable, and consistent
power analysis and optimization flows from the beginning of the design process to the end. Additionally,
the “late binding” of specific PVT conditions provides efficiency benefits for model generators and model
consumers alike, including very early stage electrothermal analyses.
1.4 Typographic conventions
The following typographic conventions are used in this standard:
 The courier font indicates examples or key term usage from other languages, for example,

 The bold font indicates key terms or symbols, text that shall be typed exactly as it appears, for
example, the Library definition is an XML element.
 The italic font represents definitions (e.g., Contributors may be thought of as a foundational
representation) or variables (e.g., min=”min_value” [where min_value is a variable]).
 Square brackets ([]) indicate optional parameters.
 Pipes (|) indicate (and separate) a set of pick-one options. For example, in the following line,
EnergyContributor, Expression, Table, and Scalar are a (optional) set of pick-one
choices to consider:
EnergyContributor | Expression | Table | Scalar
The conventions are for ease of reading only. Any editorial inconsistencies in the use of this typography are
unintentional and have no normative meaning in this standard.
2. Normative references
The following referenced documents are indispensable for the application of this document (i.e., they must
be understood and used, so each referenced document is cited in text and its relationship to this document is
explained). For dated references, only the edition cited applies. For undated references, the latest edition of
the referenced document (including any amendments or corrigenda) applies.
Accellera Systems Initiative, “Verilog-AMS Language Reference Manual, Version 2.4.0,” May 30, 2014.
4, 5
IEEE Std 1666™-2011, IEEE Standard for Standard SystemC Language Reference Manual.
IEEE Std 1800™-2012. IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and
Verification Language.
Verilog-AMS publications are available from the Accellera Systems Inititave (https://accellera.org/).
IEEE publications are available from The Institute of Electrical and Electronics Engineers (http://standards.ieee.org).
The IEEE standards or products referred to in Clause 2 are trademarks owned by The Institute of Electrical and Electronics
Engineers, Incorporated.
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– 12 – IEEE Std 2416™-2019
IEEE Std 1801™-2015, IEEE Standard for Design and Verification of Low-Power Integrated Circuits.
World Wide Web Consortium, “eXtensible Markup Language (XML) 1.0” specification
(http://www.w3.org/TR/REC-xml/).
3. Definitions, acronyms, and abbreviations
3.1 Definitions
For the purposes of this document, the following terms and definitions apply. The IEEE Standards
Dictionary Online should be consulted for terms not defined in this clause.
contributor: A separable component of power consumption represented by proxies, such as leaking
transistors and switched capacitances.
contributor evaluator: An expression, or set of expressions, that evaluates a contributor using specified
parameter values to return power or energy.
data name: A string that starts with an upper- or lowercase alphabetic character and has 0 or more
additional alphanumeric characters or underscores (_).
expression: A combination of one or more constants, variables, operators, and functions used to return
a value.
event: Defines the various energy-consuming activities that may occur for a modeled cell.
mode: Used in conventional gate-level power modeling to describe the logical condition of a cell in which
all signals, including any clocks, are quiescent.
scaled SI units: A string that represents a unit notation that may include a scaling factor prefix and shall
contain a unit suffix.
state: Used in system-level power modeling to describe the logical condition of a cell in which certain
signals, particularly clocks, toggle at some particular frequency while all other signals are quiescent.
3.2 Acronyms and abbreviations
IP intellectual property
PVT process, voltage, and temperature
SOC System-on-Chip
4. Model architecture
The general model architecture is a multilevel architecture, which provides backward compatibility with
existing gate-level models. This architecture also enables a single model, with multiple levels and multiple
representations, to be used at various phases in a design flow. See Figure 2.
XML publications are available from the World Wide Web Consortium (http://www.w3.org).
IEEE Standards Dictionary Online is available at: http://dictionary.ieee.org.
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IEEE Std 2416™-2019 – 13 –
Figure 2 —General model architecture
4.1 Two modeling levels
Two different modeling levels are provided, gate level and system level. Data are represented separately for
each level, although data at a lower level may be referenced by an upper level.
4.1.1 Gate level
The gate level provides the storage of data for backward compatibility with legacy modeling approaches,
such as Liberty [B3], in which static power and energy data are stored. A cell modeled in this manner may
store hard-coded PVT-specific data or reference contributors. This level uses the Pins (see 6.2), Modes
(see 6.3), and Events (see 6.4) elements.
The power and energy data returned from this level are identical to that provided by Liberty [B3], namely,
static power per mode per supply and energy per event per supply as shown in Figure 2, along with
associated data such as pin names and related information.
4.1.2 System level
The system level provides for interoperability with IEEE 1801 component power-state models.
The output from the system level shall be consistent with the IEEE 1801 –power_expr attribute of the
add_power_state command, which expects to receive static power and dynamic power for a
defined state. Several inputs (in addition to those required by the gate level) need to be added to provide
this power data, including the operating frequency (and potentially others depending on how the
IEEE 1801 power-state model is defined and parameterized). This level uses the ModelParameters
(see 5.4), CellParameters (see 6.5), and States (see 6.6) elements.
For a voltage-independent, system-level power model, data may be represented by expressions
(see Clause 9) or tables (see Clause 8). Contributor data are accessed through power expressions and the
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– 14 – IEEE Std 2416™-2019
Contributor Evaluator (see Figure 2) in a cascaded fashion. The power expressions shall convert PVT-
specific energy and static power into dynamic and static power compatible with
IEEE 1801 requirements.
4.2 Four modeling representations
Energy and power data may be represented by contributors, expressions, tables, or scalars.
4.2.1 Contributors
Contributors may be thought of as a foundational representation. With this representation, power data
are not stored as absolute numbers of energy or power. Instead, data are stored as different power
contributors, such as subthreshold leakage contributors, gate leakage contributor
...