IEC 62530-2:2023
(Main)SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual
SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual
IEC 62530-2:2023 establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.1. This is an IEC/IEEE dual logo standard.
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IEC 62530-2 ®
Edition 2.0 2023-10
™
IEEE Std 1800.2
INTERNATIONAL
STANDARD
SystemVerilog –
Part 2: Universal Verification Methodology Language Reference Manual
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IEC 62530-2 ®
Edition 2.0 2023-10
IEEE Std 1800.2™
INTERNATIONAL
STANDARD
SystemVerilog –
Part 2: Universal Verification Methodology Language Reference Manual
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 25.040.01, 35.060 ISBN 978-2-8322-7516-0
– i – IEEE Std 1800.2™-2020
Contents
1. Overview .12
1.1 Scope .12
1.2 Purpose .12
1.3 Word usage .12
1.4 Conventions used .13
2. Normative references .15
3. Definitions, acronyms, and abbreviations .15
3.1 Definitions .15
3.2 Acronyms and abbreviations .16
4. Universal Verification Methodology (UVM) class reference .17
5. Base classes .18
5.1 Overview .18
5.2 uvm_void .18
5.3 uvm_object .19
5.4 uvm_transaction .27
5.5 uvm_port_base #(IF) .31
5.6 uvm_time .34
5.7 uvm_field_op .36
6. Reporting classes .38
6.1 Overview .38
6.2 uvm_report_message .39
6.3 uvm_report_object .41
6.4 uvm_report_handler .47
6.5 Report server.50
6.6 uvm_report_catcher .53
7. Recording classes .58
7.1 uvm_tr_database .59
7.2 uvm_tr_stream .61
7.3 UVM links .65
8. Factory classes .69
8.1 Overview .69
8.2 Factory component and object wrappers .69
8.3 UVM factory.75
9. Phasing .81
9.1 Overview .81
9.2 Implementation .81
9.3 Phasing definition classes .82
9.4 uvm_domain .91
9.5 uvm_bottomup_phase .92
9.6 uvm_task_phase.92
9.7 uvm_topdown_phase .93
9.8 Predefined phases .94
10. Synchronization classes .98
10.1 Event classes .98
Published by IEC under licence from IEEE. © 2020 IEEE. All rights reserved.
IEEE Std 1800.2™-2020 – ii –
10.2 uvm_event_callback .101
10.3 uvm_barrier .102
10.4 Pool classes .104
10.5 Objection mechanism .105
10.6 uvm_heartbeat .110
10.7 Callbacks classes .112
11. Container classes .115
11.1 Overview .115
11.2 uvm_pool #(KEY,T) .116
11.3 uvm_queue #(T) .118
12. UVM TLM interfaces .120
12.1 Overview .120
12.2 UVM TLM 1 .120
12.3 UVM TLM 2 .138
13. Predefined component classes .159
13.1 uvm_component .159
13.2 uvm_test .172
13.3 uvm_env .173
13.4 uvm_agent .173
13.5 uvm_monitor .174
13.6 uvm_scoreboard .174
13.7 uvm_driver #(REQ,RSP) .175
13.8 uvm_push_driver #(REQ,RSP) .175
13.9 uvm_subscriber .176
14. Sequence classes .177
14.1 uvm_sequence_item .177
14.2 uvm_sequence_base .181
14.3 uvm_sequence #(REQ,RSP) .189
14.4 uvm_sequence_library .191
15. Sequencer classes .194
15.1 Overview .194
15.2 Sequencer interface .195
15.3 uvm_sequencer_base .197
15.4 Common sequencer API .203
15.5 uvm_sequencer #(REQ,RSP).204
15.6 uvm_push_sequencer #(REQ,RSP) .207
16. Policy classes .208
16.1 uvm_policy .208
16.2 uvm_printer .211
16.3 uvm_comparer .226
16.4 uvm_recorder .231
16.5 uvm_packer .240
16.6 uvm_copier .245
17. Register layer .247
17.1 Overview .247
17.2 Global declarations .247
18. Register model .251
18.1 uvm_reg_block .251
Published by IEC under licence from IEEE. © 2020 IEEE. All rights reserved.
– iii – IEEE Std 1800.2™-2020
18.2 uvm_reg_map .263
18.3 uvm_reg_file .271
18.4 uvm_reg .273
18.5 uvm_reg_field .290
18.6 uvm_mem .301
18.7 uvm_reg_indirect_data .315
18.8 uvm_reg_fifo .315
18.9 uvm_vreg .319
18.10 uvm_vreg_field .328
18.11 uvm_reg_cbs .334
18.12 uvm_mem_mam .339
19. Register layer interaction with the design .347
19.1 Generic register operation descriptors .347
19.2 Classes for adapting between register and bus operations .352
19.3 uvm_reg_predictor .353
19.4 Register sequence classes .355
19.5 uvm_reg_backdoor .363
19.6 UVM HDL backdoor access support routines .365
Annex A (informative) Bibliography .367
Annex B (normative) Macros and defines .368
B.1 Report macros .368
B.2 Utility and field macros for components and objects .369
B.3 Sequence-related macros .384
B.4 Callback macros .385
B.5 UVM TLM implementation port declaration macros .387
B.6 Size defines .390
B.7 UVM version globals .391
Annex C (normative) Configuration and resource classes .392
C.1 Overview .392
C.2 Resources .392
C.3 UVM resource database .401
C.4 UVM configuration database .404
Annex D (normative) Convenience classes, interface, and methods .407
D.1 uvm_callback_iter .407
D.2 Component interfaces .408
D.3 uvm_reg_block access methods .412
D.4 Callback typedefs .414
Annex E (normative) Test sequences .416
E.1 uvm_reg_hw_reset_seq .416
E.2 Bit bashing test sequences .416
E.3 Register access test sequences .418
E.4 Shared register and memory access test sequences .420
E.5 Memory access test sequences .422
E.6 Memory walking-ones test sequences .423
E.7 uvm_reg_mem_hdl_paths_seq .425
E.8 uvm_reg_mem_built_in_seq .425
Annex F (normative) Package scope functionality .427
F.1 Overview .427
F.2 Types and enumerations .427
Published by IEC under licence from IEEE. © 2020 IEEE. All rights reserved.
IEEE Std 1800.2™-2020 – iv –
F.3 Methods and types .434
F.4 Core service .438
F.5 Traversal .442
F.6 uvm_run_test_callback .445
F.7 uvm_root .446
Annex G (normative) Command line arguments .450
G.1 Command line processing .450
G.2 Built-in UVM-aware command line arguments .452
Annex H (normative) Deprecation .455
H.1 General .455
H.2 Constructs that have been deprecated .455
Annex I (informative) Participants .457
Published by IEC under licence from IEEE. © 2020 IEEE. All rights reserved.
– v – IEEE Std 1800.2™-2020
SystemVerilog –
Part 2: Universal Verification Methodology Language Reference Manual
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IEEE Std 1800.2™-2020 – vi –
IEC 62530-2/IEEE Std 1800.2 was processed through IEC technical committee 91: Electronics
assembly technology, under the IEC/IEEE Dual Logo Agreement. It is an International
Standard.
The text of this International Standard is based on the following documents:
IEEE Std FDIS Report on voting
1800.2 (2020) 91/1872/FDIS 91/1886/RVD
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
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Published by IEC under licence from IEEE. © 2020 IEEE. All rights reserved.
IEEE Std 1800.2™-2020
IEEE Standard for Universal
Verification Methodology Language
Reference Manual
Developed by the
Design Automation Standards Committee
of the
IEEE Computer Society
Approved 4 June 2020
IEEE SA Standards Board
Published by IEC under licence from IEEE. © 2020 IEEE. All rights reserved.
IEEE Std 1800.2™-2020
Grateful acknowledgment is made for permission to use the following source material:
Accellera Systems Initiative—The Universal Verification Methodology (UVM) Pre-
IEEE Class Reference.
Abstract: The Universal Verification Methodology (UVM) that can improve interoperability, reduce
the cost of using intellectual property (IP) for new projects or electronic design automation (EDA)
tools, and make it easier to reuse verification components is provided. Overall, using this standard
will lower verification costs and improve design quality throughout the industry. The primary
audiences for this standard are the implementors of the UVM base class library, the implementors of
tools supporting the UVM base class library, and the users of the UVM base class library.
Keywords: agent, blocking, callback, class, component, consumer, driver, event, export, factory,
function, generator, IEEE 1800.2™, member, method, monitor, non-blocking, phase, port, register,
resource, sequence, sequencer, transaction-level modeling, verification methodology
•
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IEEE Std 1800.2™-2020
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