Digital addressable lighting interface - Part 101: General requirements - System components

IEC 62386-101:2014 is applicable to system components in a bus system for control by digital signals of electronic lighting equipment. This electronic lighting equipment should be in line with the requirements of IEC 61347, with the addition of d.c. supplies. This second edition cancels and replaces the first edition published in 2009. This edition constitutes a technical revision. This edition includes the following significant technical changes with respect to the previous edition:
a) collection of all bus timing requirements defined in IEC 62386-101:2009 and IEC 62386-102:2009 and rework of the timing requirements to facilitate the preparation of a future control devices standard, taking particular account of the requirements for multi-master systems. The 10 % tolerances have been replaced by minimum and maximum timing values;
b) integration of multi-master timing requirements;
c) extension of the defined forward frames;
d) addition of wiring requirements;
e) improvement of the bus power supply requirements;
f) improvement of test sequences and description of the test sequences in the form of pseudo code instead of flow charts.
This publication is to be read in conjunction with IEC 62386-102:2014.

Interface d'éclairage adressable numérique - Partie 101: Exigences générales - Composants de système

L'IEC 62386-101:2014 est applicable aux composants de système dans un système à bus pour la commande par des signaux numériques des appareils d'éclairage électroniques. Il convient que ces appareils d'éclairage électroniques satisfassent aux exigences de l'IEC 61347, avec en plus les alimentations en courant continu. Cette deuxième édition annule et remplace la première édition parue en 2009. Cette édition constitue une révision technique. Cette édition inclut les modifications techniques majeures suivantes par rapport à l'édition précédente:
a) collecte de toutes les exigences relatives au cadencement des bus définies dans l'IEC 62386-101:2009 et l'IEC 62386-102:2009 et reformulation des exigences relatives au cadencement pour faciliter l'élaboration d'une future norme de dispositifs de commande, en tenant notamment compte des exigences relatives aux systèmes à plusieurs maîtres. Les tolérances de 10 % ont été remplacées par des valeurs de cadencement minimales et maximales;
b) intégration des exigences de cadencement de plusieurs maîtres;
c) extension des trames en avant définies;
d) ajout d'exigences relatives au câblage;
e) amélioration des exigences relatives à l'alimentation électrique du bus;
f) amélioration des séquences d'essai et description des séquences d'essai sous la forme d'un pseudo-code au lieu d'organigrammes.
Cette publication doit être lue conjointement avec la CEI 62386-102:2014.

General Information

Status
Published
Publication Date
06-Nov-2014
Technical Committee
Drafting Committee
Current Stage
DELPUB - Deleted Publication
Start Date
16-Nov-2022
Completion Date
30-Nov-2020
Ref Project

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IEC 62386-101:2014 - Digital addressable lighting interface - Part 101: General requirements - System components
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IEC 62386-101 ®
Edition 2.0 2014-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Digital addressable lighting interface –
Part 101: General requirements – System components

Interface d’éclairage adressable numérique –
Partie 101: Exigences générales – Composants de système
IEC 62386-101:2014-11(en-fr)
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IEC 62386-101 ®
Edition 2.0 2014-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Digital addressable lighting interface –

Part 101: General requirements – System components

Interface d’éclairage adressable numérique –

Partie 101: Exigences générales – Composants de système

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX XC
ICS 29.140, 29.140.50 ISBN 978-2-8322-1910-2

– 2 – IEC 62386-101:2014 © IEC 2014

CONTENTS
FOREWORD . 7
INTRODUCTION . 9
1 Scope . 10
2 Normative references . 10
3 Terms and definitions . 10
4 General . 15
4.1 Purpose . 15
4.2 Version number . 15
4.3 System structure and architecture . 15
4.4 System information flow . 16
4.5 Command types . 16
4.6 Bus units . 17
4.6.1 Transmitters and receivers in bus units . 17
4.6.2 Control gear . 17
4.6.3 Input device . 17
4.6.4 Single master application controller . 17
4.6.5 Multi-master application controller . 18
4.6.6 Sharing an interface . 18
4.7 Bus power supply and load calculations . 19
4.7.1 Current demand coverage . 19
4.7.2 Maximum signal current compliance . 19
4.7.3 Simplified system calculation . 19
4.8 Wiring . 19
4.8.1 Wiring structure . 19
4.8.2 Wiring specification . 19
4.9 Insulation . 20
4.10 Earthing of the bus . 20
4.11 Power interruptions at bus units . 20
4.11.1 Different levels of power interruptions . 20
4.11.2 Short power interruptions of external power supply . 20
4.11.3 External power cycle . 21
4.11.4 Short interruptions of bus power supply . 21
4.11.5 Bus power down . 21
4.11.6 System start-up timing . 21
5 Electrical specification . 23
5.1 General . 23
5.2 Marking of the interface . 23
5.3 Capacitors between the interface and earth . 23
5.4 Signal voltage rating . 23
5.5 Signal current rating. 24
5.6 Marking of bus powered bus unit . 24
5.7 Signal rise time and fall time . 24
6 Bus power supply . 26
6.1 General . 26
6.2 Marking of the bus power supply terminals . 26
6.3 Capacitors between the interface and earth . 26

6.4 Voltage rating . 26
6.5 Current rating. 26
6.5.1 General current rating . 26
6.5.2 Single bus power supply current rating . 27
6.5.3 Integrated bus power supply current rating . 27
6.5.4 Dynamic behaviour of the bus power supply . 27
6.6 Bus power supply timing requirements . 28
6.6.1 Short power supply interruptions . 28
6.6.2 Short circuit behaviour . 29
7 Transmission protocol structure . 29
7.1 General . 29
7.2 Bit encoding . 29
7.2.1 Start bit and data bit encoding . 29
7.2.2 Stop condition encoding . 30
7.3 Frame description . 30
7.4 Frame types . 30
7.4.1 16 bit forward frame . 30
7.4.2 24 bit forward frame . 30
7.4.3 Reserved forward frame . 30
7.4.4 Backward frame . 30
7.4.5 Proprietary forward frames . 30
8 Timing . 31
8.1 Transmitter timing . 31
8.1.1 Transmitter bit timing . 31
8.1.2 Transmitter frame sequence timing . 32
8.2 Receiver timing . 32
8.2.1 Receiver bit timing . 32
8.2.2 Receiver bit timing violation . 34
8.2.3 Receiver frame size violation . 34
8.2.4 Receiver frame sequence timing . 34
8.2.5 Reception of backward frames . 35
8.3 Multi-master transmitter timing . 35
8.3.1 Multi-master transmitter bit timing . 35
8.3.2 Multi-master transmitter frame sequence timing . 36
9 Method of operation . 36
9.1 Collision avoidance, collision detection and collision recovery . 36
9.1.1 General . 36
9.1.2 Collision avoidance . 37
9.1.3 Collision detection . 37
9.1.4 Collision recovery . 38
9.2 Transactions . 39
9.3 Send-twice forward frames and send-twice commands . 40
9.4 Command iteration . 40
9.5 Usage of a shared interface . 41
9.5.1 General . 41
9.5.2 Backward frames . 41
9.5.3 Forward frames . 41
9.6 Use of multiple bus power supplies . 41

– 4 – IEC 62386-101:2014 © IEC 2014

9.7 Command execution . 42
10 Declaration of variables . 42
11 Definition of commands . 42
12 Test procedures . 42
12.1 General notes on test . 42
12.1.1 Abbreviations . 42
12.1.2 Ambient temperature . 42
12.1.3 External power supply voltage and frequency . 43
12.1.4 Measurement requirements . 43
12.1.5 Test signal generators and bus voltage sources . 43
12.1.6 Deviation from documentation . 43
12.1.7 Test setup . 43
12.1.8 Notation . 43
12.2 General interface tests . 49
12.2.1 Label and literature check . 49
12.2.2 Interface marking check . 49
12.2.3 Bus powered bus unit marking check . 50
12.2.4 Bus power supply marking check . 52
12.2.5 Insulation test . 54
12.2.6 Capacitor check . 55
12.3 Bus power supply tests . 55
12.3.1 Voltage rating test . 55
12.3.2 Voltage rise time test . 56
12.3.3 Current rating test . 56
12.3.4 Dynamic behaviour test . 58
12.3.5 Power-on open circuit test . 60
12.3.6 Power-on timing test . 61
12.3.7 Power supply short interruptions test . 62
12.3.8 Power supply short circuit test . 63
12.3.9 Power supply current consumption test . 64
12.4 Control device tests . 65
12.5 Control gear tests . 65
Annex A (informative) Background information for systems . 66
A.1 Wiring information . 66
A.2 System architectures . 67
A.2.1 General . 67
A.2.2 Single master architecture . 67
A.2.3 Multi-master architecture with one application controller . 68
A.2.4 Multi-master architecture with more than one application controller . 69
A.2.5 Multi-master architecture with integrated input device . 70
A.2.6 Multi-master architecture with integrated input device and power supply. 71
A.3 Collision detection . 72
A.4 Timing definition explanations . 73
A.4.1 General . 73
A.4.2 Receiver timing . 73
A.4.3 Transmitter timing . 73
A.4.4 Grey areas . 74
A.5 Maximum current consumption calculation explanation . 74

A.5.1 Single bus power supply . 74
A.5.2 Multiple bus power supplies . 75
A.5.3 Redundant bus power supplies . 76
A.6 Communication layer overview . 77
A.6.1 General . 77
A.6.2 Physical layer . 77
A.6.3 Data link layer . 77
A.6.4 Network layer . 77
A.6.5 Transport layer . 78
A.6.6 Session layer . 78
A.6.7 Presentation layer . 78
A.6.8 Application layer . 78
Bibliography . 79

Figure 1 – IEC 62386 graphical overview . 9
Figure 2 – System structure example . 16
Figure 3 – Communication between bus units (example) . 16
Figure 4 – Example of a shared interface . 18
Figure 5 – Start up timing example . 22
Figure 6 – Maximum signal rise and fall time measurements . 25
Figure 7 – Minimum signal rise and fall time measurements . 25
Figure 8 – Bus power supply current behaviour . 28
Figure 9 – Bus power supply voltage behaviour . 28
Figure 10 – Frame example . 29
Figure 11 – Bi-phase encoded bits . 30
Figure 12 – Bit timing example . 31
Figure 13 – Settling time illustration . 32
Figure 14 – Receiver timing decision example . 34
Figure 15 – Collision detection timing decision example . 38
Figure 16 – Collision recovery example . 39
Figure 17 – Current rating test signal . 57
Figure 18 – Dynamic behaviour test setup . 58
Figure 19 – Dynamic behaviour test signal . 59
Figure A.1 – Single master architecture example . 68
Figure A.2 – Multi-master architecture example with one application controller . 69
Figure A.3 – Multi-master architecture example with two application controllers . 70
Figure A.4 – Multi-master architecture example with integrated input device . 71
Figure A.5 – Multi-master architecture example with integrate input device and bus
power supply . 72
Figure A.6 – Collision detection timing diagram. 73
Figure A.7 – Transmitter and receiver timing illustration . 74
Figure A.8 – Bus power supply current values. 75
Figure A.9 – Current demand coverage . 75
Figure A.10 – Combination of 4 bus power supplies . 76
Figure A.11 – Redundant bus power supplies . 76

– 6 – IEC 62386-101:2014 © IEC 2014

Table 1 – System components . 15
Table 2 – Transmitters and receivers in bus units . 17
Table 3 – Power-interruption timing of external power . 20
Table 4 – Power-interruption timing of bus power . 20
Table 5 – Short power interruptions . 21
Table 6 – Start-up timing. 22
Table 7 – System voltage levels . 23
Table 8 – Receiver voltage levels . 23
Table 9 – Transmitter voltage levels . 24
Table 10 – Current rating . 24
Table 11 – Signal rise and fall times . 25
Table 12 – Bus power supply output voltage . 26
Table 13 – Bus power supply current rating . 27
Table 14 – Bus power supply dynamic behaviour . 27
Table 15 – Short circuit timing behaviour . 29
Table 16 – Transmitter bit timing . 32
Table 17 – Transmitter settling time values . 32
Table 18 – Receiver timing starting at the beginning of a logical bit . 33
Table 19 – Receiver timing starting at an edge inside of a logical bit . 33
Table 20 – Receiver settling time values . 35
Table 21 – Multi-master transmitter bit timing. 35
Table 22 – Multi-master transmitter settling time values . 36
Table 23 – Checking a logical bit, starting at an edge at the beginning of the bit . 37
Table 24 – Checking a logical bit, starting at an edge inside the bit . 38
Table 25 – Collision recovery timing . 39
Table 26 – Transmitter command iteration timing . 41
Table 27 – Receiver command iteration timing . 41
Table 28 – Function call keywords . 44
Table 29 – Defined operators . 47
Table A.1 – Maximum cable length . 67
Table A.2 – OSI layer model of IEC 62386 . 77

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
DIGITAL ADDRESSABLE LIGHTING INTERFACE –

Part 101: General requirements –
System components
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
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2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
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between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
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5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
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6) All users should ensure that they have the latest edition of this publication.
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Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 62386-101 has been prepared by subcommittee 34C: Auxiliaries
for lamps, of IEC technical committee 34: Lamps and related equipment.
This second edition cancels and replaces the first edition published in 2009. This edition
constitutes a technical revision.
This edition includes the following significant technical changes with respect to the previous
edition:
a) collection of all bus timing requirements defined in IEC 62386-101:2009 and
IEC 62386-102:2009 and rework of the timing requirements to facilitate the preparation of
a future control devices standard, taking particular account of the requirements for multi-
master systems. The 10 % tolerances have been replaced by minimum and maximum
timing values;
b) integration of multi-master timing requirements;

– 8 – IEC 62386-101:2014 © IEC 2014

c) extension of the defined forward frames;
d) addition of wiring requirements;
e) improvement of the bus power supply requirements;
f) improvement of test sequences and description of the test sequences in the form of
pseudo code instead of flow charts.
The text of this standard is based on the following documents:
FDIS Report on voting
34C/1098/FDIS 34C/1111/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This Part 101 is intended to be used in conjunction with:
• Part 102, which contains general requirements for the relevant product type (control gear),
and with the appropriate Part 2xx (particular requirements for control gear);
• Part 103, which contains general requirements for the relevant product type (control
devices), and the appropriate Part 3xx (particular requirements for control devices).
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts of the IEC 62386 series, under the general title: Digital addressable lighting
interface, can be found on the IEC website
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
INTRODUCTION
IEC 62386 contains several parts, referred to as series. The 1xx series includes the basic
specifications. Part 101 contains general requirements for system components, Part 102
extends this information with general requirements for control gear and Part 103 extends it
further with general requirements for control devices.
The 2xx parts extend the general requirements for control gear with lamp specific extensions
(mainly for backward compatibility with Edition 1 of IEC 62386) and with control gear specific
features.
The 3xx parts extend the general requirements for control devices with input device specific
extensions describing the instance types as well as some common features that can be
combined with multiple instance types.
This second edition of IEC 62386-101 is published in conjunction with IEC 62386-102:2014
and with the various parts that make up the IEC 62386-2xx series for control gear, together
with IEC 62386-103:2014 and the various parts that make up the IEC 62386-3xx series of
particular requirements for control devices. The division into separately published parts
provides for ease of future amendments and revisions. Additional requirements will be added
as and when a need for them is recognised.
The setup of the standard is graphically represented in Figure 1 below.

2xx 2xx 2xx 2xx 2xx 3xx 3xx 3xx 3xx 3xx
102 General requirements - 103 General requirements -
Control gear Control devices
101 General requirements -
System components
IEC
Figure 1 – IEC 62386 graphical overview
When this part of IEC 62386 refers to any of the clauses of the other two parts of the
IEC 62386-1xx series, the extent to which such a clause is applicable and the order in which
the tests are to be performed are specified. The other parts also include additional
requirements, as necessary.
All numbers used in this International Standard are decimal numbers unless otherwise noted.
Hexadecimal numbers are given in the format 0xVV, where VV is the value. Binary numbers
are given in the format XXXXXXXXb or in the format XXXX XXXX, w here X is 0 or 1, "x" in
binary numbers means "don't care".

– 10 – IEC 62386-101:2014 © IEC 2014

DIGITAL ADDRESSABLE LIGHTING INTERFACE –

Part 101: General requirements –
System components
1 Scope
This part of IEC 62386 is applicable to system components in a bus system for control by
digital signals of electronic lighting equipment. This electronic lighting equipment should be in
line with the requirements of IEC 61347, with the addition of d.c. supplies.
NOTE Tests in this standard are type tests. Requirements for testing individual bus units during production are
not included.
2 Normative references
The following documents, in whole or in part, are normatively referenced in this document and
are indispensable for its application. For dated references, only the edition cited applies. For
undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 61347 (all parts), Lamp controlgear
IEC 61347-1, Lamp controlgear – Part 1: General and safety requirements
IEC 62386-102:2014, Digital addressable lighting interface – Part 102: General requirements
– Control gear
IEC 62386-103:2014, Digital addressable lighting interface – Part 103: General requirements
– Control devices
IEC 61000-4-11, Electromagnetic compatibility (EMC) – Part 4-11:Testing and measurement
techniques – Voltage dips, short interruptions and voltage variations immunity tests
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
3.1
active state
phase of low level voltage during a transmission
Note 1 to entry: Noise and short pulses may be ignored and therefore do not change the state.
3.2
advanced bus power supply
bus power supply capable of checking the bus for fault conditions before switching on its
output continuously
Note 1 to entry: Examples of fault conditions are mains voltage connected to the bus or short circuit of the bus.

3.3
application controller
control device that is connected to the bus and sends commands in order to control input
devices and/or control gear connected to the same bus
3.4
backward frame
frame used for backward transmission
3.5
backward transmission
transmission of data as a reply to and triggered by a forward transmission
3.6
bus
two-wire connection line carrying power and frames
3.7
bus powered
drawing the power for operation from the bus
3.8
bus power down
bus power interruption longer than 45 ms
3.9
bus power interruption
abnormal condition where the bus voltage is in the receiver low level voltage range, but not
because of a transmitter being active
3.10
bus power supply
unit feeding defined energy to the bus
3.11
bus unit
logical unit or combination of logical units, containing one transmitter and optionally one
receiver
Note 1 to entry: See 4.6.6.
3.12
charge overshoot
product of current overshoot time and current overshoot amplitude
Note 1 to entry: Within this standard the charge overshoot is a simple multiplication of the current overshoot time
and the current overshoot amplitude.
3.13
collision
situation in which two or more transmitters are transmitting simultaneously
Note 1 to entry: Collisions can go unnoticed if the transmission timing is sufficiently similar and
...


IEC 62386-101 ®
Edition 2.1 2018-05
CONSOLIDATED VERSION
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Digital addressable lighting interface –
Part 101: General requirements – System components

Interface d’éclairage adressable numérique –
Partie 101: Exigences générales – Composants de système

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IEC 62386-101 ®
Edition 2.1 2018-05
CONSOLIDATED VERSION
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Digital addressable lighting interface –

Part 101: General requirements – System components

Interface d’éclairage adressable numérique –

Partie 101: Exigences générales – Composants de système

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 29.140.50; 29.140.99 ISBN 978-2-8322-5753-1

IEC 62386-101 ®
Edition 2.1 2018-05
CONSOLIDATED VERSION
REDLINE VERSION
VERSION REDLINE
colour
inside
Digital addressable lighting interface –
Part 101: General requirements – System components

Interface d’éclairage adressable numérique –
Partie 101: Exigences générales – Composants de système

– 2 – IEC 62386-101:2014+AMD1:2018 CSV

© IEC 2018
CONTENTS
FOREWORD . 7

INTRODUCTION . 9

1 Scope . 10

2 Normative references . 10

3 Terms and definitions . 10

4 General . 15

4.1 Purpose . 15
4.2 Version number . 15
4.3 System structure and architecture . 16
4.4 System information flow . 16
4.5 Command types . 17
4.6 Bus units . 17
4.6.1 Transmitters and receivers in bus units . 17
4.6.2 Control gear . 18
4.6.3 Input device . 18
4.6.4 Single master application controller . 18
4.6.5 Multi-master application controller . 19
4.6.6 Sharing an interface . 19
4.7 Bus power supply and load calculations . 20
4.7.1 Current demand coverage . 20
4.7.2 Maximum signal current compliance . 20
4.7.3 Simplified system calculation . 20
4.8 Wiring . 20
4.8.1 Wiring structure . 20
4.8.2 Wiring specification . 20
4.9 Insulation . 21
4.10 Earthing of the bus . 21
4.11 Power interruptions at bus units . 21
4.11.1 Different levels of power interruptions . 21
4.11.2 Short power interruptions of external power supply . 21
4.11.3 External power cycle . 22
4.11.4 Short interruptions of bus power supply . 22

4.11.5 Bus power down . 22
4.11.6 System start-up timing . 22
5 Electrical specification . 24
5.1 General . 24
5.2 Marking of the interface . 24
5.3 Capacitors between the interface and earth . 24
5.4 Signal voltage rating . 24
5.5 Signal current rating. 25
5.6 Marking of bus powered bus unit . 25
5.7 Signal rise time and fall time . 26
6 Bus power supply . 27
6.1 General . 27
6.2 Marking of the bus power supply terminals . 27
6.3 Capacitors between the interface and earth . 27

© IEC 2018
6.4 Voltage rating . 27

6.5 Current rating. 28

6.5.1 General current rating . 28

6.5.2 Single bus power supply current rating . 28

6.5.3 Integrated bus power supply current rating . 28

6.5.4 Dynamic behaviour of the bus power supply . 28

6.6 Bus power supply timing requirements . 30

6.6.1 Short power supply interruptions . 30

6.6.2 Short circuit behaviour . 30

7 Transmission protocol structure . 31

7.1 General . 31
7.2.1 Start bit and data bit encoding . 31
7.2 Bit encoding . 31
7.2.2 Stop condition encoding . 31
7.3 Frame description . 31
7.4 Frame types . 32
7.4.1 16 bit forward frame . 32
7.4.2 24 bit forward frame . 32
7.4.3 Reserved forward frame . 32
7.4.4 Backward frame . 32
7.4.5 Proprietary forward frames . 32
8 Timing . 33
8.1 Transmitter timing . 33
8.1.1 Transmitter bit timing . 33
8.1.2 Transmitter frame sequence timing . 33
8.2 Receiver timing . 34
8.2.1 Receiver bit timing . 34
8.2.2 Receiver bit timing violation . 35
8.2.3 Receiver frame size violation . 36
8.2.4 Receiver frame sequence timing . 36
8.2.5 Reception of backward frames . 37
8.3 Multi-master transmitter timing . 37
8.3.1 Multi-master transmitter bit timing . 37
8.3.2 Multi-master transmitter frame sequence timing . 37
9 Method of operation . 38

9.8 Dealing with frames and commands . 38
9.8.1 General . 38
9.8.2 Frame received or rejected . 39
9.8.3 Frame accepted or ignored . 39
9.8.4 Command accepted or ignored . 39
9.8.5 Command executed or discarded . 39
9.1 Collision avoidance, collision detection and collision recovery . 40
9.1.1 General . 40
9.1.2 Collision avoidance . 40
9.1.3 Collision detection . 40
9.1.4 Collision recovery . 42
9.2 Transactions . 43
9.3 Send-twice forward frames and send-twice commands . 43

– 4 – IEC 62386-101:2014+AMD1:2018 CSV

© IEC 2018
9.4 Command iteration . 44

9.5 Usage of a shared interface . 44

9.5.1 General . 44

9.5.2 Backward frames . 45

9.5.3 Forward frames . 45

9.6 Use of multiple bus power supplies . 45

9.7 Command execution . 45

10 Declaration of variables . 45

11 Definition of commands . 46

12 Test procedures . 46
12.1 General notes on test .
12.1.1 Abbreviations .
12.1.2 Ambient temperature .
12.1.3 External power supply voltage and frequency .
12.1.4 Measurement requirements .
12.1.5 Test signal generators and bus voltage sources .
12.1.6 Deviation from documentation .
12.1.7 Test setup .
12.1.8 Notation .
12.2 General interface tests .
12.2.1 Label and literature check .
12.2.2 Interface marking check .
12.2.3 Bus powered bus unit marking check .
12.2.4 Bus power supply marking check .
12.2.5 Insulation test .
12.2.6 Capacitor check .
12.3 Bus power supply tests .
12.3.1 Voltage rating test .
12.3.2 Voltage rise time test .
12.3.3 Current rating test .
12.3.4 Dynamic behaviour test .
12.3.5 Power-on open circuit test .
12.3.6 Power-on timing test .
12.3.7 Power supply short interruptions test .
12.3.8 Power supply short circuit test .

12.3.9 Power supply current consumption test .
12.4 Control device tests .
12.5 Control gear tests .
Annex A (informative)   Background information for systems . 70
A.1 Wiring information . 70
A.2 System architectures . 71
A.2.1 General . 71
A.2.2 Single master architecture . 71
A.2.3 Multi-master architecture with one application controller . 72
A.2.4 Multi-master architecture with more than one application controller . 73
A.2.5 Multi-master architecture with integrated input device . 74
A.2.6 Multi-master architecture with integrated input device and power supply. 75
A.3 Collision detection . 76

© IEC 2018
A.4 Timing definition explanations . 77

A.4.1 General . 77

A.4.2 Receiver timing . 77

A.4.3 Transmitter timing . 77

A.4.4 Grey areas . 78

A.5 Maximum current consumption calculation explanation . 78

A.5.1 Single bus power supply . 78

A.5.2 Multiple bus power supplies . 79

A.5.3 Redundant bus power supplies . 80

A.6 Communication layer overview . 81

A.6.1 General . 81
A.6.2 Physical layer . 81
A.6.3 Data link layer . 81
A.6.4 Network layer . 81
A.6.5 Transport layer . 82
A.6.6 Session layer . 82
A.6.7 Presentation layer . 82
A.6.8 Application layer . 82
A.7 Effects on combining version number 1 and version number 2.y devices . 82
Bibliography . 83

Figure 1 – IEC 62386 graphical overview . 9
Figure 2 – System structure example . 16
Figure 3 – Communication between bus units (example) . 17
Figure 4 – Example of a shared interface . 19
Figure 5 – Start up timing example . 23
Figure 6 – Maximum signal rise and fall time measurements . 26
Figure 7 – Minimum signal rise and fall time measurements . 27
Figure 8 – Bus power supply current behaviour . 29
Figure 9 – Bus power supply voltage behaviour . 30
Figure 10 – Frame example . 31
Figure 11 – Bi-phase encoded bits . 31
Figure 12 – Bit timing example . 33

Figure 13 – Settling time illustration . 33
Figure 14 – Receiver timing decision example . 35
Figure 15 – Collision detection timing decision example . 42
Figure 16 – Collision recovery example . 43
Figure 17 – Current rating test signal .
Figure 18 – Dynamic behaviour test setup .
Figure 19 – Dynamic behaviour test signal .
Figure 20 – Dealing with frames and commands . 39
Figure A.1 – Single master architecture example . 72
Figure A.2 – Multi-master architecture example with one application controller . 73
Figure A.3 – Multi-master architecture example with two application controllers . 74
Figure A.4 – Multi-master architecture example with integrated input device . 75

– 6 – IEC 62386-101:2014+AMD1:2018 CSV

© IEC 2018
Figure A.5 – Multi-master architecture example with integrate input device and bus

power supply . 76

Figure A.6 – Collision detection timing diagram. 77

Figure A.7 – Transmitter and receiver timing illustration . 78

Figure A.8 – Bus power supply current values. 79

Figure A.9 – Current demand coverage . 79

Figure A.10 – Combination of 4 bus power supplies . 80

Figure A.11 – Redundant bus power supplies . 80

Table 1 – System components . 16
Table 2 – Transmitters and receivers in bus units . 18
Table 3 – Power-interruption timing of external power . 21
Table 4 – Power-interruption timing of bus power . 21
Table 5 – Short power interruptions . 22
Table 6 – Start-up timing. 23
Table 7 – System voltage levels . 24
Table 8 – Receiver voltage levels . 25
Table 9 – Transmitter voltage levels . 25
Table 10 – Current rating . 25
Table 11 – Signal rise and fall times . 26
Table 12 – Bus power supply output voltage . 28
Table 13 – Bus power supply current rating . 28
Table 14 – Bus power supply dynamic behaviour . 29
Table 15 – Short circuit timing behaviour . 30
Table 16 – Transmitter bit timing . 33
Table 17 – Transmitter settling time values . 34
Table 18 – Receiver timing starting at the beginning of a logical bit . 35
Table 19 – Receiver timing starting at an edge inside of a logical bit . 35
Table 20 – Receiver settling time values . 36
Table 21 – Multi-master transmitter bit timing. 37
Table 22 – Multi-master transmitter settling time values . 38

Table 23 – Checking a logical bit, starting at an edge at the beginning of the bit . 41
Table 24 – Checking a logical bit, starting at an edge inside the bit . 41
Table 25 – Collision recovery timing . 42
Table 26 – Transmitter command iteration timing . 44
Table 27 – Receiver command iteration timing . 44
Table 28 – Function call keywords .
Table 29 – Defined operators .
Table A.1 – Maximum cable length . 71
Table A.2 – OSI layer model of IEC 62386 . 81
Table A.3 – Effects on combining version number 1 and version number 2.y devices . 82

© IEC 2018
INTERNATIONAL ELECTROTECHNICAL COMMISSION

____________
DIGITAL ADDRESSABLE LIGHTING INTERFACE –

Part 101: General requirements –

System components
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.

This consolidated version of the official IEC Standard and its amendment has been prepared
for user convenience.
IEC 62386-101 edition 2.1 contains the second edition (2014-11) [documents 34C/1098/FDIS and
34C/1111/RVD] and its amendment 1 (2018-05) [documents 34/418/CDV and 34/502/RVC].
In this Redline version, a vertical line in the margin shows where the technical content is
modified by amendment 1. Additions are in green text, deletions are in strikethrough red text.
A separate Final version with all changes accepted is available in this publication.

– 8 – IEC 62386-101:2014+AMD1:2018 CSV

© IEC 2018
International Standard IEC 62386-101 has been prepared by subcommittee 34C: Auxiliaries

for lamps, of IEC technical committee 34: Lamps and related equipment.

This second edition constitutes a technical revision.

This edition includes the following significant technical changes with respect to the previous

edition:
a) collection of all bus timing requirements defined in IEC 62386-101:2009 and

IEC 62386-102:2009 and rework of the timing requirements to facilitate the preparation of

a future control devices standard, taking particular account of the requirements for multi-

master systems. The 10 % tolerances have been replaced by minimum and maximum
timing values;
b) integration of multi-master timing requirements;
c) extension of the defined forward frames;
d) addition of wiring requirements;
e) improvement of the bus power supply requirements;
f) improvement of test sequences and description of the test sequences in the form of
pseudo code instead of flow charts.
This Part 101 is intended to be used in conjunction with:
• Part 102, which contains general requirements for the relevant product type (control gear),
and with the appropriate Part 2xx (particular requirements for control gear);
• Part 103, which contains general requirements for the relevant product type (control
devices), and the appropriate Part 3xx (particular requirements for control devices).
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts of the IEC 62386 series, under the general title: Digital addressable lighting
interface, can be found on the IEC website
The committee has decided that the contents of the base publication and its amendment will
remain unchanged until the stability date indicated on the IEC web site under
"http://webstore.iec.ch" in the data related to the specific publication. At this date, the
publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or

• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
© IEC 2018
INTRODUCTION
IEC 62386 contains several parts, referred to as series. The 1xx series includes the basic

specifications. Part 101 contains general requirements for system components, Part 102

extends this information with general requirements for control gear and Part 103 extends it

further with general requirements for control devices.

The 2xx parts extend the general requirements for control gear with lamp specific extensions

(mainly for backward compatibility with Edition 1 of IEC 62386) and with control gear specific

features.
The 3xx parts extend the general requirements for control devices with input device specific
extensions describing the instance types as well as some common features that can be
combined with multiple instance types.
This second edition of IEC 62386-101 is published intended to be used in conjunction with
IEC 62386-102:2014 and IEC 62386-102:2014/AMD1:— and with the various parts that make
up the IEC 62386-2xx series for control gear, together with IEC 62386-103:2014 and
IEC 62386-103:2014/AMD1:— and the various parts that make up the IEC 62386-3xx series
of particular requirements for control devices. The division into separately published parts
provides for ease of future amendments and revisions. Additional requirements will be added
as and when a need for them is recognised.
The setup of the standard is graphically represented in Figure 1 below.

2xx 2xx 2xx 2xx 2xx 3xx 3xx 3xx 3xx 3xx
102 General requirements - 103 General requirements -
Control gear Control devices
101 General requirements -
System components
IEC
Figure 1 – IEC 62386 graphical overview
When this part of IEC 62386 refers to any of the clauses of the other two parts of the
IEC 62386-1xx series, the extent to which such a clause is applicable and the order in which
the tests are to be performed are specified. The other parts also include additional
requirements, as necessary.
All numbers used in this International Standard are decimal numbers unless otherwise noted.
Hexadecimal numbers are given in the format 0xVV, where VV is the value. Binary numbers
are given in the format XXXXXXXXb or in the format XXXX XXXX, w here X is 0 or 1, "x" in
binary numbers means "don't care".

– 10 – IEC 62386-101:2014+AMD1:2018 CSV

© IEC 2018
DIGITAL ADDRESSABLE LIGHTING INTERFACE –

Part 101: General requirements –

System components
1 Scope
This part of IEC 62386 is applicable to system components in a bus system for control by
digital signals of electronic lighting equipment which is in line with the requirements of
IEC 61347 (all parts), with the addition of DC supplies. This electronic lighting equipment
should be in line with the requirements of IEC 61347, with the addition of d.c. supplies.
NOTE Tests in this standard are type tests. Requirements for testing individual bus units during production are
not included.
2 Normative references
The following documents, in whole or in part, are normatively referenced in this document and
are indispensable for its application are referred to in the text in such a way that some or all
of their content constitutes requirements of this document. For dated references, only the
edition cited applies. For undated references, the latest edition of the referenced document
(including any amendments
...

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