SIST EN 62878-1-1:2015

2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.Element z ugnezdenim substratom - Rodovna specifikacija - Preskusna metodaTrägermaterial mit eingebetteten Bauteilen - Teil 1-1: Fachgrundspezifikation - PrüfverfahrenSubstrat avec appareil(s) intégré(s) - Partie 1-1: Spécification générique - Méthodes d'essaiDevice embedded substrate - Generic specification - Test method31.190Sestavljeni elektronski elementiElectronic component assemblies31.180SORãþHPrinted circuits and boardsICS:Ta slovenski standard je istoveten z:EN 62878-1-1:2015SIST EN 62878-1-1:2015en01-september-2015SIST EN 62878-1-1:2015SLOVENSKI
STANDARD
EUROPEAN STANDARD NORME EUROPÉENNE EUROPÄISCHE NORM
EN 62878-1-1
July 2015 ICS 31.180; 31.190
English Version
Device embedded substrate -
Part 1-1: Generic specification - Test methods (IEC 62878-1-1:2015)
Substrat avec appareil(s) intégré(s) -
Partie 1-1: Spécification générique - Méthodes d'essai (IEC 62878-1-1:2015)
Trägermaterial mit eingebetteten Bauteilen -
Teil 1-1: Fachgrundspezifikation - Prüfverfahren (IEC 62878-1-1:2015) This European Standard was approved by CENELEC on 2015-06-24. CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC Management Centre or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the same status as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and the United Kingdom. European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique Europäisches Komitee für Elektrotechnische Normung CEN-CENELEC Management Centre: Avenue Marnix 17,
B-1000 Brussels © 2015 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members.
Ref. No. EN 62878-1-1:2015 E SIST EN 62878-1-1:2015

The following dates are fixed: • latest date by which the document has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2016-03-24 • latest date by which the national standards conflicting with the document have to be withdrawn (dow) 2018-06-24
Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights. CENELEC [and/or CEN] shall not be held responsible for identifying any or all such patent rights.
Endorsement notice The text of the International Standard IEC 62878-1-1:2015 was approved by CENELEC as a European Standard without any modification. In the official version, for Bibliography, the following notes have to be added for the standards indicated:
IEC 60068-1 NOTE Harmonized as EN 60068-1. IEC 60068-2-6 NOTE Harmonized as EN 60068-2-6. IEC 60068-2-14 NOTE Harmonized as EN 60068-2-14. IEC 60068-2-20 NOTE Harmonized as EN 60068-2-20. IEC 60068-2-21 NOTE Harmonized as EN 60068-2-21. IEC 60068-2-30 NOTE Harmonized as EN 60068-2-30. IEC 60068-2-38 NOTE Harmonized as EN 60068-2-38. IEC 60068-2-53 NOTE Harmonized as EN 60068-2-53. IEC 60068-2-58 NOTE Harmonized as EN 60068-2-58. IEC 60068-2-64 NOTE Harmonized as EN 60068-2-64. IEC 60068-2-66 NOTE Harmonized as EN 60068-2-66. IEC 60068-2-78 NOTE Harmonized as EN 60068-2-78. IEC 60068-2-80 NOTE Harmonized as EN 60068-2-80. IEC 61189-1 NOTE Harmonized as EN 61189-1. IEC 61189-2 NOTE Harmonized as EN 61189-2. IEC 61189-11 NOTE Harmonized as EN 61189-11. IEC 61190-1-2 NOTE Harmonized as EN 61190-1-2. IEC 61190-1-3 NOTE Harmonized as EN 61190-1-3. IEC 62137-1-2 NOTE Harmonized as EN 62137-1-2. IEC 62137-1-3 NOTE Harmonized as EN 62137-1-3. IEC 62421 NOTE Harmonized as EN 62421. ISO 291 NOTE Harmonized as EN ISO 291. SIST EN 62878-1-1:2015

Normative references to international publications with their corresponding European publications
The following documents, in whole or in part, are normatively referenced in this document and are indispensable for its application. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies.
NOTE 1 When an International Publication has been modified by common modifications, indicated by (mod), the relevant EN/HD applies.
NOTE 2 Up-to-date information on the latest versions of the European Standards listed in this annex is available here: www.cenelec.eu
Publication Year Title EN/HD Year
IEC 60068-2-1 -
Environmental testing -
Part 2-1: Tests - Test A: Cold EN 60068-2-1 -
IEC 60068-2-2 -
Environmental testing -
Part 2-2: Tests - Test B: Dry heat EN 60068-2-2 -
IEC 60194 -
Printed board design, manufacture
and assembly - Terms and definitions EN 60194 -
IEC 61189-3 -
Test methods for electrical materials, printed boards and other interconnection structures and assemblies -
Part 3: Test methods for interconnection structures (printed boards) EN 61189-3 -
IEC/TS 62878-2-4 2015
Device embedded substrate -
Part 2-4: Guidelines - Test element groups (TEG) - -
IEC 62878-1-1 Edition 1.0 2015-05 INTERNATIONAL STANDARD NORME INTERNATIONALE Device embedded substrate –
Part 1-1: Generic specification – Test methods
Substrat avec appareil(s) intégré(s) –
Partie 1-1: Spécification générique – Méthodes d'essai
INTERNATIONAL ELECTROTECHNICAL COMMISSION COMMISSION ELECTROTECHNIQUE INTERNATIONALE
ICS 31.180; 31.190
ISBN 978-2-8322-2674-2
– 2 – IEC 62878-1-1:2015 © IEC 2015 CONTENTS FOREWORD . 5 1 Scope . 7 2 Normative references . 7 3 Terms, definitions and abbreviations . 7 3.1 Terms and definitions . 7 3.2 Abbreviations . 7 4 Test methods . 8 4.1 General . 8 4.2 Visual inspection and micro-sectioning. 8 4.2.1 General . 8 4.2.2 Visual inspection . 8 4.2.3 Micro-sectioning . 8 4.2.4 Lack of conductor and residue of conductor . 10 4.2.5 Land dimension and land width (annular ring) . 10 4.3 Electrical tests . 13 4.3.1 Conductor resistance . 13 4.3.2 Through hole and build-up via . 14 4.3.3 Withstanding current of embedded device connection . 15 4.3.4 Withstanding voltage in embedded boards . 17 4.3.5 Insulation resistance . 19 4.3.6 Conduction and insulation of circuit . 20 4.4 Mechanical tests . 20 4.4.1 Pulling strength of conductor . 20 4.4.2 Pulling strength of un-plated through hole . 21 4.4.3 Pulling strength of plated through hole . 22 4.4.4 Pulling strength of pad of land pattern . 22 4.4.5 Adhesivity of plated foil . 23 4.4.6 Adhesivity of solder resist and symbol mark. 24 4.4.7 Hardness of painted film (solder resist and symbol mark) . 28 4.5 Environmental tests . 29 4.5.1 General . 29 4.5.2 Vapour phase thermal shock . 30 4.5.3 High temperature immersion tests . 30 4.5.4 Resistance to humidity . 31 4.6 Mechanical environmental test – Resistance to migration . 34 4.6.1 General . 34 4.6.2 Equipment . 34 4.6.3 Specimen . 35 4.6.4 Test condition . 35 5 Shipping inspection . 36 5.1 General . 36 5.2 Electrical test . 37 5.2.1 General . 37 5.2.2 Test of conductor pattern not connected to an embedded component . 38 5.2.3 Test on the pattern having a passive component and a conductor pattern . 40 SIST EN 62878-1-1:2015

IEC 62878-1-1:2015 © IEC 2015 – 3 – 5.2.4 Test of a circuit having both active component(s) and a conductor pattern . 43 5.2.5 Test of a circuit having connections of both individual passive component(s) and conductor pattern . 46 5.2.6 Test of a circuit having an embedded component which cannot be checked from the surface and a conductor pattern . 47 5.3 Internal transparent test . 47 5.4 Visual test . 47 Annex A (informative)
Related test methods . 49 Bibliography . 52
Figure 1 – Measuring items of the micro-sectioned through hole structure . 9 Figure 2 – Measuring items of the micro-sectioned device
embedded board with build-up structure . 9 Figure 3 – Measurement of land dimension . 11 Figure 4 – Build-up land measurement . 12 Figure 5 – Conductor resistance measurement . 14 Figure 6 – Relationship between current, conductor width and thickness and temperature rise . 17 Figure 7 – Adhesivity of plated film . 24 Figure 8 – Single cutting tool . 25 Figure 9 – Cutter knife . 25 Figure 10 – Multiple blade cutter . 26 Figure 11 – Equal-distance spacer with guide . 26 Figure 12 – Cutting using a single cutting tool or a cutting knife . 27 Figure 13 – Cross-cut test . 28 Figure 14 – Coated film hardness test . 29 Figure 15 – Temperature and humidity cycles . 33 Figure 16 – Device embedded board for shipping inspection . 36 Figure 17 – Typical circuit construction of device embedded board . 37 Figure 18 – Examples of evaluation levels of electrical test . 39 Figure 19 – Circuit construction not connected to embedded component . 39 Figure 20 – Circuit construction which is capable of independent check . 40 Figure 21 – Circuit construction for parallel connection of passive components . 42 Figure 22 – Circuit construction for series connection of passive components . 43 Figure 23 – Circuit construction of embedded diode . 44 Figure 24 – Circuit construction of transistor circuit . 44 Figure 25 – Circuit construction of a conductor pattern with embedded IC and LSI . 45 Figure 26 – Circuit construction composed of a passive component and
an active component . 46 Figure 27 – Circuit construction of embedded components
having no connection terminal on the surface . 47
Table 1 – Test items, characteristics and observations
of micro-sectioned specimens . 9 Table 2 – Test method for coplanarity around the land pattern . 12 Table 3 – Characteristics and test methods for conductor resistance . 15 SIST EN 62878-1-1:2015

– 4 – IEC 62878-1-1:2015 © IEC 2015 Table 4 – Withstanding current and test methods . 16 Table 5 – Withstanding voltage and test methods . 18 Table 6 – Criteria and test methods for insulation resistance . 20 Table 7 – Characteristics and test method of pulling strength of conductor . 21 Table 8 – Dimensions of land, hole and conductor . 22 Table 9 – Characteristics and test methods of pulling strength of plated through hole . 22 Table 10 – Specification and test method of pad pulling strength of land pattern . 23 Table 11 – High and low temperature characteristics and tests . 30 Table 12 – Thermal shock characteristics and test methods . 30 Table 13 – Thermal shock (high temperature immersion test) . 31 Table 14 – Measuring environment . 31 Table 15 – Thermal shock (high temperature immersion tests) . 31 Table 16 – Resistance to humidity characteristics and test methods . 34 Table 17 – Resistance to migration characteristics and test methods . 35 Table 18 – Applicable items of shipping inspection . 37 Table A.1 – Related test methods . 49
IEC 62878-1-1:2015 © IEC 2015 – 5 – INTERNATIONAL ELECTROTECHNICAL COMMISSION ____________
DEVICE EMBEDDED SUBSTRATE –
Part 1-1: Generic specification – Test methods
FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with may participate in this preparatory work. International, governmental and non-governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions determined by agreement between the two organizations. 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any misinterpretation by any end user. 4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications transparently to the maximum extent possible in their national and regional publications. Any divergence between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter. 5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any services carried out by independent certification bodies. 6) All users should ensure that they have the latest edition of this publication. 7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and members of its technical committees and IEC National Committees for any personal injury, property damage or other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is indispensable for the correct application of this publication. 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. International Standard IEC 62878-1-1 has been prepared by IEC technical committee 91: Electronics assembly technology. The text of this standard is based on the following documents: FDIS Report on voting 91/1248/FDIS 91/1260/RVD
Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above table. A list of all parts in the IEC 62878, published under the general title Device embedded substrate, can be found on the IEC website. This publication has been drafted in accordance with the ISO/IEC Directives, Part 2. SIST EN 62878-1-1:2015

– 6 – IEC 62878-1-1:2015 © IEC 2015 The committee has decided that the contents of this publication will remain unchanged until the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data related to the specific publication. At this date, the publication will be
• reconfirmed, • withdrawn, • replaced by a revised edition, or • amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates that it contains colours which are considered to be useful for the correct understanding of its contents. Users should therefore print this document using a colour printer.
IEC 62878-1-1:2015 © IEC 2015 – 7 – DEVICE EMBEDDED SUBSTRATE –
Part 1-1: Generic specification – Test methods
1 Scope This part of IEC 62878 specifies the test methods of passive and active device embedded substrates. The basic test methods of printed wiring substrate materials and substrates themselves are specified in IEC 61189-3. This part of IEC 62878 is applicable to device embedded substrates fabricated by use of organic base material, which include for example active or passive devices, discrete components formed in the fabrication process of electronic wiring board, and sheet formed components.
The IEC 62878 series neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as an M-type business model in IEC 62421. 2 Normative references The following documents, in whole or in part, are normatively referenced in this document and are indispensable for its application. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies. IEC 60068-2-1, Environmental testing – Part 2-1: Tests – Test A: Cold IEC 60068-2-2, Environmental testing – Part 2-2: Tests – Test B: Dry heat IEC 60194, Printed board design, manufacture and assembly – Terms and definitions IEC 61189-3, Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 3: Test methods for interconnection structures (printed boards) IEC TS 62878-2-4:2015, Device embedded substrate – Part 2-4 – Guidelines – Test element groups (TEG) 3 Terms, definitions and abbreviations 3.1 Terms and definitions For the purposes of this document, the terms and definitions given in IEC 60194 apply. 3.2 Abbreviations AABUS as agreed between user and supplier AOI automated optical inspection LSI large scale integration SIST EN 62878-1-1:2015

– 8 – IEC 62878-1-1:2015 © IEC 2015 4 Test methods 4.1 General This clause is given for guidance only. The test shall be carried out at the standard air conditions (or simply stated as standard environment): Temperature Relative humidity Atmospheric pressure 15°C to 35°C 25 % to 75 % 86 kPa to 106 kPa 4.2 Visual inspection and micro-sectioning 4.2.1 General Visual inspection and micro-sectioning of multi-layer printed wiring boards are specified in 4.2.2 and 4.2.3. 4.2.2 Visual inspection Visual inspection consists of checking the appearance, finish, and pattern of specimens using the naked eye or a magnifying glass in reference to its individual specification. The test result shall be as agreed between user and supplier (hereafter referred as AABUS). 4.2.3 Micro-sectioning Micro-sectioning is to check the state, appearance, and dimensions according to individual specifications of the plated through hole, the via in the build-up layer, the conductor, the interlayer distance, the conductor distance, and the connections to the embedded device. The specimen is mounted in epoxy or polyester resin and the specimen is cross-sectioned and polished for observation. The evaluation of the results shall be AABUS. The equipment, material, specimen and test are specified in a) to d). a) Equipment An industrial microscope capable of measuring plated film thicknesses with an accuracy of 0,001 mm. b) Material Materials used in this test are releasing agent, moulding resin, polishing cloth or paper (#180, #400, #1 000, etc.) with the option to use polishing materials (alumina or chromium oxide). c) Specimen A specimen is cut from the product to an appropriate size sufficient for observation and mounted in moulding resin. The cut surface is then polished with polishing cloth/paper starting from coarse to fine using a rotating felt surface and the above mentioned polishing material. The polishing face shall be within an angle of 85° to 95° to the layer to be observed. The diameter of the plated film of the through hole and of the vias in the build-up layer observed by micro-sectioning shall be no less than 90 % of the previously observed hole diameter. Etch the specimen if the boundary of the plating needs to be clarified after polishing. d) Test The test consists of observing the items specified in the individual specifications by means of a microscope of specified magnification. Figure 1 illustrates the test items for the through hole to check the micro-sectioned faces, and Figure 2 for the build-up structure and embedded devices. Table 1 gives the characteristics and observation items of the test. SIST EN 62878-1-1:2015

IEC 62878-1-1:2015 © IEC 2015 – 9 –
Key A Conductor width F Conductor plated film thickness B Conductor gap G Thickness of copper foil C Insulation layer thickness H Conductor thickness D Hole diameter I Boundary of plated film E Plated film thickness of through hole J Internal circuit Figure 1 – Measuring items of the micro-sectioned through hole structure
Key A Distance between conductor and embedded device B Device embedding layer Figure 2 – Measuring items of the micro-sectioned device
embedded board with build-up structure Table 1 – Test items, characteristics and observations
of micro-sectioned specimens No Test item Characteristics and observation 1 Conductor width
(inner layer , outer layer) – Upper conductor width – Lower conductor width – Etch factor 2 Conductor gap (inner layer, outer layer) – Minimum conductor gap 3 Insulation layer thickness/conductor gap – Minimum insulation layer/minimum conductor gap – Delamination – Measling – Crazing 4 Hole diameter and land width – Hole diameter – Land width IEC ABIEC ABCCDEFGHIIJSIST EN 62878-1-1:2015

– 10 – IEC 62878-1-1:2015 © IEC 2015 No Test item Characteristics and observation 5 Plated film thickness of the through hole – Plated film thickness of the through hole – Plated film thickness of the via in the build-up layer (conformal via) – Corner crack – Barrel crack – Foil crack 6 Film thickness of the plated conductor – Film thickness of the plated conductor 7 Copper foil thickness – Copper foil thickness 8 Conductor thickness – Total conductor thickness(copper foil and film thickness of the plated conductor) 9 Distance between conductor and embedded device – Distance between conductor and embedded device 10 Thickness of the device embedding layer – Thickness of the device embedding layer – Delamination – Measling – Crazing
4.2.4 Lack of conductor and residue of conductor In order to measure lack and residue of conductor, a) and b) apply: a) Equipment An industrial microscope with an accuracy of at least 0,001 mm. b) Measurement Measure the lack of conductor and residue of the conductor in the vertical and horizontal directions at the insulating area. 4.2.5 Land dimension and land width (annular ring) 4.2.5.1 Component insertion land and through hole land In order to measure component insertion land and through hole land, a) and b) apply: a) Equipment An industrial microscope with an accuracy of at least 0,001 mm. b) Measurement 1) Measure the land dimension d1 to d4 as illustrated in Figure 3. 2) Measure the left outer land width w1 to w4 as illustrated in Figure 3 by micro-sectioning of the distance between the hall edge and not including the plated film and land edge to better than 0,001 mm. SIST EN 62878-1-1:2015

IEC 62878-1-1:2015 © IEC 2015 – 11 –
a) Non-plated hole b) Plated hole Key A Non-plated hole B Plated hole C Via in the build-up layer with the form of conformal via d1 to d4 Maximum dimension of land w1 to w4 Width of lands in outer layer w5, w6 Width of lands in inter layer Figure 3 – Measurement of land dimension 4.2.5.2 Via (including interstitial via hole and via in the build-up layer) In order to measure the via, a) and b) apply: a) Equipment Industrial microscope with an accuracy of at least 0,001 mm. b) Measurement 1) Measure the land dimension d1 to d4 as illustrated in Figure 4. 2) It is not necessary to measure the land dimension w1 to w4 as shown in Figure 4 unless there is a problem with the electrical connection. The measurement can be carried out upon agreement between user and supplier and by means of micro-sectioning to better than 0,001 mm of the maximum dimension.
IEC Cd1d3d2d4w1w2w3w4w5w6AAAABBSIST EN 62878-1-1:2015

– 12 – IEC 62878-1-1:2015 © IEC 2015
a) Conformal via b) Filled via Key A Insulation layer d1 to d4 Maximum land dimension w1 to w4 Land edge width Figure 4 – Build-up land measurement 4.2.5.3 Coplanarity
4.2.5.3.1 Bend In order to measure the bend, a) and b) apply. a) Equipment A gap gauge or a height gauge with an accuracy of 0,1 mm or better shall be used. b) Measurement Place a device embedded board on a precision plate with the protruded side up and then measure the maximum gap between the base and specimen to an accuracy of 0,1 mm to find the bend. 4.2.5.3.2 Twist In order to measure the twist, a) and b) apply a) Equipment A gap gauge or a height gauge with an accuracy of 0,1 mm or better shall be used. b) Measurement Place a device embedded board on a precision plate with the protruded side up with three corners of the specimen touched to the plate and measure the distance between the plate and the untouched corner of the specimen to an accuracy of 0,1 mm. 4.2.5.3.3 Test method Table 2 gives the test method for coplanarity around the land pattern. Table 2 – Test method for coplanarity around the land pattern Item Criteria Test method Effect on embedded device AABUS Use TEG in-place of an embedded device A test for terminal connections of embedded devices is under consideration. IEC Ad1w1d2w2d3w3d4w4SIST EN 62878-1-1:2015

IEC 62878-1-1:2015 © IEC 2015 – 13 – 4.3 Electrical tests 4.3.1 Conductor resistance In order to check conductor resistance, a) to d) apply: a) Equipment Voltage drop method (four-terminal method) or equivalent. The measuring signal (voltage or current) shall be DC or AC. b) Specimen The specimen is the specified section of the test pattern or the complex test pattern of a device embedded board illustrated in IEC TS 62878-2-4:2015, Figures 1 to 27. c) Pre-treatment Pre-treatment shall be either 1) or 2), depending on the individual specifications. 1) Leave a specimen in the standard environment for 24 h ± 4 h. 2) Leave a specimen in a bath of 85 °C ± 2 °C for 4 h and then in the standard environment for 24 h ± 4 h. d) Test The measurement shall be carried out as illustrated in Figure 5 to an accuracy of ± 5 %. Ensure that effects of probe contacting and heating due to measuring current are avoided. The specimen includes the connection between an embedded device and terminals, a conductor including through hole and a via in the build-up layer. SIST EN 62878-1-1:2015

– 14 – IEC 62878-1-1:2015 © IEC 2015
a) Conductor resistance measurement b) Through hole resistance measurement
c) Resistance measurement of via in the
build-up layer d) Resistance measurement of via in the inner conductor layer
e) Resistance measurement for connection
of embedded device
Key A Current terminal C TEG B Voltage terminal D Connection actually used Figure 5 – Conductor resistance measurement 4.3.2 Through hole and build-up via In order to check through hole and build-up via, a) to d) apply: a) Equipment
The equipment shall be in accordance with 4.3.1 a). b) Specimen IEC ABIEC AABBIEC AABBIEC ABIEC ABCDSIST EN 62878-1-1:2015

IEC 62878-1-1:2015 © IEC 2015 – 15 – Specimen is the specified section of the test pattern or of the complex test pattern of a device embedded board illustrated in Figures 1 to 27 of IEC TS 62878-2-4:2015. c) Pre-treatment Pre-treatment shall be in accordance with 4.3.1 c). d) Test Measurement shall be made as illustrated in Figure 5 to an accuracy of ± 5 % with an effort to avoid effects of probe contacting and heating due to measuring current. Table 3 gives the characteristics and test method for conductor resistance. Table 3 – Characteristics and test methods for conductor resistance Item Characteristics Test method Connection to embedded device/Pad connection/Via connection AABUS As indicated in 4.3.2, plated through hole and via in the build-up layer. Use TEG for embedded device.
4.3.3 Withstanding current of embedded device connection In order to measure withstanding current of embedded device connection, a) to d) apply: a) Equipment A DC or AC power supply capable of giving the test current specified in Table 4 and an ammeter. The equipment shall be a DC or AC power supply capable of giving the test current specified in 4.3.2 a) and an ammeter. b) Specimen The specimen shall be the terminals of the TEG and the specified part of the complex test pattern (Figures 1 to 28 in IEC TS 62878-2-4:2015). A zero ohm jumper resistor is recommended for the TEG for an embedded device. c) Pre-treatment Pre-treatment shall be in accordance with 4.3.1 c). d) Test Check any abnormality after supplying a current contact terminal of TEG and pad on the board with a specified current given its individual specification for 30 s. Test current for a given hole diameter is given in Table 5. Table 4 shows the withstanding current characteristics and test methods. SIST EN 62878-1-1:2015

– 16 – IEC 62878-1-1:2015 © IEC 2015 Table 4 – Withstanding current and test methods Item Characteristics Test method Conductor Withstanding current characteristics shall be AABUS. The relationship between current and conductor width, conductor thickness and temperature rise is shown in Figure 6. As per 4.3.2 withstanding current for through hole and via in the build-up layers. As per 4.3.3 withstanding current of conductor. Shape and dimension of specimen shall be AABUS. Through hole and via in the build-up layer
As per 4.3.3 withstanding current of conductor. Shape and dimension of specimen shall be AABUS. Embedded device
– Pad connection – Via connection
As per 4.3.3 withstanding current of embedding device connection. Use the TEG for embedded device. Internal resistance of the TEG shall be less than 50 mΩ. The test current shall not exceed the rated current shown below. Rated current is for steady state loading of 30 s. The maximum overload current is defined for 2 s.
Type Rated current
70 °C, A Maximum overload current, A
0603 0,5 1,0
1005 1,0 2,0
1608 1,0 2,0
IEC 62878-1-1:2015 © IEC 2015 – 17 –
a) Conductor thickness is 18 µm b) Conductor thickness is 35 µm
c) Conductor thickness is 70 µm d) Conductor thickness is 105 µm X current (A) Y conductor width (mm) Figure 6 – Relationship between current, conductor width and thickness and temperature rise 4.3.4 Withstanding voltage in embedded boards 4.3.4.1 General Withstanding voltages of conductor, plated through hole and via in the build-up layers, inner connection and connection to the embedded device shall be measured according to each individual specification. This test shall be made only when the test of withstanding voltage is required. 4.3.4.2 Withstanding voltage of inner layers in embedded boards In order to measure withstanding voltage of inner layer in embedded boards, a) to d) apply: a) Equipment The equipment shall be in accordance with 4.3.2.a). b) Specimen IEC 0,1 0,15 0,2 0,3 0,4 0,5 0,6 0,8 1,0 1,2 1,5 2,5 0,2 0,3 0,4 0,6 0,8 1 1,5 2 3 4 5 6 8 10 ∆ t ==10 °C ∆ t ==20 °C ∆ t ==30 °C ∆ t ==40 °C ∆ t ==50 °C ∆ t ==75 °C ∆ t ==100 °C IEC 0,1 0,15 0,2 0,3 0,4 0,5 0,6 0,8 1,0 1,2 1,5 2,5 0,3 2 3 4 6 8 10 ∆ t ==10 °C ∆ t ==20 °C ∆ t ==30 °C ∆ t ==40 °C ∆ t ==50 °C ∆ t ==75 °C ∆ t ==100 °C 0,5 0,7 0,9 1,2 1,5 15 IEC 0,1 0,15 0,2 0,3 0,4 0,5 0,6 0,8 1,0 1,2 1,5 2,5 0,4 ∆ t ==10 °C ∆ t ==20 °C ∆ t ==30 °C ∆ t ==40 °C ∆ t ==50 °C ∆ t ==75 °C ∆ t ==100 °C 0,8 1,2 2 3 4 6 8 10 15 20 IEC 0,1 0,15 0,2 0,3 0,4 0,5 0,6 0,8 1,0 1,2 1,5 2,5 0,6 ∆ t ==10 °C ∆ t ==20 °C ∆ t ==30 °C ∆ t ==40 °C ∆ t ==50 °C ∆ t ==75 °C ∆ t ==100 °C 1 1,5 2 3 4 5 6 8 10 15 20 30 SIST EN 62878-1-1:2015

– 18 – IEC 62878-1-1:2015 © IEC 2015 The specimen shall be manufactured to fit the connection terminal of the TEG in the device embedding board or the pad of complex test pattern (see Figures 1 to 27 in IEC TS 62878-2-4:2015). A specimen suffering from mechanical damage, flashover, sparkover or breakdown shall not be used in further tests. c) Pre-treatment Pre-treatment shall be as described in 4.3.1 c). d) Test The test shall be as described in 4.3.1 d). 4.3.4.3 Withstanding voltage of embedded device connection Items a) to d) apply: a) Equipment The equipment shall be in accordance with 4.3.1 a). b) Specimen The specimen shall be a specified part of the TEG in a device embedding board or complex test pattern (Figures 1 to 27 of IEC TS 62878-2-4:2015). It is recommended to use a zero ohm jumper resistor for the TEG. A specimen suffering from mechanical damage, flush over, spark over or breakdown shall not be used in further tests. c) Pre-treatment Pre-treatment shall be as described in 4.3.1 c). d) Test The test shall be as described in 4.3.1 d). Table 5 shows the test methods for withstanding voltage. Table 5 – Withstanding voltage and test methods Item Characteristics Test Interlayer There should be no abnormality such as mechanical damage, flush-over or insulation damage. As stated in 4.3.4.2, interlayer surge voltage. The test voltage is given below.
Interlayer distance x mm Test voltage V
0,02 Ì x < 0,05 100
0,05 Ì x < 0,08 250
0,08 Ì x < 0,20 500
0,20 Ì x 1 000
Connection to embedded device There should be no abnormality such as mechanical damage, flush-over or insulation damage. As stated in 4.3.4.3, withstanding voltage for embedded device. Use the TEG for embedded device. The internal resistance of the TEG shall be less than 50 mΩ. Test below the isolation voltage of the TEG.
Type Isolation voltage (effective value of
Vdc or Vac)
0603 30
1005 100
1608 100
IEC 62878-1-1:2015 © IEC 2015 – 19 –
4.3.5 Insulation resistance 4.3.5.1 General The insulation resistance shall be measured between the terminals of the conductor the embedded device based on individual specifications. 4.3.5.2 Insulation resistance of the inner layer In order to measure insulation resistance of the inner layer, a) to d) apply: a) Equipment An insulation resistance tester capable of measuring values greater than 1010 Ω. b) Specimen The specimen shall be a specified part of a device embedding board, test pattern or complex test pattern (Figures 1 to 27 of IEC TS 62878-2-4:2015) including connection to embedded device. c) Pre-treatment Pre-treatment shall be in accordance with 4.3.4.2 c). d) Test Apply a DC voltage of 10 V ± 1 V, 50 V ± 5 V, 100 V ± 10 V or 500 V ± 50 V depending on the individual specification for 1 min and then measure the insulation resistance while applying the voltage. 4.3.5.3 Insulation resistance between inner layers In order to measure insulation resistance between inner layers, a) to d) apply: a) Equipment Equipment shall be in accordance with 4.3.1 a). b) Specimen The specimen shall be a specified part of a device embedding board, test pattern or a complex test pattern (Figures 1 to 27 of IEC TS 62878-2-4:2015) including connection to embedded device. c) Pre-treatment Pre-treatment shall be in accordance with 4.3.1 c). d) Test The test shall be in accordance with 4.3.1 d). 4.3.5.4 Insulation resistance between embedded terminals In order to measure insulation resistance between embedded terminals, a) to d) apply: a) Equipment The equipment shall be in accordance with 4.3.4.3 a). b) Specimen The specimen shall be a specified part of a device embedding board, test pattern or a complex test pattern (Figures 1 to 27 in IEC TS 62878-2-4:2015) including connection to embedded device. It is recommended to use a zero ohm jumper resistor for TEG. c) Pre-treatment Pre-treatment shall be in accordance with 4.3.1 c). d) Test SIST EN 62878-1-1:2015

– 20 – IEC 62878-1-1:2015 © IEC 2015 The test shall be in accordance with 4.3.1 d). Table 6 shows evaluation items of insulation resistance, characteristics and test methods. Table 6 – Criteria and test methods for insulation resistance Item Criteria Test Interlayer Normal Resistance shall be larger than: As per 4.3.5.3 interlayer insulation resistance. Test voltage shall be:
Minimum insulator thickness x mm Resistance
Ω
Minimum insulation layer thickness x mm Test voltage
V
0,02 Ì x < 0,05 5 × 109
0,03 Ì x < 0,05 10
0,05 Ì x < 0,13 1 × 1010
0,05 Ì x < 0,08 50
0,13 Ì x 5 × 1010
0,08 Ì x < 0,20 100
0,20 Ì x 500
Between embedded device terminals Normal Resistance
shall be larger than: As stated in 4.3.5.4 insulation resistance between terminals of embedded device. Use TEG. Internal resistance of the TEG shall be less than 50 mΩ. When using a resistor, the guaranteed insulation resistance shall be 109 Ω.
Minimum distance between insulation terminal or pads x mm Resistance
Ω
0,02 Ì x < 0,05 5 × 108
0,05 Ì x < 0,13 1 × 109
0,13 Ì x
5 × 109
4.3.6 Conduction and insulation of circuit This test has been developed to verify the insulation of points not electrically connected to
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