IEC 60749-27:2006

IEC 60749-27 ®
Edition 2.1 2012-09
CONSOLIDATED VERSION
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Semiconductor devices – Mechanical and climatic test methods –
Part 27: Electrostatic discharge (ESD) sensitivity testing – Machine model (MM)
Dispositifs à semiconducteurs – Méthodes d'essais mécaniques et climatiques –
Partie 27: Essai de sensibilité aux décharges électrostatiques (DES) – Modèle de
machine (MM)
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IEC 60749-27 ®
Edition 2.1 2012-09
CONSOLIDATED VERSION
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Semiconductor devices – Mechanical and climatic test methods –

Part 27: Electrostatic discharge (ESD) sensitivity testing – Machine model (MM)

Dispositifs à semiconducteurs – Méthodes d'essais mécaniques et climatiques –

Partie 27: Essai de sensibilité aux décharges électrostatiques (DES) – Modèle

de machine (MM)
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.080.01 ISBN 978-2-8322-0407-8

– 2 – 60749-27  IEC:2006+A1:2012
CONTENTS
FOREWORD . 3

1 Scope . 5
2 Normative references . 5
3 Terms and definitions . 5
4 Equipment . 6
4.1 MM ESD waveform generator . 6
4.2 Waveform verification equipment . 6
5 MM current waveform requirements . 7
5.1 General . 7
5.2 Waveform qualification and verification . 10
5.3 Extra consideration for waveform specifications . 9
6 Device specific evaluation considerations . 10
6.1 Sample size and test conditions . 10
6.2 Worst-case pin or standard qualification board . 10
7 Classification procedure . 11
7.1 Device requirements . 11
7.2 Device selection . 11
7.3 Device characterization . 11
7.4 Device stress levels . 11
7.5 Pin combinations . 12
7.6 Order of test . 12
8 Failure criteria . 12
9 Classification criteria . 12
10 Summary . 13

Figure 1 – MM ESD waveform generator equivalent . 7
Figure 2 – Typical current waveform through a shorting wire . 8
Figure 3 – Typical current waveform through a 500 Ω resistor . 9

Table 1 – Waveform specification . 8
Table 2 – Pin combinations for integrated circuits . 12

60749-27  IEC:2006+A1:2012 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
___________
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –
Part 27: Electrostatic discharge (ESD) sensitivity testing –
Machine model (MM)
FOREWORD
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This consolidated version of the official IEC Standard and its amendment has been prepared
for user convenience.
IEC 60749-27 edition 2.1 contains the second edition (2006) [documents 47/1861/FDIS and
47/1873/RVD] and its amendment 1 (2012) [documents 47/2135/FDIS and 47/2144/RVD].
A vertical line in the margin shows where the base publication has been modified by
amendment 1. Additions and deletions are displayed in red, with deletions being struck
through.
– 4 – 60749-27  IEC:2006+A1:2012
International Standard IEC 60749-27 has been prepared by IEC technical committee 47:
Semiconductor devices.
This second edition cancels and replaces the first edition, published in 2003, and has been
revised in collaboration with technical committee 101. Whilst it does not contain any major
technical changes, reference is now made, where necessary, to IEC 61340-3-2.
A list of all parts of IEC 60749 series, under the general title Semiconductor devices –
Mechanical and climatic test methods can be found on the IEC website.
The committee has decided that the contents of the base publication and its amendments will
remain unchanged until the stability date indicated on the IEC web site under
"http://webstore.iec.ch" in the data related to the specific publication. At this date, the
publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The “colour inside” logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct understanding
of its contents. Users should therefore print this publication using a colour printer.

60749-27  IEC:2006+A1:2012 – 5 –
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –

Part 27: Electrostatic discharge (ESD) sensitivity testing –
Machine model (MM)
1 Scope
This part of IEC 60749 establishes a standard procedure for testing and classifying
semiconductor devices according to their susceptibility to damage or degradation by exposure
to a defined machine model (MM) electrostatic discharge (ESD). It may be used as an
alternative test method to the human body model ESD test method. The objective is to
provide reliable, repeatable ESD test results so that accurate classifications can be performed.
This test method is applicable to all semiconductor devices and is classified as destructive.
ESD testing of semiconductor devices is selected from this test method, the human body
model (HBM – see IEC 60749-26) or other test methods in the IEC 60749 series. The MM and
HBM test methods produce similar but not identical results. Unless otherwise specified, the
HBM test method is the one selected.
NOTE 1 This test method does not truly simulate discharge from real machines or metallic tools because the test
method uses high parasitic inductance of the test circuit, whereas real machines and metallic tools, whose
discharge rise time is approximately 100 ps, have no inductance.
NOTE 2 Certain clauses in this test method are in accordance with IEC 61340-3-2.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 61340-3-2, Electrostatics – Part 3-2: Methods for simulation of electrostatic effects –
Machine model (MM – Component testing ) electrostatic discharge test waveforms
IEC 60749-26: Semiconductor devices – Mechanical and climatic test methods – Part 26:
Electrostatic discharge (ESD) sensitivity testing – Human body model (HBM)
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
3.1
device under test
DUT
semiconductor product subjected to MM ESD test
3.2
DUT failure
condition in which a DUT does not meet one or more specified parameters as a result of ESD
test
– 6 – 60749-27  IEC:2006+A1:2012
3.3
ESD withstand voltage
maximum applied ESD voltage level that does not cause failure parameter limits to be
exceeded provided that all DUTs stressed at lower levels have also passed
NOTE Clause 3 of this test method is in accordance with IEC 61340-3-2 except for the specific reference to
devices.
3.4
ringing
noise component caused by a large inductance in the discharge circuit
4 Equipment
4.1 MM ESD waveform generator
This equipment produces an electrostatic discharge current pulse simulating a MM ESD event
for application to the DUT. The equivalent waveform generator circuit and tester evaluation
loads are illustrated in Figure 1.
4.2 Waveform verification equipment
4.2.1 General
Equipment capable of verifying the MM current waveform is defined in this standard. This
equipment includes but is not limited to a waveform recording system, a high voltage resistor
and a current transducer.
4.2.2 Waveform recording system
The waveform recording system shall have a minimum single shot bandwidth of 350 MHz.
4.2.3 Evaluation loads
Two evaluation loads are necessary to verify the functionality of the waveform generator:
a) load 1: a shorting wire;
b) load 2: a 500 Ω with a tolerance of ±1 % low inductance resistor appropriate rated for the
voltages that will be used for waveform qualification.
The lead length of the evaluation loads (shorting wire or resistor) shall be as short as possible
consistent with connecting the evaluation load to the appropriate reference terminals (A and B
in Figure 1) while passing through the current transducer.
4.2.4 Current transducer
The current transducer shall have a minimum bandwidth of 350 MHz.

60749-27  IEC:2006+A1:2012 – 7 –

IEC  678/02
Key
1 MM ESD waveform generator (nominally 200 pF)
2 Terminal A
3 Switch
4 Terminal B
5 DUT
6 Evaluation load
7 Shorting wire
8 Resistance R = 500 Ω
9 Current transducer
Figure 1 – MM ESD waveform generator equivalent
Requirements for Figure 1:
1. The evaluation loads (7 and 8) are specified in 4.2.3.
2. The current transducer (9) is specified in 4.2.4.
3. The reversal of terminals A (2) and B (4) to achieve dual polarity is not permitted.
4. The switch (3) is closed 10 ms to 100 ms after the pulse delivery period of each single MM
pulse to ensure that the DUT and any test fixture are not left in a charged state.
NOTE 1 The performance of the waveform generator is strongly influenced by parasitic capacitance and
inductance.
NOTE 2 Precautions must be taken in the design of the waveform generator to avoid recharge transients and
double pulses.
NOTE 3 A resistance in series with the switch would ensure a slow discharge of the DUT.
NOTE 4 Clause 4 of this test method is in accordance with IEC 61340-3-2 except for the specific reference to
devices.
5 MM current waveform requirements
5.1 General
Prior to DUT testing, MM ESD waveform generator qualification shall ensure waveform
integrity of the discharge current through both a shorting wire and a resistive load. The
shorting wire waveform requirements are specified in Figure 2 for all positive and negative
voltages defined in Table 1, while the resistive load waveform requirements for ±400 V are
shown in Figure 3 and Table 1.

– 8 – 60749-27  IEC:2006+A1:2012
Table 1 – Waveform specification
Equivalent I peak current I peak current I current through a
p1 PR 100
Level voltage through a shorting wire
through a 500 Ω resistor 500 Ω resistor at 100 ns
V A (±15 %)
A A (±15 %)
1 100 1,7 – –
2 200 3,5 – –
3 400 7,0 0,29
4 800 14,0 – –
Equivalent I peak current through I peak current I current through a
p1 PR 100
voltage a shorting wire
Level through a 500 Ω resistor 500 Ω resistor at 100 ns
a
V
A (± 15 %) A
A (± 15 %)
1 100 1,7 (1,5) – –
2 200 3,5 (3,0) – –
3 400 7,0 (6,0) 4 800 14,0 (12,0) – –
a
Values in parentheses are the peak current value without ringing.

I
p1
t
pm
t
t
t
t
0 2
I
p2
20 ns per division
IEC  682/02
Figure 2 – Typical current waveform through a shorting wire

60749-27  IEC:2006+A1:2012 – 9 –
Requirements for Figure 2:
The current pulse shall meet the following requirements:
I is the maximum peak current is specified in Table 1;
p1
I is the second peak current shall be between 67 % and 90 % of the absolute value
p2
obtained for I for each level;
p1
t is the period of the major pulse shall be between 63 ns and 91 ns. The measurement
pm
shall be made between the first zero crossing point, t , and the third zero crossing point, t .
1 3
The inductance (L) which is related to t shall be controlled to meet the above specified
pm
pulse period. The recommended value is 750 nH.

I
PR
I
20 ns per division
IEC  683/02
Figure 3 – Typical current waveform through a 500 Ω resistor
Requirements for Figure 3:
The current pulse through a 500 Ω resistor shall meet the following characteristics:
I is the maximum peak current shall be within the range specified in Table 1;
PR
I is the current at 100 ns is defined in Table 1.
5.3 Extra consideration for waveform specifications
The peak current I without ringing shall be verified against the values in Table 1.
p1
– 10 – 60749-27  IEC:2006+A1:2012
5.2 Waveform qualification and verification
Equipment qualification shall be performed during initial acceptance testing. Re-qualification
is required whenever equipment repairs are made that may affect the waveform. Additionally,
the waveforms shall be verified periodically. If a test fixture or circuit board is used to perform
DUT testing, the test fixture (board) shall also be used during equipment qualification tests. In
case the waveform no longer meets the waveform parameters described in Table 1 and
Figures 2 and 3, all ESD testing performed after the previous satisfactory waveform check
shall be considered invalid.
NOTE Clause 5 of this test method is in accordance with IEC 61340-3-2 except for the specific reference to
devices.
6 Device specific evaluation considerations
6.1 Sample size and test conditions
In the semiconductor industry, the typical ESD evaluation uses a sample size of three devices,
each of which is tested using one positive and one negative pulse with a pulse interval of
300 ms.
6.2 Worst-case pin or standard qualification board
6.2.1 General
Equipment qualification shall be made by discharge current measurement with a worst-case
pin combination of DUT board, as specified in 6.2.2. This method shall be used if the
equipment is constructed using a single discharge generator that can be connected to all pins
of the socket on the DUT board by switching of relays.
Multiple discharge generators shall be qualified using the standard qualification board
specified in 6.2.3. This method shall be used if the equipment is constructed to use a large
number of pairs of pins of the DUT board and each test circuit is connected to only a single
pin of the DUT board.
6.2.2 Worst-case pin
The worst-case pin combination for each socket and DUT board shall be identified and
documented. It is recommended that the manufacturers supply the worst-case pin data with
each DUT board. The pin combination with the waveform closest to the limits (see Table 1)
shall be designated for waveform verification.
The worst-case pin combination shall be identified by the following procedure:
a) For each test socket, identify the socket pin with the shortest wiring path from the pulse
generating circuit to the test socket. Connect this pin to terminal B (where it will remain
the reference pin throughout the worst case pin search) and connect one of the remaining
pins to terminal A. Attach a shorting wire between these pins with the current probe
around the shorting wire, as close to terminal B as practicable.
b) Apply a positive 400 V pulse and a negative 400 V pulse and verify that the waveform
meets the requirements defined in Table 1 for both positive and negative pulses.
c) Repeat steps a) and b) until all socket pins have been evaluated.
d) Determine the worst-case pin pair (within the limits and closest to the minimum or
maximum parameter values as specified in Table 1) to be used for future waveform
verification.
60749-27  IEC:2006+A1:2012 – 11 –
e) For initial board check-out, connect a 500 Ω resistor between the worst-case pins
previously identified with the shorting wire in step d). Apply a positive and negative 400 V
pulse and verify that the waveform meets the requirements defined in Table 1.
NOTE If the test socket/test board has already been characterized for worst-case pin on HBM, then that pin
combination is acceptable for use with MM waveform verification. As an alternative to the worst-case pin search,
the reference pin pair may be identified for each test socket of each test fixture. The reference pin combination
should be identified by determining the socket pin with the shortest wiring path from the pulse generating circuit to
the test socket. Connect this pin to terminal B and then connect the socket pin with the longest wiring path from the
pulse generating circuit to the test socket to terminal A (normally provided by the manufacturer). Attach a shorting
wire between these pins with the current probe around the shorting wire. Follow the procedure in step b). For the
initial board check-out connect a 500 Ω resistor between the reference pins. Apply a positive and negative 400 V
pulse and verify that the waveform meets the parameters in Table 1.
6.2.3 Standard qualification board
The standard qualification board shall satisfy the following requirements:
a) the size for the standard qualification board shall be the same size as is used for the DUT
board;
b) the specific length of internal wires of the standard qualification board, between equipment
and the terminals used to connect with evaluation loads, shall be specified in the
applicable specification;
c) the total length of each circuit pair in all DUT boards shall be shorter than/equal to the
length of the internal wire pairs in the standard qualification board and the evaluation load
specified in 4.2.3.
7 Classification procedure
7.1 Device requirements
The devices used for classification testing shall have completed all normal manufacturing
operations.
7.2 Device selection
Prior to ESD testing, d.c. parametric and functional testing at room temperature and, if
applicable, high temperature shall be performed on all devices submitted for ESD testing. The
test devices shall meet device data sheet requirements for these parameters.
7.3 Device characterization
A sample of devices (e.g. three) for each voltage level shall be characterized for the device
ESD failure threshold using the voltage steps shown in Table 1. Finer voltage steps may
optionally be used to obtain a more accurate measure of the failure threshold. ESD testing
should begin at the lowest step in Table 1. The ESD test shall be performed at room
temperature.
7.4 Device stress levels
Each sample of devices (e.g. three) shall be stressed at one voltage level using one positive
and one negative pulse with a minimum of 0,3 s between pulses per pin for all pin
combinations specified in Table 2. It is permitted to use a separate sample of devices (e.g.
three) for each pin combination specified in Table 2. It is permitted to use the same sample
(e.g. three) at the next highest voltage stress level if all devices pass the failure criteria
specified in Clause 8 after ESD exposure to a specified voltage level.

– 12 – 60749-27  IEC:2006+A1:2012
7.5 Pin combinations
The pin combinations to be used are given in Table 2. The actual number of pin combinations
depends on the number of power pin groups. Like-named power pins (V , V , V , V ,
CC1 CC2 SS1 SS2
GND, etc.) that are directly connected by metal (inside the package) may be tied together and
treated as one pin for terminal B connection. Otherwise, each power pin shall be treated as a
separate power pin. Programming pins that do not draw current should be considered as I/O
pins (example: V pins on memory devices). Active discrete devices (FETs, transistors, etc.)
PP
shall be tested using all possible pin-pair combinations (one pin connected to terminal A,
another pin connected to terminal B) regardless of pin name or function. All pins configured
as “no connect” pins shall be verified as “no-connect” and left open (floating) at all times.
Pins labelled “no-connect”, that in fact are connected, shall be tested as non-supply pins.
Table 2 – Pin combinations for integrated circuits
Connect individually to Connect to terminal B Floating pins
Pin combination
terminal A (ground) (unconnected)
a
1 All pins one at a time, First power pin(s) All pins except PUT
except the pin(s) connected and first power pin(s)
to terminal B
2 All pins one at a time, Second power pin(s) All pins except PUT and
except the pin(s) connected second power pin(s)
to terminal B
th
3 All pins one at a time, N power pin(s) All pins except PUT and
th
except the pin(s) connected N power pin(s)
to terminal B
4 Each non-supply pin, one at All other non-supply pins All power pins
a time collectively except PUT
a
PUT: Pin under test.
7.6 Order of test
If a different sample group is ESD tested at each stress level, it is permitted to perform the d.c.
parametric and functional ATE (automatic test equipment) testing after all sample groups
have been ESD tested.
8 Failure criteria
A device will be defined as a failure if, after exposure to ESD pulses, it no longer meets the
device data sheet requirements using parametric and functional testing. If testing is required
at a number of different temperatures, testing shall be performed at the lowest temperature
first.
9 Classification criteria
All samples used shall meet the test requirements of Clause 7 up to a particular voltage level
in order for the device to be classified as meeting a particular withstand classification.
CLASS A: Any device that fails after exposure to an ESD pulse of 200 V or less.
CLASS B: Any device that passes after exposure to an ESD pulse of 200 V, but fails after
exposure to an ESD pulse of 400 V.
CLASS C: Any device that passes after exposure to an ESD pulse of 400 V.

60749-27  IEC:2006+A1:2012 – 13 –
10 Summary
The following details shall be specified in the applicable specification:
a) test method to be selected from human body model or machine model (see Clause 1);
b) frequency of equipment qualification (see 5.2);
c) worst case pin pair and DUT board used for equipment qualification if it is used (see 6.2);
d
...