IEC 62148-19:2019
(Main)Fibre optic active components and devices - Package and interface standards - Part 19: Photonic chip scale package
Fibre optic active components and devices - Package and interface standards - Part 19: Photonic chip scale package
IEC 62148-19: 2019 covers the photonic chip scale package. The purpose of this document is to specify adequately the physical requirements of optical transmitters and receivers that will enable mechanical interchangeability of transmitters and receivers.
Keywords: physical interface for photonic chip scale packages
Composants et dispositifs actifs fibroniques - Normes de boîtier et d’interface - Partie 19 : Boîtier à puce photonique
L'IEC 62148-19: 2019 couvre les boîtiers à puces photoniques. L'objectif du présent document est de spécifier les exigences physiques des modules d'émission et de réception optique qui permettent l'interchangeabilité mécanique des émetteurs et transmetteurs.
Mots-clés: interface physique des boîtiers à puces photoniques
General Information
Standards Content (Sample)
IEC 62148-19 ®
Edition 1.0 2019-05
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Fibre optic active components and devices – Package and interface standards –
Part 19: Photonic chip scale package
Composants et dispositifs actifs fibroniques – Normes de boîtier et d'interface –
Partie 19: Boîtier à puce photonique
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IEC 62148-19 ®
Edition 1.0 2019-05
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Fibre optic active components and devices – Package and interface standards –
Part 19: Photonic chip scale package
Composants et dispositifs actifs fibroniques – Normes de boîtier et d'interface –
Partie 19: Boîtier à puce photonique
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 33.180.20 ISBN 978-2-8322-6869-8
– 2 – IEC 62148-19:2019 © IEC 2019
CONTENTS
FOREWORD . 4
INTRODUCTION . 6
1 Scope . 7
2 Normative references . 7
3 Terms, definitions and abbreviated terms . 7
3.1 Terms and definitions . 7
3.2 Abbreviated terms . 7
4 Classification . 8
5 Specification of photonic chip scale package . 8
5.1 General . 8
5.2 General block diagram (silicon photonics) . 8
5.3 Electrical interface . 9
5.3.1 General . 9
5.3.2 Numbering of electrical terminals . 9
5.4 Optical interface . 9
5.4.1 General . 9
5.4.2 Free space optical beam condition . 9
5.5 Outline and footprint . 9
5.5.1 General . 9
5.5.2 Drawing of footprint . 10
Annex A (normative) Specific configurations . 11
A.1 General . 11
A.2 4ch transceiver . 11
A.2.1 Block diagram . 11
A.2.2 Electrical terminal assignments . 12
A.2.3 Optical terminal assignments . 15
A.2.4 Outline drawing . 16
A.3 8ch transceiver . 18
A.3.1 Block diagram . 18
A.3.2 Electrical terminal assignments . 19
A.3.3 Optical terminal assignments . 23
A.3.4 Outline drawing . 24
A.4 12ch transmitter and receiver . 25
A.4.1 Block diagram . 25
A.4.2 Electrical terminal assignments . 27
A.4.3 Optical terminal assignments . 32
A.4.4 Outline drawing . 34
Bibliography . 38
Figure 1 – General block diagram for photonic chip scale package . 8
Figure 2 – Electrical terminal numbering assignment (top view) . 9
Figure 3 – Recommended pattern layout for PCB . 10
Figure 4 – Informative electrical strip line wiring for high speed electrical interface . 10
Figure A.1 – Block diagram for chip scale package of 4ch transceiver using silicon
photonics chip with optional pads for LD control. 12
Figure A.2 – Electrical terminal numbering assignment (top view) . 13
Figure A.3 – Optical terminal numbering assignment for 0,25 mm pitch optical interface
for 4ch transceiver (top view) . 16
Figure A.4 – Package outline drawing of 4ch transceiver . 17
Figure A.5 – Block diagram for chip scale package of 8ch transceiver using silicon
photonics chip with optional pads for LD control. 19
Figure A.6 – Electrical terminal numbering assignment (top view) . 20
Figure A.7 – Optical terminal numbering assignment for 0,125 mm pitch optical
interface for 8ch transceiver (top view) . 23
Figure A.8 – Package outline drawing of 8ch transceiver . 24
Figure A.9 – Block diagram for chip scale package of 12ch transmitter using silicon
photonics chip with optional pads for LD control. 26
Figure A.10 – Block diagram for the chip scale package of 12ch receiver with optional
pad for PD bias . 26
Figure A.11 – Electrical terminal numbering assignment (top view) . 27
Figure A.12 – Optical terminal numbering assignment for 0,125 mm pitch optical
interface for 12ch transmitter and receiver (top view) . 33
Figure A.13 – Package outline drawing of 12ch transmitter . 34
Figure A.14 – Package outline drawing of 12ch receiver . 36
Table 1 – Dimensions of recommended pattern layout for PCB . 10
Table A.1 – Specific configurations specified in Annex A . 11
Table A.2 – Terminal function definitions for a 4ch transceiver . 13
Table A.3 – Optical terminal function definitions for 4ch transceiver . 16
Table A.4 – Dimensions of the package outline of 4ch transceiver . 17
Table A.5 – Terminal function definitions for 8ch transceiver. 20
Table A.6 – Optical terminal function definitions for 8ch transceiver . 24
Table A.7 – Dimensions of the package outline of 8ch transceiver . 25
Table A.8 – Terminal function definitions for 12ch transmitter . 27
Table A.9 – Terminal function definitions for 12ch receiver . 30
Table A.10 – Optical terminal function definitions for 12ch transmitter .
...
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