IEC 60747-15:2003

INTERNATIONAL IEC
STANDARD
60747-15
First edition
2003-06
Discrete semiconductor devices –
Part 15:
Isolated power semiconductor devices
Dispositifs à semiconducteurs –
Partie 15:
Dispositifs à semiconducteurs de puissance isolés

Reference number
Publication numbering
As from 1 January 1997 all IEC publications are issued with a designation in the

60000 series. For example, IEC 34-1 is now referred to as IEC 60034-1.

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The IEC is now publishing consolidated versions of its publications. For example,

edition numbers 1.0, 1.1 and 1.2 refer, respectively, to the base publication, the

base publication incorporating amendment 1 and the base publication incorporating

amendments 1 and 2.
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INTERNATIONAL IEC
STANDARD
60747-15
First edition
2003-06
Discrete semiconductor devices –
Part 15:
Isolated power semiconductor devices
Dispositifs à semiconducteurs –
Partie 15:
Dispositifs à semiconducteurs de puissance isolés

 IEC 2003  Copyright - all rights reserved
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– 2 – 60747-15  IEC:2003(E)
CONTENTS
FOREWORD . 4

1 Scope . 5

2 Normative references. 5

3 Terms and definitions . 7

4 Letter symbols .12

4.1 General .12

4.2 Additional subscripts/symbols .12
4.3 List letter symbols.12
5 Essential ratings (limiting values) and characteristics .13
5.1 General .13
5.2 Ratings (limiting values) .13
5.3 Characteristics.16
6 Verification of ratings (limiting values) .24
) .24
6.1 Isolation voltage between terminals and base plate (V
isol
6.2 Peak case non-rupture current.26
6.3 Maximum terminal current (I ) .26
tRMS
6.4 Surge (non-repetitive) current test (I ; I ).26
FSM TSM
7 Methods of measurement of characteristics .26
7.1 Rated partial discharge inception and extinction voltages (V ) (V ) .26
i e
7.2 Parasitic stray inductance between main terminals (L ) .27
P
7.3 Parasitic stray capacitance of functional circuit elements to case (C ) .30
P
7.4 Measuring methods for thermal characteristics .31
7.5 Measuring methods of mechanical characteristics .32
8 Acceptance and reliability .33
8.1 General requirements .33
8.2 List of endurance tests .33
8.3 Type tests and routine tests of isolated power devices .36
Annex A (informative) Test method for peak case non-rupture current.38
Annex B (informative) Measuring method of the thickness of thermal compound paste.41

Annex C (informative) Climatic parameters and characteristics .42
Annex D (informative) Internal circuit configurations.43
Bibliography.44
Figure 1 – Explanation of parasitic inductance L .18
P
Figure 2 – Examples for distributed parasitic stray inductances L .18
P
Figure 3a – Example of a cross-section of an isolated power device mounted on a heat
sink, with the temperatures T ,… T .20
vj a
Figure 3b – Model of thermal resistances of circuit elements R , R , R ,
th(j-c) th(c-s) th(s-a)
resp. Z , Z and Z , schematically .20
th(j-c) th(j-s) th(j-a)
Figure 4 – Reference points for measuring the temperatures T , T , T , T T to be
vj c cI cD s
specified for an isolated power device, seen from above .22

60747-15  IEC:2003(E) – 3 –
Figure 5 – Transient thermal impedance Z = f(t ) of an isolated power
th(j-c) p
semiconductor device as a function of the pulse duration time t , elapsed after a step
p
change of applied power dissipation.23

Figure 6 – Basic circuit diagram for isolation breakdown withstand voltage test (“high

pot test”) with V .24
isol
Figure 7 – Isolation levels of an isolated power device with integrated driver and

protection functions.25

Figure 8a – Circuit diagram for measurement of parasitic stray inductances (L ).28
P
Figure 8b – Wave forms .29

Figure 9 – Circuit for the measurement of parasitic stray capacitance C of
p
the functional circuit elements to base plate (ground).30
Figure 10 – Example for reference points for the measurement of T and T for the
cref sref
thermal resistance of an isolated power semiconductor devices (dual-switch, 62 mm wide).32
Figure 11 – Power cycling (load) capability N versus temperature rise of the junction
f;p
temperature T per load pulse .34
vj
Figure A.1 – Circuit diagram for test of peak case non-rupture current I .38
CNR
Figure B.1– Example of a measuring gauge for a layer of thermal compound paste of a
thickness between 5 µm and 150 µm.41
Figure D.1 – Converter circuits containing diodes and/or thyristors .43
Figure D.2 – Inverter circuits containing diodes and/or transistors shown as IGBT .44
Table 1 – Environmental testing .35
Table 2 – Minimum type and routine tests for isolated power semiconductor devices .36
Table C.1 – Classification of climatic environmental conditions, e.g. Class 3K3 and 3K4
(extract, not complete) .42

– 4 – 60747-15  IEC:2003(E)
INTERNATIONAL ELECTROTECHNICAL COMMISSION

____________
DISCRETE SEMICONDUCTOR DEVICES –

Part 15: Isolated power semiconductor devices

FOREWORD
1) The IEC (International Electrotechnical Commission) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, the IEC publishes International Standards. Their preparation is
entrusted to technical committees; any IEC National Committee interested in the subject dealt with may
participate in this preparatory work. International, governmental and non-governmental organizations liaising
with the IEC also participate in this preparation. The IEC collaborates closely with the International
Organization for Standardization (ISO) in accordance with conditions determined by agreement between the
two organizations.
2) The formal decisions or agreements of the IEC on technical matters express, as nearly as possible, an
international consensus of opinion on the relevant subjects since each technical committee has representation
from all interested National Committees.
3) The documents produced have the form of recommendations for international use and are published in the form
of standards, technical specifications, technical reports or guides and they are accepted by the National
Committees in that sense.
4) In order to promote international unification, IEC National Committees undertake to apply IEC International
Standards transparently to the maximum extent possible in their national and regional standards. Any
divergence between the IEC Standard and the corresponding national or regional standard shall be clearly
indicated in the latter.
5) The IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with one of its standards.
6) Attention is drawn to the possibility that some of the elements of this International Standard may be the subject
of patent rights. The IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60747-15 has been prepared by subcommittee 47E, Discrete
semiconductor devices of IEC technical committee 47: Semiconductor devices
The text of this standard is based on the following documents:
FDIS Report on voting
47E/236/FDIS 47E/238/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
The committee has decided that the contents of this publication will remain unchanged until 2006.
At this date, the publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition, or
• amended.
60747-15  IEC:2003(E) – 5 –
DISCRETE SEMICONDUCTOR DEVICES –

Part 15: Isolated power semiconductor devices

1 Scope
This part of IEC 60747 gives the product specific standards, requirements and test methods
for isolated power semiconductor devices. These requirements are added to those given in
other parts of IEC 60747, IEC 60748 and IEC 60749 for the corresponding non-isolated power
devices.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 60068-2-6, Environmental testing – Part 2-6: Tests – Test Fc: Vibration (sinusoidal)
IEC 60068-2-7, Environmental testing – Part 2-7: Tests – Test Ga and guidance: Acceleration,
steady state
IEC 60068-2-14, Environmental testing – Part 2-14: Tests – Test N: Change of temperature
IEC 60068-2-20, Environmental testing – Part 2-20: Tests – Test T: Soldering
IEC 60068-2-27, Environmental testing – Part 2-27: Tests – Test Ea and guidance: Shock
IEC 60068-2-47, Environmental testing – Part 2-47: Test methods – Mounting of components,
equipment and other articles for vibration, impact and other similar dynamic tests
IEC 60068-2-48, Environmental testing – Part 2-48: Test methods – Guidance on the appli-
cation of the tests of IEC 60068 to simulate the effects of storage
IEC 60068-3-4: Environmental testing – Part 3-4: Supporting documentation and guidance –
Damp heat tests
IEC 60191-4:1999, Mechanical standardization of semiconductor devices – Part 4: Coding
system and classification into forms of package outlines for semiconductor device packages
IEC 60270:2000, High voltage test techniques – Partial discharge measurements
IEC 60319, Presentation and specification of reliability data for electronic components
IEC 60664-1:1992, Insulation coordination for equipment within low-voltage systems –
Principles, requirements and tests
IEC 60721-3-3:1994, Classification of environmental conditions – Part 3-3: Classification
of groups of environmental parameters and their severities – Stationary use at weather-
protected locations
– 6 – 60747-15  IEC:2003(E)
IEC 60747-1:1983, Semiconductor devices – Discrete devices and integrated circuits –
Part 1: General
Amendment 1 (1991)
Amendment 3 (1996)
IEC 60747-2:2000, Semiconductor devices – Discrete devices and integrated circuits – Part 2:

Rectifier diodes
IEC 60747-6:2000, Semiconductor devices – Part 6: Thyristors

IEC 60747-7:2000, Semiconductor devices – Part 7: Bipolar transistors

IEC 60747-8:2000, Semiconductor devices – Part 8: Field effect transistors
IEC 60747-9:1998, Semiconductor devices – Discrete devices – Part 9: Insulated-gate bipolar
transistors (IGBTs)
IEC 60749-5: Semiconductor devices – Mechanical and climatic test methods – Part 5:
Steady-state temperature humidity bias life test
IEC 60749-6: Semiconductor devices – Mechanical and climatic test methods – Part 6:
Storage at high temperature
IEC 60749-10: Semiconductor devices – Mechanical and climatic test methods – Part 10:
Mechanical shock
IEC 60749-12: Semiconductor devices – Mechanical and climatic test methods – Part 12:
Vibration, variable frequency
IEC 60749-14: Semiconductor devices – Mechanical and climatic test methods – Part 14:
Robustness of terminations (lead integrity)
IEC 60749-15: Semiconductor devices – Mechanical and climatic test methods – Part 15:
Resistance to soldering temperature for through-hole mounted devices
IEC 60749-21: Semiconductor devices – Mechanical and climatic test methods – Part 21:
Solderability
IEC 60749-25: Semiconductor devices – Mechanical and climatic test methods – Part 25:
Rapid change of temperature (air, air)
IEC 60749-26: Semiconductor devices – Mechanical and climatic test methods – Part 26:
Rapid change of temperature (air, air)

IEC 60749-36: Semiconductor devices – Mechanical and climatic test methods – Part 36:
Acceleration, steady-state
IEC 61287-1:1995, Power convertors installed on board rolling stock – Part 1: Characteristics
and test methods
ISO 1302:2002, Geometrical Product Specifications (GPS) – Indication of surface texture
in technical product documentation
ISO 2768-2:1989, General tolerances – Part 2: Geometrical tolerances for features without
individual tolerance indications
———————
In preparation.
A new edition is being prepared.

60747-15  IEC:2003(E) – 7 –
3 Terms and definitions
For the purposes of this part of IEC 60747, the following definitions apply.

3.1
isolated power semiconductor device

semiconductor device that contains an integral electrical insulator between cooling surface or

base plate (envelope) and any isolated circuit elements

NOTE 1 Included are solid-state relays (SSRs) incorporating opto-isolated driving units (see IEC 60747-5-1,
IEC 60745-5-2 and IEC 60745-5-3), monolithically integrated ICs with power stages and isolated cooling surface,

i.e. intelligent power devices and isolated discrete plastic encapsulated packages that have an isolated cooling

surface.
NOTE 2 The surface of the package transferring the heat to a heat sink or ambient is referred to as “base plate”.
The surface of the package not transferring the heat is referred to as “envelope”.
3.2
constituent parts of the isolated power semiconductor device
3.2.1
circuit element
any constituent part of a circuit that contributes directly to its operation and performs a
definable function
NOTE Examples include rectifier diodes, thyristors, bipolar transistors, MOSFETs, IGBTs affixed on metallized
isolator substrates and integrated driver and protection circuits.
3.2.2
interconnection
internal connection between circuit elements and between circuit elements and terminals (see
subclause 3.7.2 of IEC 60747-1)
NOTE They are considered to be parts of their associated circuit elements.
3.2.3
base plate
metallic or metallized cooling surface part of the package that transfers the heat from inside to
a heat sink outside
3.2.4
terminals
externally available points of connection, isolated from base plate
3.2.4.1
main terminals
terminals having the high potential of the power circuit and carrying the main current
3.2.4.2
control terminals
terminals having only low current capability for the purpose of control function to which the
external control signals are applied or from which sensing parameters are taken
3.2.4.3
high-voltage control terminals
terminals having the high potential of the power circuit, but carrying only low current for
control function
NOTE Examples include current shunts and collector sense terminals having the high potential of the main
terminals.
– 8 – 60747-15  IEC:2003(E)
3.2.4.4
low-voltage control terminals
terminals at a low potential against base plate having a control function, and isolated from the

“main terminals” as well as from high voltage control terminals

NOTE Examples include the terminals of isolated temperature sensors and isolated gate driver inputs, etc.

3.3
classification of categories of isolated power devices

isolated power semiconductor devices are classified as follows:

3.3.1
chip content: types according to their main functional circuit elements
3.3.1.1
thyristor module
isolated power semiconductor device containing thyristor chips
3.3.1.2
diode module
isolated power semiconductor device containing diode chips
3.3.1.3
bipolar transistor module
isolated power semiconductor device containing bipolar transistor chips and their inverse
diode chips
3.3.1.4
IGBT module
isolated power semiconductor device containing isolated gate bipolar transistor (IGBT) chips
and their inverse diode chips
3.3.1.5
MOSFET module
isolated power semiconductor device containing MOSFET chips
3.3.2
circuit configuration: types according to their main functional circuit
3.3.2.1
single switch
one functional circuit element, the “semiconductor switch”, in one case (as the most simple
functional device) (see Annex D, Figure D.2a)

NOTE 1 Examples include epoxy isolated discrete semiconductors with metallic cooling surface.
NOTE 2 “Switch” is here a commonly used synonym for “functional circuit elements”.
3.3.2.2
dual switch
two switches in one case, series connected, forming a “half bridge” circuit, a phase leg
of a single-phase bridge or three-phase bridge circuit arrangement (see Annex D,
Figure D.2b)
NOTE Examples include “brake chopper” circuit with a high side switch or a low side switch and the freewheeling
diode on the other position, see Annex D, Figure D.2c and D.2d.
3.3.2.3
H – bridge
four switches in one case, two half bridges forming a “full bridge”, a single-phase bridge (see
Annex D, Figure D.2e)
60747-15  IEC:2003(E) – 9 –
3.3.2.4
sixpack
six switches in one case, three half bridges forming a “three-phase bridge” (see Annex D,

Figure D.2f)
3.3.2.5
sevenpack
seven switches in one case, three half bridges forming a three-phase bridge circuit and in

addition a brake chopper circuit (see Annex D, Figures D.2g and D.2h)

NOTE Above circuit configurations are mainly used for transistor inverter circuits producing a.c. output of fixed or

variable frequency from d.c. input voltage, using pulse width modulation (PWM), see Annex D, Figure D.2i (CIB-

converter-inverter-brake chopper devices).
3.3.2.6
bridge rectifier
single-phase bridge converter circuit of 4 diodes in one case (see Annex D, Figure D.1: circuit
B2U, two pulse bridge uncontrolled)
3.3.2.7
half controlled bridge rectifier
single-phase bridge converter circuit of 2 diodes and 2 thyristors in one case (see Annex D,
Figure D.1: B2HK)
3.3.2.8
fully controlled bridge rectifier
single-phase bridge converter circuit of 4 thyristors in one case (see Annex D, Figure D.1:
B2C, two pulse bridge controlled)
3.3.2.9
three phase bridge rectifier
three-phase bridge converter circuit of 6 diodes in one case (see Annex D, Figure D.1: B6U,
six pulse bridge uncontrolled)
3.3.2.10
half controlled three phase bridge rectifier
three-phase bridge converter circuit of 3 diodes and 3 thyristors in one case (see Annex D,
Figure D.1: B6HK)
3.3.2.11
fully controlled three phase rectifier
three-phase bridge converter circuit of 6 thyristors in one case (see Annex D, Figure D.1:
B6C, six pulse bridge controlled)

3.3.2.12
a.c. controller
single-phase (or three-phase) proportional controller of two (or six) inverse-parallel connected
thyristors producing a proportional a.c. output voltage from a.c. input voltage using phase
angle control (see Annex D, Figure D.1: W1C or W3C)
NOTE 1 Above rectifier (or respectively controller) circuits are mainly used as input converters producing a fixed
or – if thyristor controlled – proportional d.c. (or respectively a.c.) output voltage from a.c. input voltage, using
phase-angle control. (See also JESD 14.)
NOTE 2 IEC 60971 provides details. Examples include circuits designated “B2U”,…. “B6C”,…… “W1C”, “W3C”.
3.3.3
other circuit configurations and combinations
for other circuit configurations and combinations for the above circuits, see Annex D.

– 10 – 60747-15  IEC:2003(E)
3.4
functionality: types according to additional functions

such as for measurement, protection and control, including SSRs:

circuits as in 3.2.3, but with enhanced functionality by:

• current shunts or sensors
• temperature sensors
• overcurrent or overvoltage protection

• driver with or without integrated power supply

• further control circuitry
• opto-coupler and auxiliary circuits
• other functions
NOTE Such devices are called intelligent power modules (IPM) on the market. IPM and SMART power devices
are specific names of such specific products.
3.5
solid-state relays
SSRs
isolated power semiconductor devices that incorporate an opto-isolated electronic driving unit
using an input section, fully isolated from the power output side and the metallic or metallized
isolated cooling surface or base plate, performing a switch-on/switch-off function as an
electronic relay producing a non-proportional output
NOTE For SSRs, IEC 60747-5-1, IEC 60747-5-2 and IEC 60747-5-3 also apply.
3.6
isolation voltage
V
isol
isolation breakdown withstand voltage between terminals and base plate (or external heat
sink) over a specified time
NOTE Subclause 1.3.9.1 of IEC 60664-1 defines ‘rated insulation voltage’ as r.m.s. withstand voltage value
assigned by the manufacturer to the equipment or to a part of it, characterizing the specified isolation voltage
withstand capability of its insulation.
3.7
partial discharge inception voltage
V
i
voltage between main terminals and base plate at which partial discharges occur when
the applied voltage is gradually increased from a lower value
NOTE 1 IEC 60270 defines inception voltage as greater than the extinction voltage.

NOTE 2 Subclause 1.3.18.4 of IEC 60664-1 defines ‘partial discharge inception voltage’, U , as the lowest peak
i
value of the test voltage at which the apparent charge becomes greater than the specified discharge magnitude
when the test voltage is increased above a low value for which no discharge occurs.
3.8
partial discharge extinction voltage
V
e
voltage between main terminals and base plate at which partial discharges disappear when
the applied voltage is gradually decreased from a higher value
NOTE 1 IEC 60270 defines the extinction voltage as lower than the inception voltage.
NOTE 2 Subclause 1.3.18.5 of IEC 60664-1 defines ‘partial discharge extinction voltage’, U , as the lowest peak
e
value of the test voltage at which the apparent charge becomes less than the specified discharge magnitude when
the test voltage is reduced below a high level where such discharges have occurred.

60747-15  IEC:2003(E) – 11 –
3.9
creepage distance along surface

d
s
shortest distance along the surface of the insulating material between two conductive parts at

different potentials
NOTE See subclause 1.3.3 of IEC 60664-1 (IEV 151-15-50).

3.10
clearance distance in air
d
a
shortest distance in air between two conductive parts at different potentials

NOTE See 1.3.2 of IEC 60664-1.
3.11
peak case non-rupture current
peak current that will not lead to a rupture of the package, ejecting plasma and massive
particles under specified conditions
NOTE The value indicated depends on the type of the device, e.g. thyristor, diode, IGBT, and the packaging
technology, e.g. whether wire bonded.
3.11.1
peak case non-rupture current for diodes and thyristors
I
RSMC
peak reverse current of a half sine wave, when the device has lost its reverse blocking
capability, that should not be exceeded in order to avoid bursting of the case or emission of
a plasma beam or massive particles under specified conditions
NOTE Specified in IEC 60747-2 for diode devices, respectively IEC 60747-6 for thyristor devices.
3.11.2
peak case non-rupture current for bipolar transistors, IGBT and MOSFETs
I
CNR
peak collector current that should not be exceeded in order to avoid bursting of the case or
emission of a plasma beam or ejection of massive particles under specified conditions
3.12
parasitic stray inductance between main terminals
L
P
inner wiring stray inductance, effective in the main current path between the main terminals
NOTE 1 L of a half-bridge module (dual switch) is the effective parasitic stray inductance L between the power
P CE
terminal (+) (top collector) and power terminal (–) (bottom emitter).
NOTE 2 Parasitic stray inductance L will cause a voltage spike at switch-off (above the continuous d.c. voltage
P
V ) on chip level, higher than the voltage, measured between the terminals.
CC
3.13
parasitic stray capacitance between switching circuit elements and case
C
P
coupling capacitance between all terminals connected together and the base plate (or heat-
sink surface)
NOTE This capacitance can serve as a bypass for parasitic high frequency currents that can cause electro-
magnetic interference (EMI).
3.14
power cycling (load) capability
N
f;p
number of power cycles N until failure of the cumulative percentage p (=percentile) of
f;p
a device population
NOTE Subclause 7.4.6 of IEC 60747-2 (diodes) and 9.4.6 of IEC 60747-6 (thyristors) define “power cycling load
test”. Subclause 10.1.3.3 of Amendment 1 to IEC 60747-9 (IGBT) defines “intermittent operating life tests”.

– 12 – 60747-15  IEC:2003(E)
4 Letter symbols
4.1 General
IEC 60747-1 applies.
4.2 Additional subscripts/symbols

p = parasitic
ref = reference point (for measuring temperatures)

s = heat sink (subscript of heat-sink temperature T )

s
t = time (parameter) used for currents, voltages as function of time: in brackets: (t)
t = terminal (subscript of mounting torque to terminal M )
t
1 = primary side (of a transformer or control input)
2 = secondary side (power output side)
4.3 List letter symbols
4.3.1 Voltages and currents (see also IEC 60747-1)
I
Terminal current
tRMS
V
Isolation voltage
isol
V
Partial discharge inception voltage
i
V
Partial discharge extinction voltage
e
I
Isolation leakage current
isol
I
Peak case non-rupture current (for diode and thyristor devices)
RSMC
I
Peak case non-rupture current (for IGBT and MOSFET devices)
CNR
4.3.2 Mechanical terms
M
Mounting torque for screws to heat sink s see Note 1
M
t
Mounting torque for terminal screws see Note 1
F
Mounting force for pressure mounted devices
a
Maximum acceleration in all 3 axis (x, y, z)
m
Mass
e
c
Flatness of the case (base-plate, cooling surface) see Note 2
e
Flatness of the cooling surface (heat sink) s
R
Zc
Roughness of the case (base plate) see Note 3
R
Roughness of the cooling surface (heat sink) Zs see Note 3
D
(c-s)
Thickness of thermal compound grease (case – sink) see Annex B
NOTE 1 Under given mounting instructions. In respect of thermal compound properties see mounting instructions.
NOTE 2 See for instance IEC 60191-2:1995, outline 191-IEC-080B (34 mm wide module) and 191-IEC-081B
(62 mm wide module) deviation from flatness 100 µm – see Note 4.
NOTE 3 In USA: “R ” is used instead, (R = about 3*R ). There is no fixed factor between those two.
a z a
NOTE 4 Example: Seating plane. Deviation from flatness shall be <20 µm concave and <100 µm convex, the
roughness <10 µm. Flatness and roughness are to be specified as, for instance, defined in the related publication
IEC 60191-2.
60747-15  IEC:2003(E) – 13 –
4.3.3 Other terms
P
Total max. power dissipation per functional circuit element at T = 25 °C tot
c
L
Parasitic inductance, effective between terminals x and y or between terminals and Pxy

chips (to be specified)
C
Parasitic capacitance between all terminals connected together and cooling P

surface (case, base plate, ground)

R
Ohmic lead resistance between terminal x and related functional circuit element x’ xx’

T
Terminal temperature t
T
Sensor temperature sen
T
Significant temperature of the temperature sensor No.1 (to be specified) sen1
T
Significant case temperature at the reference point (to be specified) cref
N
Number of power load cycles until failure of a percentage p of a population of f;p
devices
5 Essential ratings (limiting values) and characteristics
5.1 General
Isolated power semiconductor devices should be specified as case rated or heat-sink rated
devices.
NOTE Actual values regarding isolation voltage, partial discharge voltage, creepage and clearance distance are
not described in this standard. The values shall be based on each standard, which will be applied to any equipment
using the isolated power semiconductor devices.
5.1.1 Temperatures
The ratings and characteristics should be quoted at a temperature of 25 °C or another
specified elevated temperature chosen from Amendment 3 (1996) to IEC 60747-1.
NOTE T = –40 °C is specified in IEC 60749-25.
stg
5.1.2 Climatic characteristics
Limiting values of environmental parameters for the final application are as follows:
• ambient temperature;
• humidity;
• speed and pressure of air;
• irradiation by sun and other heat sources;
• mechanical active substances;
• chemically active substances;
• biological issues.
These shall be described by class, as specified in Table 1 and Annex C of IEC 60721-3-3.
5.2 Ratings (limiting values)
Unless otherwise stated, all limiting ratings apply at a temperature of 25 °C or another
elevated temperature specified from the list in IEC 60747-1. The following ratings shall be
valid for the whole range of operating conditions as stated for the particular device.

– 14 – 60747-15  IEC:2003(E)
5.2.1 Isolation voltage, V
isol
Maximum r.m.s. or d.c. value between the isolated terminals and the base plate, applied

between the high potential terminals, all connected with each other, and the ground potential

of the base plate (or heat sink underneath) for a specified time at the final test procedure of

the device and of the final equipment to assure the capability to isolate the electrical system
from ground potential.
NOTE 1 Details for the dielectric isolation voltage test for solid insulation shall be secured following 2.2.2.2,

4.1.2, 4.1.2.1 and 4.1.2.3.1 of IEC 60664-1 (for low voltage equipment), respectively IEC 61287 (for rolling stock)
depending on the overvoltage category (application), the applied maximum working voltage, etc.

NOTE 2 Specified values are under discussion. The future IEC 62103 (=EN 50178) proposes reduced isolation
voltages in comparison to before.

5.2.2 Peak case non-rupture current (where appropriate)
Maximum surge current that does not cause the bursting of the case or emission of plasma
and particles.
5.2.2.1 Peak case non-rupture current (I ) of isolated diode and thyristor modules
RSMC
Maximum peak reverse current of a half sine wave (e.g. 10 ms), when the device has lost its
reverse blocking capability, that should not be exceeded in order to avoid bursting of the case
or emission of a plasma beam or massive particles.
NOTE Specified in IEC 60747-2 for diode devices and in IEC 60747-6 for thyristors devices.
5.2.2.2 Peak case non-rupture current (I ) of bipolar transistors, IGBTs and
CNR
MOSFETs modules
Maximum peak collector current during a short-circuit that should not be exceeded in order to
avoid bursting of the case or emission of a plasma beam or ejection of massive particles
under specified conditions, i.e. of specified duration t and wave shape, at a driving d.c.
p(SC)
voltage V (e.g. two-thirds V ), driving conditions and a maximum stored energy E of the
CC CES C
feeding d.c. line capacitor, C, and specified short-circuit inductance L (see Note 4 below
SC
and Annex A).
NOTE 1 If an isolated device suffers a short-circuit, then most of the energy stored in the system is discharged
into the device. The prime source of such energy is the DC line capacitor. Due to the very low parasitic inductance
(between 5 nH and 100 nH) in the circuit with isolated IGBT devices, the characteristic time for the discharge of
energy is only 30 µs to 100 µs. Other parts of the system may have larger stored energies (e.g. transformers,
motors, etc.), but their characteristic time for discharge is considerably longer.
NOTE 2 For wire bonded isolated IGBT devices, the minimum limit for material ejection (explosion of the device)
is at a stored capacitive energy of about 10 kJ. Therefore it is necessary in some applications to verify the
reliability of the isolated device in a test and measurement procedure.
NOTE 3 Still to be specified for IGBTs in IEC 60747-9.

NOTE 4 L = L + L + L
SC LSC CSC P
where
Lsc is the inductance of the complete short-circuit between plus and minus;
L is the inductance of the load short-circuited;
LSC
L is the parasitic inductance of the capacitor bank;
CSC
L is the internal parasitic (stray) inductance of the module between collector and emitter terminal respectively
P
between plus and minus bus bar.
5.2.3 Maximum terminal current (I ) (where appropriate)
tRMS
Maximum r.m.s. value of the current through the main terminal under specified conditions as
minimum mounting torque, M and maximum allowed terminal temperature (T = T or
t tmax stg
T = tmax vjmax
NOTE 1 Examples include the common terminal of devices containing multiple isolated functional circuit
elements, all feeding into one terminal, i.e. of a sixpack etc.

60747-15  IEC:2003(E) – 15 –
NOTE 2 It should not be necessary to derate this current with junction temperature, as dissipation caused in the

terminal is not in the semiconductor junction and should be removed over the connections.

5.2.4 Total power dissipation (P )
tot
Maximum value per functional circuit element at T = 25 °C (or T = 25 °C), when T = T ,
c s vj vjmax
at d.c. load, not regarding any power dissipation caused by switching and any lead
resistances of internal connections.

P = V*I – (R + R ) I (1)
tot cc’ ee’
where
V is the measured forward voltage between the related main terminals;
I is the maximum allowable average current;
(R + R ) is the lead resistance to terminals.
cc’ ee’
P = (T – T )/ R (2)
tot vjmax c th(j-c)
for case rated devices, respectively
P = (T – T )/ R (3)
tot vjmax s th(j-s)
for heat sink rated devices.
5.2.5 Minimum and maximum temperatures of isolated devices (T , T , T , T )
stg c vj sold
Maximum allowed solder temperature T during solder process over a specified solder
sold
processing time t . For other temperatures see Amendment 3 to IEC 60747-1.
sold
NOTE This is essential for solderable terminals for printed circuit board (PCB) mounting, important especially for
lead-free soldering, see also IEC 60068-2-58.
5.2.6 Mechanically limiting ratings
Allowed limiting values that do not cause any mechanical damage or failure but secure
mechanical function over the life time of the device and are necessary to meet the data sheet
values:
• minimum and maximum mounting torque M for screws (to be specified) to heat sink (see
s
Note 1);
• minimum and maximum mounting torque M for terminal screws (to be specified) (see Note 1);
t
• minimum and maximum mounting force F for pressure mounted devices (see Note 1);
• maximum pulling force F for terminals (robustness) (see IEC 60749-14);
t
• maximum acceleration, a, in all three axes (x, y, z) (see IEC 60749-36, IEC 60068-2-7 and
IEC 60068-2-47);
• flatness e of the case (base plate) (see Note 2 and IEC 60191-2);
c
• roughness R of the case (base plate) (see Note 3 and IEC 60191-2);
zc
• flatness e of the heat sink surface necessary (see manufacturer’s mounting instructions).
s
NOTE 1 Under given mounting instructions. For thermal compound properties, see mounting instructions and
Annex B.
NOTE 2 For example IEC 60191-2:1995, outline 191-IEC-108 B (34 mm wide transistor module) and 191-IEC-
108 B (62 mm wide transistor module) describe maximum deviation from flatness to be 100 µm (see Note 4).
NOTE 3 In the USA: “R ” is used instead, (R = about 3*R ). There is no fix factor between those two.
a z a
NOTE 4 For example, the seating plane deviation from flatness shall be <20 µm (concave) and <100 µm (convex),
the roughness R <10 µm. If thermal compound is used, R <64 µm may also be suitable (see manufacturer’s
zc zc
instructions). Flatness and roughness are defined in the related publication IEC 60191-2. If the case outline is
IEC standardized, see Annex B.

– 16 – 60747-15  IEC:2003(E)
5.2.6.1 Minimum mounting torque of screws to heat sink (M )
s
Minimum mounting torque that shall be applied to the fixing screws to the heat sink that is

necessary to guarantee the data sheet values of thermal resistance, using the mounting

instructions of the manufacturer.

5.2.6.2 Minimum mounting torque of screws to terminals (M )
t
Minimum mounting torque that shall be applied to screwed main terminals that is necessary to

guarantee the data sheet values of their current carrying capability, based on mounting

instructions.
5.2.6.3 Minimum mounting force (F)
Minimum mounting force for pressure-mounted devices, fixed by clips, that shall be applied to
the isolated pressure contact device that is necessary to guarantee the data sheet values of
thermal resistance and current-carrying capability.
NOTE Such devices include isolated discrete devices with a metallic cooling surface (with outlines as for
IEC 60191-2 / 191IEC I-73a – known also as case outline JEDEC TO-220 or similar case outlines).
5.2.6.4 Maximum allowed terminal pull-out force (F )
t
Maximum allowed value of the force that is not enough to pull the terminal out of its position
and that does not damage the case of the device, respectively the proper electrical contact.
NOTE 1 Pulling leads and/or mechanical vibrations should be avoided.
NOTE 2 In some cases, no pulling force on terminals are acceptable at all: F = 0.
t
5.3 Characteristics
5.3.1 Distances
5.3.1.1 Creepage distance along surface (d )
s
Minimum value of distance along surface of the insulating material of the device between
terminals of different potential and to base plate.
NOTE 1 IEC 60112 and 2.7 and 3.2 of IEC 60664-1, together with Figure D.1 apply.
NOTE 2 Subclause 4.2 of IEC 60664-1 shows typical examples of various shapes of creepage distances,
while 2.5 shows pollution degrees and Table 2 shows minimum clearances.
NOTE 3 Air gaps between plastic surface and grounded metal or between terminals of opposite polarity smaller
than 1,0 mm (for pollution degree 2), or 1,5 mm (pollution degree 3) shorten the countable creepage distance
considerably (for details see the examples in IEC 60664-1). This is essential, if dust, moisture or dirt starts to cover
the surface and increases the leakage current over the surface, which might start burning the plastic encapsulation
material.
5.3.1.2 Clearance distance in air (d )
a
Minimum value of distance through air between terminals of different potential of the isolated
device and of the base plate.
NOTE For details see 2.5 of IEC 60664-1 (pollution degree), as well as 3.1, Tables 1 and 2. See also 4.2 of
IEC 60664-1 showing typical examples of various shapes of clearance distances.
5.3.2 Parasitic stray inductance (L )
P
Maximum or typical value of the inner wiring stray inductance of the circuit element, effective
in the main current path between the main terminals.
NOTE 1 The voltage spike at switch-off can be higher than the continuous d.c. voltage V on chip level, and
CC
higher than the voltage measured between the terminals.

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