IEC 60747-15:2024

IEC 60747-15 ®
Edition 3.0 2024-10
REDLINE VERSION
INTERNATIONAL
STANDARD
colour
inside
Semiconductor devices – Discrete devices
Part 15: Discrete devices – Isolated power semiconductor devices

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IEC 60747-15 ®
Edition 3.0 2024-10
REDLINE VERSION
INTERNATIONAL
STANDARD
colour
inside
Semiconductor devices – Discrete devices
Part 15: Discrete devices – Isolated power semiconductor devices
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 31.080.99 ISBN 978-2-8322-9946-3
– 2 – IEC 60747-15:2024 RLV © IEC 2024
CONTENTS
FOREWORD . 5
1 Scope . 7
2 Normative references. 7
3 Terms and definitions . 8
4 Letter symbols . 9
4.1 General . 9
4.2 Additional subscripts/symbols . 9
4.3 List of letter symbols . 9
4.3.1 Voltages and currents . 9
4.3.2 Mechanical symbols . 10
4.3.3 Other symbols . 10
5 Essential ratings (limiting values) and characteristics . 10
5.1 General . 10
5.2 Ratings (limiting values) . 10
5.2.1 Isolation voltage or isolation test voltage (V ) . 10
isol
5.2.2 Peak case non-rupture current (I or I ) (where appropriate) . 10
RSMC CNR
5.2.3 Terminal current (I ) (where appropriate) . 11
tRMS
5.2.4 Total power dissipation (P ) .
tot
5.2.4 Temperatures . 11
5.2.5 Mechanical ratings . 11
5.2.6 Climatic ratings (where appropriate) . 12
5.3 Characteristics . 12
5.3.1 Mechanical characteristics . 12
5.3.2 Parasitic inductance (L ) . 12
p
5.3.3 Parasitic capacitances (C ) . 12
p
5.3.4 Partial discharge inception voltage (V or V ) (where
iM i(RMS)
appropriate) . 13
5.3.5 Partial discharge extinction voltage (V or V ) (where

eM e(RMS)
appropriate) . 13
5.3.6 Thermal resistances . 13
5.3.7 Transient thermal impedance (Z ) . 13
th
6 Measurement methods . 14
6.1 Verification of isolation voltage rating . 14
6.1.1 Verification of isolation voltage rating between terminals and base plate
(V ) . 14
isol
6.1.2 Verification of isolation voltage rating between temperature sensor and
terminals (V ) . 15
isol1
6.2 Methods of measurement . 16
6.2.1 Partial discharge inception and extinction voltages (V ) (V ) . 16
i e
6.2.2 Parasitic inductance (L ) . 16
p
6.2.3 Parasitic capacitance terminal to case (C ) . 18
p
6.2.4 Thermal characteristics . 19
7 Acceptance and reliability . 23
7.1 General requirements . 23

7.2 List of endurance tests . 23
7.3 Acceptance defining criteria . 24
7.4 Type tests and routine tests . 24
7.4.1 Type tests . 24
7.4.2 Routine tests. 25
Annex A (informative) Test method of peak case non-rupture current . 26
A.1 Purpose . 26
A.2 Circuit diagram . 26
A.3 Test procedure . 29
A.4 Post test measurements and criteria . 29
A.5 Specified conditions . 29
Annex B (informative) Measuring method of the thickness of thermal compound paste . 31
B.1 General . 31
B.2 Measuring method . 31
Annex C (informative) Intelligent power semiconductor modules (IPMs) . 32
C.1 General . 32
C.2 Control terminals of IPM . 32
C.3 Essential ratings (limiting value) and characteristics . 33
C.3.1 General . 33
C.3.2 Ratings (limiting value) and testing method . 33
C.3.3 Characteristics and measuring method . 38
Bibliography . 61

Figure 1 – Basic circuit diagram for isolation breakdown withstand voltage test ("high
pot test") with V . 14
isol
Figure 2 – Basic circuit diagram for isolation voltage test between temperature sensor
and terminals (V ) . 15
isol1
Figure 3 – Circuit diagram for measurement of parasitic inductances (L ) . 17
p
Figure 4 – Wave forms . 18
Figure 5 – Circuit diagram for measurement of parasitic capacitance (C ) . 19
p
Figure 6 – Cross-section of an isolated power device with reference points for
temperature measurement of T and T . 20
c s
Figure A.1 – Circuit diagram for test of peak case non-rupture current . 28
Figure B.1 – Example of a measuring gauge for a layer of thermal compound paste of
a thickness between 5 µm and 150 µm . 31
Figure C.1 – Example of internal circuit configuration block diagram of IPM . 32
Figure C.2 – Testing circuit for supply voltage, input voltage / input signal voltage, and

fault output voltage / alarm signal voltage . 34
Figure C.3 – Testing circuit for fault output current / alarm signal current . 35
Figure C.4 – Testing circuit for main circuit DC bus voltage at short circuit . 37
Figure C.5 – Waveforms of short circuit protection function . 38
Figure C.6 – Measurement circuit for switching times and switching energy at inductive
load (lower arm device measurement) . 39
Figure C.7 – Switching waveforms at inductive load . 40
Figure C.8 – Measurement circuit for control circuit current . 43
Figure C.9 – Measurement circuit for input threshold voltage . 44

– 4 – IEC 60747-15:2024 RLV © IEC 2024
Figure C.10 – Measuring circuit for over current protection level/short circuit trip level . 46
Figure C.11 – Waveforms during over current protection / short circuit protection . 47
Figure C.12 – Measurement circuit for over current protection delay time/Short circuit
current delay time . 49
Figure C.13 – Waveforms of protection delay time during over current protection / short
circuit protection . 50
Figure C.14 – Measurement circuit for over temperature protection and its hysteresis . 52
Figure C.15 – Waveforms during the overheating protection operation and the fault
output . 54
Figure C.16 – Waveforms during the under-voltage protection operation and the fault
output . 55
Figure C.17 – Measurement circuit for fault output current . 56
Figure C.18 – Measurement circuit for common mode noise withstand capability . 58
Figure C.19 – Waveforms during the common mode noise withstand capability
measurement . 59

Table 1 – Endurance tests . 23
Table 2 – Acceptance defining characteristics for endurance and reliability tests . 24
Table 3 – Minimum type and routine tests for isolated power semiconductor devices . 25
Table C.1 – Acceptance defining criteria for the IPM control circuit after rating tests . 38

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
DISCRETE DEVICES –
Part 15: Discrete devices – Isolated power semiconductor devices

FOREWORD
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This redline version of the official IEC Standard allows the user to identify the changes
made to the previous edition IEC 60747-15:2010. A vertical bar appears in the margin
wherever a change has been made. Additions are in green text, deletions are in
strikethrough red text.
– 6 – IEC 60747-15:2024 RLV © IEC 2024
IEC 60747-15 has been prepared by subcommittee 47E: Discrete semiconductor devices, of
IEC technical committee 47: Semiconductor devices. It is an International Standard.
This third edition cancels and replaces the second edition published in 2010. This edition
constitutes a technical revision.
This edition includes the following significant technical changes with respect to the previous
edition:
a) The intelligent power semiconductor modules (IPM), which was previously excluded from
the first and second edition, is now included in this document (Annex C);
b) The thermal resistance is described for each switch (6.2.4);
c) Added isolation test between temperature sensor and terminals, in case there is an
agreement with the user (6.1.2).
The text of this International Standard is based on the following documents:
Draft Report on voting
47E/832/FDIS 47E/844/RVD
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/publications.
This International Standard is to be used in conjunction with IEC 60747-1:2006 and
Amendment 1: 2010.
A list of all parts in the IEC 60747 series, published under the general title Semiconductor
devices, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
• reconfirmed,
• withdrawn, or
• revised.
IMPORTANT – The "colour inside" logo on the cover page of this document indicates
that it contains colours which are considered to be useful for the correct understanding
of its contents. Users should therefore print this document using a colour printer.

SEMICONDUCTOR DEVICES –
DISCRETE DEVICES –
Part 15: Discrete devices – Isolated power semiconductor devices

1 Scope
This part of IEC 60747 gives the requirements for isolated power semiconductor devices
excluding devices with incorporated control circuits. These requirements are additional to those
given in other parts of IEC 60747 for the corresponding non-isolated power devices and parts
of IEC 60748 for ICs.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies.
For undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 60068-2-1:2007, Environmental testing – Part 2-1: Tests – Test A: Cold
IEC 60270:2015, High-voltage test techniques – Partial discharge measurements
IEC 60664-1:20072020, Insulation coordination for equipment within low-voltage systems –
Part 1: Principles, requirements and tests
IEC 60721-3-3:19942019, Classification of environmental conditions – Part 3-3: Classification
of groups of environmental parameters and their severities – Stationary use at weather
protected locations
IEC 60747-1:2006, Semiconductor devices – Part 1: General
IEC 60747-1:2006/AMD1:2010
IEC 60747-2:2016, Semiconductor devices – Discrete devices and integrated circuits – Part 2:
Rectifier diodes
IEC 60747-6:2016, Semiconductor devices – Part 6: Thyristors
IEC 60747-7:2019, Semiconductor discrete devices and integrated circuits – Part 7: Bipolar
transistors
IEC 60747-8:2021, Semiconductor devices – Part 8: Field-effect transistors
IEC 60747-9:2019, Semiconductor devices – Discrete devices – Part 9: Insulated-gate bipolar
transistors (IGBTs)
IEC 60748 (all parts), Semiconductor devices – Integrated circuits
IEC 60749-5:2017, Semiconductor devices – Mechanical and climatic test methods – Part 5:
Steady-state temperature humidity bias life test

– 8 – IEC 60747-15:2024 RLV © IEC 2024
IEC 60749-6:2017, Semiconductor devices – Mechanical and climatic test methods – Part 6:
Storage at high temperature
IEC 60749-10:2003, Semiconductor devices – Mechanical and climatic test methods – Part 10:
Mechanical shock
IEC 60749-12:2017, Semiconductor devices – Mechanical and climatic test methods – Part 12:
Vibration, variable frequency
IEC 60749-15:2020, Semiconductor devices – Mechanical and climatic test methods – Part 15:
Resistance to soldering temperature for through-hole mounted devices
IEC 60749-21:2011, Semiconductor devices – Mechanical and climatic test methods – Part 21:
Solderability
IEC 60749-25:2003, Semiconductor devices – Mechanical and climatic test methods – Part 25:
Temperature cycling
IEC 60749-34:2010, Semiconductor devices – Mechanical and climatic test methods – Part 34:
Power cycling
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminology databases for use in standardization at the following
addresses:
• IEC Electropedia: available at https://www.electropedia.org/
• ISO Online browsing platform: available at https://www.iso.org/obp
3.1
isolated power semiconductor device
semiconductor power device that contains an integral electrical insulator between the cooling
surface or base plate and any isolated circuit elements
3.2
constituent parts of the isolated power semiconductor device
3.2.1
switch
any single component that performs a switching function in an electrical circuit, e.g. diode,
thyristor, MOSFET, etc.
Note 1 to entry: A switch might be a parallel or series connection of several chips with a single functionality.
3.2.2
base plate
part of the package having a cooling surface that transfers the heat from inside to outside
3.2.3
main terminal
terminal having a high potential of the power circuit and carrying the main current
Note 1 to entry: The main terminal can comprise more than one physical connector.

3.2.4
control terminal
terminal having a low current capability for the purpose of control function, to which the external
control signals are applied or from which sensing parameters are taken
3.2.4.1
high voltage control terminal
terminal electrically connected to an isolated circuit element, but carrying only low current for
control function
Note 1 to entry: Examples include current shunts and collector sense terminals having the high potential of the
main terminals.
3.2.4.2
low voltage control terminal
terminal having a control function and isolated from the high voltage control terminals
Note 1 to entry: Examples include the terminals of isolated temperature sensors and isolated gate driver inputs,
etc.
3.2.5
insulation layer
integrated part of the device case that insulates any part having high potential from the cooling
surface or external heat sink and any isolated circuit element
3.3
peak case non-rupture current
peak current, which will not lead to a rupture of the package, ejecting plasma and massive
particles under specified conditions
3.4
thermal interface material
heat conducting material between base plate and external heat sink
4 Letter symbols
4.1 General
General letter symbols are defined in Clause 4 of IEC 60747-1:2006.
4.2 Additional subscripts/symbols
p parasitic
t terminal
isol isolation
m = mount
4.3 List of letter symbols
4.3.1 Voltages and currents
Terminal current I
tRMS
Isolation voltage V
isol
Partial discharge inception voltage V
i
Partial discharge extinction voltage V
e
Isolation leakage current I
isol
– 10 – IEC 60747-15:2024 RLV © IEC 2024
Peak case non-rupture current (for diode and thyristor devices) I
RSMC
Peak case non-rupture current (for IGBT and MOSFET devices) I
CNR
4.3.2 Mechanical symbols
Mounting torque for screws to heat sink M
s
Mounting torque for terminal screws M
t
Mounting force F
Maximum Acceleration in all 3 axis (x, y, z) a
Mass m
Flatness of the case (base plate) e
c
Flatness of the cooling heat sink surface (heat sink) e
s
Roughness of the case (base plate) R
Zc
Roughness of the cooling heat sink surface (heat sink) R
Zs
Thickness of thermal interface material (case – heat sink) d
(c-s)
4.3.3 Other symbols
Total maximum power dissipation per switch at T = 25 °C P
c tot
Parasitic inductance, effective between terminals and chips (to be specified) L
p
Parasitic capacitance between terminals and cooling surface (case, base plate, ground) C
p
Lead resistance between terminal x and related switch internal device connection x' r
xx
Terminal temperature T
t
Number of power load cycles until failure of a percentage p of a population of devices N
f;p
5 Essential ratings (limiting values) and characteristics
5.1 General
Isolated power semiconductor devices should be specified as case rated or heat sink rated
devices. The ratings and characteristics should be quoted at a temperature of 25 °C or another
specified elevated temperature. Requirements for multiple devices having a common
encapsulation are described in 5.12 of IEC 60747-1:2006.
5.2 Ratings (limiting values)
5.2.1 Isolation voltage or isolation test voltage (V )
isol
Maximum RMS or DC value between main terminals and high voltage control terminals at one
side and low voltage control terminals (where appropriate) and base plate at the other side for
a specified time.
5.2.2 Peak case non-rupture current (I or I ) (where appropriate)
RSMC CNR
Maximum value for each main terminal that does not cause the bursting of the case or emission
of plasma and particles.
5.2.3 Terminal current (I ) (where appropriate)
tRMS
Maximum RMS value of the current through the main terminal under specified conditions at
minimum mounting torque M and maximum allowed terminal temperature (T = T or T

t tmax stg tmax
≤ T ).
vjmax
5.2.4 Total power dissipation (P )
tot
Maximum value per switch at T = 25 °C (or T = 25 °C), when T = T , at d.c. load.
c s vj vjmax
5.2.4 Temperatures
5.2.4.1 Solder temperature (T ) (where appropriate)
sold
Maximum solder temperature T during solder process over a specified solder processing
sold
time t .
sold
5.2.4.2 Storage temperature (T )
stg
Minimum and maximum storage temperature.
5.2.5 Mechanical ratings
5.2.5.1 Mounting torque for screws to heat sink (M )
s
Minimum and maximum mounting torque that shall be applied to the fixing screws to the heat
sink.
5.2.5.2 Mounting torque for screws to terminals (M )
t
Minimum and maximum mounting torque that shall be applied to screwed terminals.
5.2.5.3 Mounting force (F)
Minimum and maximum mounting force for pressure mounted devices, fixed by clips, that shall
be applied to the isolated pressure contact device.
5.2.5.4 Terminal pull-out force (F )
t
Maximum force.
5.2.5.5 Acceleration (a)
Maximum value along each axis (x, y, z).
5.2.5.6 Flatness of the heat sink surface (e ) (where appropriate)
s
Maximum deviation from flatness for the heat sink surface over the whole mounting area.
5.2.5.7 Roughness of the heat sink surface (R ) (where appropriate)
Zs
Maximum roughness of the heat sink surface over the whole mounting area.

– 12 – IEC 60747-15:2024 RLV © IEC 2024
5.2.6 Climatic ratings (where appropriate)
Limiting values of environmental parameters for the final application as follows:
– ambient temperature;
– humidity;
– speed and pressure of air;
– irradiation by sun and other heat sources;
– mechanical active substances;
– chemically active substances;
– biological issues,
shall be described in classes as specified in IEC 60721-3-3:19942019, Table 1.
5.3 Characteristics
5.3.1 Mechanical characteristics
5.3.1.1 Creepage distance along surface (d )
s
Minimum value of distance along surface of the insulating material of the device between
terminals of different potential and to base plate.
NOTE 1 IEC 60112:2020 (details to comparative tracking index "CTI") and IEC 60664-1:20072020, 5.2 apply.
NOTE 2 Air gaps between plastic surface and grounded metal or between terminals of opposite polarity smaller
than 1,0 mm (for pollution degree 2), or 1,5 mm (pollution degree 3) shorten the countable creepage distance
considerably (details see 60664-1:20072020, examples). This is essential, if dust, moisture or dirt starts to cover the
surface and increases the leakage current over surface, which might start burning the plastic encapsulation material.
5.3.1.2 Clearance distance in air (d )
a
Minimum value of distance through air between terminals of different potential of the isolated
device and to base plate.
NOTE For details, see IEC 60664-1:20072020, 4.6 and 5.1 which show typical examples of various shapes of
clearance distances.
5.3.1.3 Mass (m) of the device
Maximum value excluding accessories (mounting hardware).
5.3.1.4 Flatness of the case (base plate) (e ) (where appropriate)
c
Maximum and minimum allowed deviation from flatness for the base plate and its direction
(convex or concave).
5.3.2 Parasitic inductance (L )
p
Maximum or typical value between the main terminals of each main current path.
5.3.3 Parasitic capacitances (C )
p
Maximum value of parasitic capacitance between the specified main terminal(s) and the cooling
surface.
5.3.4 Partial discharge inception voltage (V or V ) (where appropriate)
iM i(RMS)
Minimum peak value V or RMS value V between the isolated terminals and the base
iM i(RMS)
plate (details, see IEC 60270:2015).
5.3.5 Partial discharge extinction voltage (V or V ) (where appropriate)
eM e(RMS)
Minimum peak value V or RMS value V between the isolated terminals and the base
eM e(RMS)
plate (for details, see IEC 60270:2015).
5.3.6 Thermal resistances
5.3.6.1 Thermal resistance junction to case for case rated devices (R )
th(j-c)X
Maximum value of thermal resistance junction to a specified reference point at the case (base
plate) per switch "X" (for example of the diode (D), thyristor (T), IGBT (I) or MOSFET (M)).
5.3.6.2 Thermal resistance case to heat sink (R ) (where appropriate)
th(c-s)
Maximum or typical value of thermal resistance between two specified points at the case and
at the heat sink of the case rated device ("module"), when the case is mounted according to
manufacturer's mounting instructions.
5.3.6.3 Thermal resistance case to heat sink per switch (R )
th(c-s)X
(where appropriate)
Maximum or typical value of thermal resistance between the two specified points of the case
and the heat sink of the switch "X" (for example of the diode (D), thyristor (T), IGBT (I) or
MOSFET (M)) of the isolated case rated devices ("module"), when the case is mounted
according to the manufacturer's mounting instructions.
5.3.6.4 Thermal resistance junction to heat sink for heat sink rated devices (R )
th(j-s)X
Maximum or typical value of thermal resistance junction to a specified point at the heat sink per
switch "X" (for example of the diode (D), thyristor (T), IGBT (I) or MOSFET (M)), when the
device is mounted according to the manufacturer's mounting instructions.
5.3.6.5 Thermal resistance junction to sensor (R ) (where appropriate)
th(j-r)
Value of thermal resistance junction to an integrated temperature sensor when the device is
mounted according to the manufacturer's mounting instructions.
NOTE The position of this thermal resistance should be shown in the thermal resistance
equivalent circuit.
5.3.7 Transient thermal impedance (Z )
th
Thermal impedance as a function of the time elapsed after a step change of power dissipation
for each thermal resistance specified in 5.3.6 and shall be specified in one of the following ways.

– 14 – IEC 60747-15:2024 RLV © IEC 2024
6 Measurement methods
6.1 Verification of isolation voltage rating
6.1.1 Verification of isolation voltage rating between terminals and base plate (V )
isol
– Purpose
Proof of the ability of the isolated power device to withstand the rated isolation voltage.
– Circuit diagram
S
H
H
n
G
V
DUT
Base plate
A
E
IEC  2976/10
See Figure 1.
Key
DUT device under test
G voltage source with high impedance, capable to supply V
isol
S main switch
V voltmeter for V
isol
A ammeter or current probe for Iisol
H …H high potential terminal
1 n
Figure 1 – Basic circuit diagram for isolation breakdown withstand
voltage test ("high pot test") with V
isol
The voltage source G is capable to supply the isolation voltage V as the AC or DC voltage
isol
with a high internal impedance to limit the possible breakthrough current in case of
breakdown of the DUT.
All main terminals and high voltage control terminals are connected together and connected
to the high potential output terminal H of the voltage source G. The base plate of the DUT,
respectively its metallized cooling surface and all low voltage terminals are connected to
ground potential E. An amperemeter or current probe A is applied to measure the isolation
leakage current.
If there is an agreement with user, perform an isolation test between the temperature sensor
and the terminals (V ) (See 6.1.2).
Isol1
– Test procedure
Switch S is closed and the voltage is slowly raised to the specified value and maintained at
that value for the specified time. The current measured on ammeter A shall not exceed the
specified value. The voltage is then reduced to zero.
– Specified conditions
Specified in IEC 60664-1:20072020.
• Ambient or case temperature
• V
isol
• I as maximum test limit
isol
• Test time t, if less than 60 s.
6.1.2 Verification of isolation voltage rating between temperature sensor and
terminals (V )
isol1
– Purpose
To verify that the isolation voltage between the temperature sensor and the other terminals
in case the temperature sensor is connected to the base plate potential.
– Circuit diagram
See Figure 2.
Figure 2 – Basic circuit diagram for isolation voltage test
between temperature sensor and terminals (V )
isol1
– Circuit description and requirements, test procedure and specified conditions
Similar as described in 6.1.1, but optionally a lower test voltage V may be specified and
isol1
applied.
– 16 – IEC 60747-15:2024 RLV © IEC 2024
6.2 Methods of measurement
6.2.1 Partial discharge inception and extinction voltages (V ) (V )
i e
Between high potential terminals and base plate (where appropriate). See IEC 60270:2015 and
IEC 60664-1:20072020.
6.2.2 Parasitic inductance (L )
p
– Purpose
To measure the parasitic inductance between two main terminals.
– Circuit diagram
See Figure 3.
Key
DUT device under test T +T , for example IGBT (Single or Dual – shown – or branch of a three phase
1 2
arrangement), fast diode or MOSFET device
C main capacitor bank as reservoir
L load inductance, at least 100 times the parasitic inductance
L
L …L portions of parasitic inductance L
p1 pn p
I current probe
DUT
G voltage source to charge the capacitor
T DUT, top switch (shown as IGBT in Figure 3)
T DUT, bottom switch (shown as IGBT in Figure 3), optional
T auxiliary IGBT switch
Figure 3 – Circuit diagram for measurement of parasitic inductances (L )
p
– 18 – IEC 60747-15:2024 RLV © IEC 2024

Figure 4 – Wave forms
– Circuit description and requirements
The circuit of Figure 3 consists of a DC supply G for the charge reservoir C; T is an auxiliary
switch, a gate drive unit for T , the DUT inserted into the test set-up with the gate control
terminals shorted, a dual channel oscilloscope, which senses the voltage v between main
CE
terminals "C " and "E ", a current probe, which senses the current i through the diode
1 2 DUT
path of the DUT, connected to the dual channel oscilloscope. This measuring method uses
reduced voltage V and the di/dt of diodes incorporated in the device at switch-off, sensing
CC
the voltage at outside main terminals. This is usable for single switch devices as well as for
half bridge circuit devices (DUAL modules).
– Measurement procedure
The waveforms observed by this measurement shown in Figure 4.
A pulsed current method is used. Auxiliary transistor T switches the load current to the
inductor L on and off. When T is off, the current freewheels via the diodes of the DUT.
L 3
When T switches on again, it causes the current through the diodes to fall at an almost
linear rate di /dt. During this time (t –t ), the voltage across the DUT forms at step of
DUT 1 2
V caused by the internal parasitic inductance at current decline (di /dt). The value of
step DUT
the parasitic inductance of the main current path can be calculated from
L = V / |(di /dt)|
(1)
p step DUT
NOTE Use low inductance (sheeted) bus baring and low inductance current probe.
6.2.3 Parasitic capacitance terminal to case (C )
p
– Purpose
To measure the parasitic capacitance C between specified main terminal(s) and the case
p
(base plate)
– Circuit diagram
See Figure 5.
Key
C parasitic capacitance
p
H high potential terminal
CM capacitance meter
Figure 5 – Circuit diagram for measurement of parasitic capacitance (C )
p
– Measurement procedure
Mount the device to a grounded heat sink according to the manufacturer's mounting
instructions. Connect the current source connector "I " of the capacitance meter CM to the
specified terminal and connector "I " to ground (base plate) of the DUT. Connect the voltage
sensing connector of the capacitance meter to test points "V " and "V " to ground. CM is
1 2
set to the specified frequency. The capacitance C can be read on CM. For the measurement
p
of the total coupling capacitance C connect all main terminals to each other and proceed
p
with the measurement as described above.
– Specified conditions
• Measurement frequency f of the CM.
6.2.4 Thermal characteristics
6.2.4.1 General description of measuring methods
– Purpose
To measure thermal characteristics between the switch and the cooling system.
– Reference points for temperature measurement and description
Same methods should be used as for the corresponding non-isolated device. Thermal
resistance and impedance are measured in the same way as described in the documents
for diodes IEC 60747-2:2016, thyristors IEC 60747-6:2016, bipolar transistors
IEC 60747-7:2019, FETs IEC 60747-8:2021 and IGBTs IEC 60747-9:2019.

– 20 – IEC 60747-15:2024 RLV © IEC 2024

Chip 1 Chip n
DUT
T
T T T
sX
j1 j2 jn
Isolation layer
Base plate
Thermal interface material
Specified distance
External heat sink
T T T
c1 c2 sn
IEC  2980/10
Key
T = junction temperature of chip 1 to n
j1…n
T = case temperature under chip 1 to n
c1…n
T = heatsink temperature under chip 1 to n
s1.n
T = heatsink temperature at a specified surface point
sX
Key
T junction temperature of chip X
vjX
T case temperature under chip X
cX
T heat sink temperature under chip X
sX
Figure 6 – Cross-section of an isolated power device
with reference points for temperature measurement of T and T
c s
– Measurement procedure
Cross-sectional view of an isolated power device is shown in Figure 6.

T T is measured by a temperature measuring instrument from underneath through a small
c cX
hole through the heat sink and any thermal interface material underneath the switch X(chip).
T T is taken from above at hottest accessible point, nearest to the switch X(chip) or from
s sX
underneath through a specified sack hole ending at 2 (±1) mm below the heat sink surface
(to be specified, type test feature). T T is de
...