IEC 60424-5:2009

IEC 60424-5 ®
Edition 1.0 2009-02
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Ferrite cores – Guide on the limits of surface irregularities –
Part 5: Planar-cores
Noyaux de ferrite – Guide relatif aux limites des irrégularités de surface –
Partie 5: Noyaux planaires
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IEC 60424-5 ®
Edition 1.0 2009-02
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Ferrite cores – Guide on the limits of surface irregularities –
Part 5: Planar-cores
Noyaux de ferrite – Guide relatif aux limites des irrégularités de surface –
Partie 5: Noyaux planaires
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
N
CODE PRIX
ICS 29.100.10 ISBN 978-2-88910-190-0
– 2 – 60424-5 © IEC:2009
CONTENTS
FOREWORD.3

1 Scope.5

2 Normative references .5

3 Limits of surface irregularities.6

3.1 Chips and ragged edges.6

3.1.1 Chips and ragged edges on the mating surfaces (see Figures 1, 2

and 3).6

3.1.2 Chips and ragged edges on other surfaces.7
3.2 Cracks.10
3.3 Flash.10
3.4 Pull-out .10

Figure 1 – Chip location for planar EL-core.6
Figure 2 – Chip location for low profile E-core.6
Figure 3 – Chip location for low profile ER-core .6
Figure 4 – Cracks and pull-out location for planar EL-core .10
Figure 5 – Cracks and pull-out location for low profile E-core.11
Figure 6 – Cracks and pull-out location for low profile ER-core .11
Figure 7 – Reference dimensions for EL-core .11
Figure 8 – Reference dimensions for E-core .12
Figure 9 – Reference dimensions for ER-core.13

Table 1 – Allowable areas of chips in mm for planar EL-core.7
Table 2 – Allowable areas of chips in mm for low profile E-core .8
Table 3 – Allowable areas of chips in mm for low profile ER-core .8
Table 4 – Area and length reference for visual inspection .9
Table 5 – Limits of cracks for planar EL-core .12
Table 6 – Limits of cracks for low profile E-core.13
Table 7 – Limits of cracks for low profile ER-core .14

60424-5 © IEC:2009 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION

____________
FERRITE CORES –
GUIDE ON THE LIMITS OF SURFACE IRREGULARITIES –

Part 5: Planar-cores
FOREWORD
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International Standard IEC 60424-5 has been prepared by IEC technical committee 51:
Magnetic components and ferrite materials.
This bilingual version, published in 2009-07, corresponds to the English version.
The text of this standard is based on the following documents:
FDIS Report on voting
51/947/FDIS 51/950/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
The French version of this standard has not been voted upon.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.

– 4 – 60424-5 © IEC:2009
A list of all parts of the IEC 60424 series, under the general title Ferrite cores – Guide on the

limits of surface irregularities, can be found on the IEC website.

The committee has decided that the contents of this publication will remain unchanged until

the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in

the data related to the specific publication. At this date, the publication will be

• reconfirmed,
• withdrawn,
• replaced by a revised edition, or

• amended.
60424-5 © IEC:2009 – 5 –
FERRITE CORES –
GUIDE ON THE LIMITS OF SURFACE IRREGULARITIES –

Part 5: Planar-cores
1 Scope
This part of IEC 60424 gives guidance on allowable limits of surface irregularities applicable
to planar-cores in accordance with the relevant generic specification defined in IEC 60424-1.
The relations between the main dimensions of planar E-, ER- and EL-cores differ from those
of standard cores. For example, the width of planar cores is larger while the total height is
much smaller. Also the thickness of the legs is in most cases smaller than compared to
standard cores. Therefore the concept of fixed reference dimensions to determine the length
of crack limits yield crack lengths which are not acceptable for this type of core. This part of
IEC 60424 follows another concept which relates the crack length to dimensions of the
surface on which the crack occurs.
Also the concept to determine the maximum area of chips based on the total mating surface
fails in the case of planar cores. The outer legs of planar cores are much thinner than those of
standard cores which makes overlapping and gluing much more difficult. A single chip of
maximum size on the outer leg may risk the functionality of the core set. Therefore this
standard uses as a reference the mating surface on which the chip occurs.
Windings of planar cores are often PCBs which are glued to the inner surfaces of the planar
core. For thi
...