EN 60191-6-22:2013

SLOVENSKI STANDARD
01-junij-2013
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Mechanical Standardization Of Semiconductor Devices - Part 6-22: General rules for the
preparation of outline drawings of surface mounted semiconductor device packages -
Design guide for semiconductor packages Silicon Fine-pitch Ball Grid Array and Silicon
Fine-pitch Land Grid Array (S-FBGA and S-FLGA)
/
/
Ta slovenski standard je istoveten z: EN 60191-6-22:2013
ICS:
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

EUROPEAN STANDARD
EN 60191-6-22
NORME EUROPÉENNE
March 2013
EUROPÄISCHE NORM
ICS 31.080.01
English version
Mechanical standardization of semiconductor devices -
Part 6-22: General rules for the preparation of outline drawings of surface
mounted semiconductor device packages -
Design guide for semiconductor packages Silicon Fine-pitch Ball Grid
Array and Silicon Fine-pitch Land Grid Array (S-FBGA and S-FLGA)
(IEC 60191-6-22:2012)
Normalisation mécanique des dispositifs à Mechanische Normung von
semiconducteurs - Halbleiterbauelementen -
Partie 6-22: Règles générales pour la Teil 6-22: Allgemeine Regeln für die
préparation des dessins d'encombrement Erstellung von Gehäusezeichnungen von
des dispositifs à semiconducteurs à SMD-Halbleitergehäusen -
montage en surface - Konstruktionsleitfaden für
Guide de conception pour les boîtiers Halbleitergehäuse Si-Feinraster-Ball-Grid-
matriciels à billes et à pas fins en silicium Array und Si-Feinraster-Land-Grid-Array
et boîtiers matriciels à zone de contact (S-FBGA und S-FLGA)
plate et à pas fins en silicium (IEC 60191-6-22:2012)
(S-FBGA et S-FLGA)
(CEI 60191-6-22:2012)
This European Standard was approved by CENELEC on 2013-01-15. CENELEC members are bound to comply
with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard
the status of a national standard without any alteration.

Up-to-date lists and bibliographical references concerning such national standards may be obtained on
application to the CEN-CENELEC Management Centre or to any CENELEC member.

This European Standard exists in three official versions (English, French, German). A version in any other
language made by translation under the responsibility of a CENELEC member into its own language and notified
to the CEN-CENELEC Management Centre has the same status as the official versions.

CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus,
the Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany,
Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland,
Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and the United Kingdom.
CENELEC
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung

Management Centre: Avenue Marnix 17, B - 1000 Brussels

© 2013 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.
Ref. No. EN 60191-6-22:2013 E
Foreword
The text of document 47D/812/CDV, future edition 1 of IEC 60191-6-22, prepared by SC 47D,
"Semiconductor packaging", of IEC TC 47, "Semiconductor devices" was submitted to the IEC-CENELEC
parallel vote and approved by CENELEC as EN 60191-6-22:2013.
The following dates are fixed:
(dop) 2013-10-15
• latest date by which the document has
to be implemented at national level by
publication of an identical national
standard or by endorsement
(dow) 2016-01-15
• latest date by which the national
standards conflicting with the

document have to be withdrawn
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CENELEC [and/or CEN] shall not be held responsible for identifying any or all such patent
rights.
Endorsement notice
The text of the International Standard IEC 60191-6-22:2012 was approved by CENELEC as a European
Standard without any modification.
In the official version, for Bibliography, the following notes have to be added for the standards indicated:
IEC 60191-6 NOTE  Harmonized as EN 60191-6.
IEC 60191-6-5 NOTE  Harmonized as EN 60191-6-5.
IEC 60191-6-12 NOTE  Harmonized as EN 60191-6-12.

IEC 60191-6-22 ®
Edition 1.0 2012-12
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Mechanical standardization of semiconductor devices –

Part 6-22: General rules for the preparation of outline drawings of surface

mounted semiconductor device packages – Design guide for semiconductor

packages Silicon Fine-pitch Ball Grid Array and Silicon Fine-pitch Land Grid

Array (S-FBGA and S-FLGA)
Normalisation mécanique des dispositifs à semiconducteurs –

Partie 6-22: Règles générales pour la préparation des dessins d'encombrement

des dispositifs à semiconducteurs à montage en surface – Guide de conception

pour les boîtiers matriciels à billes et à pas fins en silicium et boîtiers matriciels

à zone de contact plate et à pas fins en silicium (S-FBGA et S-FLGA)

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX Q
ICS 31.080.01 ISBN 978-2-83220-526-6

– 2 – 60191-6-22 © IEC:2012
CONTENTS
FOREWORD . 3
1 Scope . 5
2 Normative references . 5
3 Terms and definitions . 5
4 Terminal position numbering . 5
5 Code of package nominal dimensions . 5
6 Symbols and drawings . 6
7 Dimensions . 9
7.1 Group 1 . 9
7.2 Group 2 . 11
8 Combination list of D, E, M , and M . 12
D E
Bibliography . 17

Figure 1 – S-FBGA outline . 6
Figure 2 – S-FLGA outline . 7
e)
Figure 3 – Mechanical gauge drawing . 8
f)
Figure 4 – Array of terminal-existence areas . 8

Table 1 – Dimensions and tolerances in Group 1 . 9
Table 2 – Dimensions and tolerances of Group 2 . 11
Table 3 – e = 0,80 mm pitch S-FBGA and S-FLGA . 12

Table 4 – e = 0,65 mm pitch S-FBGA and S-FLGA . 12

Table 5 – e = 0,50 mm pitch S-FBGA and S-FLGA . 13

Table 6 – e = 0,40 mm pitch S-FBGA and S-FLGA . 14

Table 7 – e = 0,30 mm pitch S-FBGA and S-FLGA . 15

Table 8 – e = 0,25 mm pitch S-FLGA . 16

60191-6-22 © IEC:2012 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –

Part 6-22: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages –
Design guide for semiconductor packages Silicon Fine-pitch Ball Grid
Array and Silicon Fine-pitch Land Grid Array (S-FBGA and S-FLGA)

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
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agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
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between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
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services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60191-6-22 has been prepared by subcommittee 47D:
Semiconductor packaging, of IEC technical committee 47: Semiconductor devices.
The text of this standard is based on the following documents:
CDV Report on voting
47D/812/CDV 47D/820/RVC
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.

– 4 – 60191-6-22 © IEC:2012
A list of all the parts in the IEC 60191 series, under the general title Mechanical
standardization of semiconductor devices, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
60191-6-22 © IEC:2012 – 5 –
MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –

Part 6-22: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages –
Design guide for
...