EN 60191-6-17:2011

SLOVENSKI STANDARD
01-junij-2011
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Mechanical standardization of semiconductor devices - Part 6-17: General rules for the
preparation of outline drawings of surface mounted semiconductor device packages -
Design guide for stacked packages - Fine-pitch ball grid array and fine-pitch land grid
array (P-PFBGA and PPFLGA) (IEC 60191-6-17:2011)
Mechanische Normung von Halbleiterbauelementen - Teil 6-17: Allgemeine Regeln für
die Erstellung von Gehäusezeichnungen von SMD-Halbleitergehäusen -
Konstruktionsleitfaden für gestapelte Gehäuse - Feinraster-Ball-Grid-Array und
Feinraster-Land-Grid-Array (P-PFBGA/P-PFLGA) (IEC 60191-6-17:2011)
Normalisation mécanique des dispositifs à semiconducteurs - Partie 6-17: Règles
générales pour la préparation des dessins d'encombrement des dispositifs à
semiconducteurs à montage en surface - Guide de conception pour les boîtiers emplilés
- Boîtiers matriciels à billes et à pas fins et boîtiers matriciels à zone de contact plate et à
pas fins (P-PFBGA et P-PFLGA) (CEI 60191-6-17:2011)
Ta slovenski standard je istoveten z: EN 60191-6-17:2011
ICS:
01.100.25 5LVEHVSRGURþMD Electrical and electronics
HOHNWURWHKQLNHLQHOHNWURQLNH engineering drawings
31.240 Mehanske konstrukcije za Mechanical structures for
elektronsko opremo electronic equipment
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

EUROPEAN STANDARD
EN 60191-6-17
NORME EUROPÉENNE
April 2011
EUROPÄISCHE NORM
ICS 31.080.01
English version
Mechanical standardization of semiconductor devices -
Part 6-17: General rules for the preparation of outline drawings of surface
mounted semiconductor device packages -
Design guide for stacked packages -
Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-
PFLGA)
(IEC 60191-6-17:2011)
Normalisation mécanique des dispositifs à Mechanische Normung von
semiconducteurs - Halbleiterbauelementen -
Partie 6-17: Règles générales pour la Teil 6-17: Allgemeine Regeln für die
préparation des dessins d'encombrement Erstellung von Gehäusezeichnungen von
des dispositifs à semiconducteurs à SMD-Halbleitergehäusen -
montage en surface - Konstruktionsleitfaden für gestapelte
Guide de conception pour les boîtiers Gehäuse -
emplilés - Feinraster-Ball-Grid-Array und Feinraster-
Boîtiers matriciels à billes et à pas fins et Land-Grid-Array (P-PFBGA/P-PFLGA)
boîtiers matriciels à zone de contact plate (IEC 60191-6-17:2011)
et à pas fins (P-PFBGA et P-PFLGA)
(CEI 60191-6-17:2011)
This European Standard was approved by CENELEC on 2011-03-03. CENELEC members are bound to comply
with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard
the status of a national standard without any alteration.

Up-to-date lists and bibliographical references concerning such national standards may be obtained on
application to the Central Secretariat or to any CENELEC member.

This European Standard exists in three official versions (English, French, German). A version in any other
language made by translation under the responsibility of a CENELEC member into its own language and notified
to the Central Secretariat has the same status as the official versions.

CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus,
the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy,
Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia,
Spain, Sweden, Switzerland and the United Kingdom.

CENELEC
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung

Management Centre: Avenue Marnix 17, B - 1000 Brussels

© 2011 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.
Ref. No. EN 60191-6-17:2011 E
Foreword
The text of document 47D/785/FDIS, future edition 1 of IEC 60191-6-17, prepared by SC 47D,
Mechanical standardization for semiconductor devices, of IEC TC 47, Semiconductor devices, was
submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 60191-6-17 on
2011-03-03.
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CEN and CENELEC shall not be held responsible for identifying any or all such patent
rights.
The following dates were fixed:
– latest date by which the EN has to be implemented
at national level by publication of an identical
national standard or by endorsement (dop) 2011-12-03
– latest date by which the national standards conflicting
with the EN have to be withdrawn (dow) 2014-03-03
Annex ZA has been added by CENELEC.
__________
Endorsement notice
The text of the International Standard IEC 60191-6-17:2011 was approved by CENELEC as a European
Standard without any modification.
__________
- 3 - EN 60191-6-17:2011
Annex ZA
(normative)
Normative references to international publications
with their corresponding European publications

The following referenced documents are indispensable for the application of this document. For dated
references, only the edition cited applies. For undated references, the latest edition of the referenced
document (including any amendments) applies.

NOTE  When an international publication has been modified by common modifications, indicated by (mod), the relevant EN/HD
applies.
Publication Year Title EN/HD Year

IEC 60191-6 - Mechanical standardization of semiconductor EN 60191-6 -
devices -
Part 6: General rules for the preparation of
outline drawings of surface mounted
semiconductor device packages
IEC 60191-6-5 - Mechanical standardization of semiconductor EN 60191-6-5 -
devices -
Part 6-5: General rules for the preparation of
outline drawings of surface mounted
semiconductor device packages - Design
guide for fine-pitch ball grid array (FBGA)

IEC 60191-6-17 ®
Edition 1.0 2011-01
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Mechanical standardization of semiconductor devices –
Part 6-17: General rules for the preparation of outline drawings of surface
mounted semiconductor device packages – Design guide for stacked packages –
Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)

Normalisation mécanique des dispositifs à semiconducteurs –
Partie 6-17: Règles générales pour la préparation des dessins d'encombrement
des dispositifs à semiconducteurs à montage en surface – Guide de conception
pour les boîtiers empilés – Boîtiers matriciels à billes et à pas fins et boîtiers
matriciels à zone de contact plate et à pas fins (P-PFBGA et P-PFLGA)

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX U
ICS 31.080.01 ISBN 978-2-88912-331-5

– 2 – 60191-6-17  IEC:2011
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative references . 6
3 Definitions . 6
4 Terminal position numbering . 7
5 Drawings . 8
6 Dimensions . 16
6.1 Group 1 . 16
6.2 Group 2 . 21
7 Dimension table . 27

Figure 1 – Individual stackable package, P-FBGA (cavity-up) . 8
Figure 2 – Individual stackable package, P-FBGA (cavity-down) . 9
Figure 3 – Individual stackable package, P-FLGA (cavity-up) . 10
Figure 4 – Stacked package outline, P-PFBGA (cavity-up BGA and cavity-up BGA) . 11
Figure 5 – Stacked package outline, P-PFBGA (cavity-down BGA and cavity-down
BGA) . 12
Figure 6 – Stacked package outline, P-PFBGA (cavity-down BGA + cavity-up LGA） . 13
Figure 7 – Stacked package outline, P-PFLGA (cavity-up LGA + cavity-up BGA) . 14
Figure 8 – Functional gauge . 15
Figure 9 – Pattern of terminal position area . 15

Table 1 – Dimensions, Group 1 . 16
Table 2 – Dimensions Group 2 . 21
Table 3 – Combination of D, E, M , and M , e = 0.80mm pitch FBGA and FLGA . 22
D E
Table 4 – Combination of D, E, M , and M , e = 0,65mm pitch FBGA and FLGA . 23
D E
Table 5 – Combination of D, E, M , and M , e = 0,50mm pitch FBGA and FLGA . 24
D E
Table 6 – Combination of D, E, M , and M , e = 0,40mm pitch FBGA an FLGA . 25
D E
Table 7 – Combination of D, E, M , and M , e = 0,30mm pitch FLGA. 26
D E
Table 8 – Dimension table . 27

60191-6-17  IEC:2011 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –

Part 6-17: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages –
Design guide for stacked packages –
Fine-pitch ball grid array and fine-pitch land grid array
(P-PFBGA and P-PFLGA)
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization
comprising all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and
non-governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates
closely with the International Organization for Standardization (ISO) in accordance with conditions determined
by agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated
in the latter.
5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any
services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60191-6-17 has been prepared by subcommittee 47D: Mechanical
standardization for semiconductor devices, of IEC technical committee 47: Semiconductor
devices.
The text of this standard is based on the following documents:
FDIS Report on voting
47D/785/FDIS 47D/793/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.

– 4 – 60191-6-17  IEC:2011
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all the parts in the IEC 60191 series, under the general title Mechanical
standardization of semiconductor devices, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
60191-6-17  IEC:2011 – 5 –
INTRODUCTION
The trend toward downsizing and higher density of portable electronic devices has driven LSI
packages into smaller and higher density configurations. The market demand of higher
density has led to the development of the package stacking technology that enabled
miniaturization and higher functionality. The objective of this design guide is to standardize
outlines and to get interchangeability of individual stackable packages.

– 6 – 60191-6-17  IEC:2011
MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –

Part 6-17: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages –
Design guide for stacked packages –
Fine-pitch ball grid array and fine-pitch land grid array
(P-PFBGA and P-PFLGA)
1 Scope
This part of IEC 60191 provides outline drawings and dimensions for stacked packages and
individual stackable packages in the form of FBGA or FLGA.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document applies.
IEC 60191-6, Mechanical standardization of semiconductor devices – Part 6: General rules
for the preparation of outline drawings of surface mounted semiconductor device package
IEC 60191-6-5, Mechanical standardization of semiconductor devices – Part 6-5: General
rules for the preparation of outline drawings of surface mounted semiconductor device
packages - Design guide for fine-pitch ball grid array (FBGA)
3 Terms and definitions
For the purposes of this document, the terms and definitions given i
...