EN 60749-29:2003

SLOVENSKI SIST EN 60749-29:2004

STANDARD
julij 2004
Semiconductor devices - Mechanical and climatic test methods - Part 29: Latch-up
test (IEC 60749-29:2003)
ICS 31.080.01 Referenčna številka
©  Standard je založil in izdal Slovenski inštitut za standardizacijo. Razmnoževanje ali kopiranje celote ali delov tega dokumenta ni dovoljeno

EUROPEAN STANDARD EN 60749-29
NORME EUROPÉENNE
EUROPÄISCHE NORM December 2003

ICS 31.080
English version
Semiconductor devices –
Mechanical and climatic test methods
Part 29: Latch-up test
(IEC 60749-29:2003)
Dispositifs à semiconducteurs –  Halbleiterbauelemente –
Méthodes d'essais mécaniques Mechanische und klimatische
et climatiques Prüfverfahren
Partie 29: Essai de verrouillage Teil 29: Latch-up-Prüfung
(CEI 60749-29:2003) (IEC 60749-29:2003)

This European Standard was approved by CENELEC on 2003-12-01. CENELEC members are bound to
comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European
Standard the status of a national standard without any alteration.

Up-to-date lists and bibliographical references concerning such national standards may be obtained on
application to the Central Secretariat or to any CENELEC member.

This European Standard exists in three official versions (English, French, German). A version in any other
language made by translation under the responsibility of a CENELEC member into its own language and
notified to the Central Secretariat has the same status as the official versions.

CENELEC members are the national electrotechnical committees of Austria, Belgium, Czech Republic,
Denmark, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Lithuania, Luxembourg, Malta,
Netherlands, Norway, Portugal, Slovakia, Spain, Sweden, Switzerland and United Kingdom.

CENELEC
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung

Central Secretariat: rue de Stassart 35, B - 1050 Brussels

© 2003 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.

Ref. No. EN 60749-29:2003 E
Foreword
The text of document 47/1713/FDIS, future edition 1 of IEC 60749-29, prepared by IEC TC 47,
Semiconductor devices, was submitted to the IEC-CENELEC parallel vote and was approved by
CENELEC as EN 60749-29 on 2003-12-01.
The following dates were fixed:
– latest date by which the EN has to be implemented
at national level by publication of an identical
national standard or by endorsement (dop) 2004-03-01
– latest date by which the national standards conflicting
with the EN have to be withdrawn (dow) 2006-12-01
__________
Endorsement notice
The text of the International Standard IEC 60749-29:2003 was approved by CENELEC as a European
Standard without any modification.
__________
NORME CEI
INTERNATIONALE IEC
60749-29
INTERNATIONAL
Première édition
STANDARD
First edition
2003-11
Dispositifs à semiconducteurs –
Méthodes d'essais mécaniques et climatiques –
Partie 29:
Essai de verrouillage
Semiconductor devices –
Mechanical and climatic test methods –
Part 29:
Latch-up test
© IEC 2003 Droits de reproduction réservés ⎯ Copyright - all rights reserved
Aucune partie de cette publication ne peut être reproduite ni No part of this publication may be reproduced or utilized in any
utilisée sous quelque forme que ce soit et par aucun procédé, form or by any means, electronic or mechanical, including
électronique ou mécanique, y compris la photocopie et les photocopying and microfilm, without permission in writing from
microfilms, sans l'accord écrit de l'éditeur. the publisher.
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Telephone: +41 22 919 02 11 Telefax: +41 22 919 03 00 E-mail: inmail@iec.ch  Web: www.iec.ch
CODE PRIX
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Commission Electrotechnique Internationale PRICE CODE
International Electrotechnical Commission
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Pour prix, voir catalogue en vigueur
For price, see current catalogue

60749-29 © IEC:2003 – 3 –
CONTENTS
FOREWORD . 5
1 Scope . 9
2 Definitions . 9
3 Apparatus and material.15
3.1 Latch-up tester .15
3.2 Automated test equipment (ATE) .19
3.3 Heat source .19
4 Procedure.19
4.1 General latch-up test procedure.19
4.2 Detailed latch-up test procedure .21
5 Failure criteria .25
6 Summary .25
Figure 1 – V qualification circuit .17
supply
Figure 2 – Trigger source qualification circuit .19
Figure 3 – Latch-up test flow .29
Figure 4 – Test waveform for positive I-test.31
Figure 5 – Test waveform for negative I-test .33
Figure 6 – Test waveform for V overvoltage .35
supply
Figure 7 – Equivalent circuit for positive input/output I-test latch-up testing.37
Figure 8 – Equivalent circuit for negative input/output I-test latch-up testing.39
Figure 9 – Equivalent circuit for V overvoltage test latch-up testing .41
supply
Table 1 – Test matrix .27
Table 2 — Timing specifications for I-test and V overvoltage test .35
supply
60749-29 © IEC:2003 – 5 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
___________
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –
Part 29: Latch-up test
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
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with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
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9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60749-29 has been prepared by IEC technical committee 47:
Semiconductor devices.
This standard cancels and replaces IEC/PAS 62181 published in 2000. This first edition
constitutes a technical revision.
The text of this standard is based on the following documents:
FDIS Report on voting
47/1713/FDIS 47/1724/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.

60749-29 © IEC:2003 – 7 –
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
The committee has decided that the contents of this publication will remain unchanged until
2007. At this date, the publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition, or
• amended.
60749-29 © IEC:2003 – 9 –
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –
Part 29: Latch-up test
1 Scope and object
This part of IEC 60749 covers the I-test and the overvoltage latch-up testing of integrated
circuits.
This test is classified as destructive.
The purpose of this test is to establish a method for determining integrated circuit (IC) latch-
up characteristics and to define latch-up failure criteria. Latch-up characteristics are used in
determining product reliability and minimizing "No Trouble Found" (NTF) and "Electrical
Overstress" (EOS) failures due to latch-up.
This test method is primarily applicable to CMOS devices. Applicability to other technologies
must be established.
In this part of IEC 60749 latch-up is not related to a specific mechanism but is an electrical
failure characteristic that occurs when a device is subjected to this test method.
The classification of latch-up as a function of temperature is defined in 2.1 and the failure
level criteria are defined in 2.10
2 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
2.1
classification
the classification defines the latch-up test temperature. Latch-up testing classifications are
defined as follows:
Class I – Latch-up testing performed at room temperature.
Class II – Latch-up testing performed at the maximum ambient rated temperature for the
device.
If no classification is specified, Class I testing shall be performed.
NOTE Elevated temperature will reduce latch-up resistance and Class II testing is recommended for devices that
are required to operate at elevated temperature.
2.2
cool-down time
period of time between successive applications of trigger pulses or the period of time between
the removal of the V voltage and the application of the next trigger pulse (See Figures 4,
supply
5, and 6 and Table 2.)
60749-29 © IEC:2003 – 11 –
2.3
DUT
device under test
2.4
GND (ground)
common or zero-potential pin(s) of the DUT
NOTE 1 Ground pins are not latch-up tested.
NOTE 2 A ground pin is sometimes called V .
ss
2.5
input pins
all address, data-in control, V and similar pins
ref
2.6
I/O (bi-directional) pins
device pins that can be made to operate as an input or output or in a high-impedance state
2.7
I
supply
total supply current in each V pin (or pin group) with the DUT biased as indicated in
supply
Table 1
2.8
I-test
latch-up test that supplies positive and negative current pulses to the pin under test
2.9
latch-up
state in which a low-impedance path resulting from an overstress that triggers a parasitic
thyristor structure, persists after removal or cessation of the triggering condition
NOTE 1 The overstress can be a voltage or current surge, an excessive rate of change of current or voltage, or
any other abnormal condition that causes the parasitic thyristor structure to become regenerative.
NOTE 2 Latch-up will not damage the device provided that the current through the low-impedance path is
sufficiently limited in magnitude or duration.
2.10
level
defines the failure criteria used during latch-up testing. Latch-up failure grades are defined as
follows:
Level A – The failure criteria as defined in Table 1
Level B – Special failure criteria. Supplier should provide definition of failure criteria used
2.11
logic-high
level within the more positive (less negative) of the two ranges of
...