HD 576 S1:1990

SLOVENSKI STANDARD
01-avgust-1997
IEC 60822 VSB – Vzporedni podsistem vodila IEC 60821 VMEbus
IEC 60822 VSB - Parallel sub-system Bus of the IEC 60821 VMEbus
IEC 60822 VSB - Parallel-Unterbussystem für den IEC 60821 VME-Bus
CEI 60822 VSB - Bus parallèle de sous-système de bus CEI 60821 VME bus
Ta slovenski standard je istoveten z: HD 576 S1:1990
ICS:
35.160 Mikroprocesorski sistemi Microprocessor systems
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

NORME CEI
INTERNATIONALE IEC
INTERNATIONAL
Première édition
STANDARD
First edition
1988-12
CEI 822 VSB
Bus parallèle de sous-système
du bus CEI 821 VMEbus
IEC 822 VSB
Parallel Sub-system Bus of the
IEC 821 VMEbus
© IEC 1988 Droits de reproduction réservés — Copyright - all rights reserved
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822 © IE C
CONTENTS
Page
FOREWORD 15
PREFACE 15
CHAPTER 0: SCOPE
CHAPTER 1: INTRODUCTION TO THE IEC 822 VSB BUS STANDARD
Section
1.1 Standard objectives of the IEC 822 VSB parallel Subsystem
Bus of the IEC 821 VMEbus (Subsystem henceforth referred to
as VSB) 19
1.2 VSB system elements 19
1.2.1 Basic definitions 19
1.2.1.1 Physical structure definition 19
1.2.1.2 Functional structure definition 21
1.2.1.3 Types of VSB cycles 25
1.3 VSB standard diagrams 31
1.4 Standard terminology 31
1.4.1 Signal line states 33
1.4.2 Use of the asterisk (*) 35
1.5 Protocol specification 35
CHAPTER 2: VSB DATA TRANSFER BUS
2.1 Introduction 39
2.2 Data Transfer Bus lines 41
2:2.1 Adressing lines 41
2.2.1.1 ADOO-AD31 41
2.2.1.2 SPACEO-SPACE1 43
2.2.1.3 SIZEO-SIZE1 43
2.2.1.4
ASACKO*-ASACK1* 43
2.2.1.5 GAO-GA2 45
2.2.2 Data lines ADOO-AD31 45
2.2.3 Control lines 45
' 2.2.3.1 PAS* 45
2.2.3.2 AC 47
WR* 2.2.3.3 47
2.2.3.4 LOCK* 47
2.2.3.5 DS* 47
2.2.3.6 WAIT* 47
2.2.3.7 ACK* 49
2.2.3.8 ERR* 49
2.2.3.9 IRQ* 49
2.2.3.10 CACHE* 51
2.3 DTB modules - Basic description 51
2.3.1 MASTER 53
2.3.2 SLAVE 55
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CI
Page
Section
Capabilities of MASTERS and SLAVES 57
2.4
61 2.4.1 Addressing capabilities
63 2.4.1.1 Basic addressing capabilities
65 2.4.1.2 ADDRESS-ONLY capability
67 2.4.2 Data transfer capabilities
67 2.4.2.1 Basic data transfer capability of MASTERS
2.4.2.2 Basic data transfer capabilities of SLAVES
71 2.4.2.3 Dynamic bus sizing
2.4.2.4 SINGLE-TRANSFER capability
2.4.2.5 BLOCK-TRANSFER capability 75
2.4.2.6 INDIVISIBLE-ACCESS capability
Interrupt capability 2.4.3
2.4.3.1 Basic interrupt capabilities of MASTERS and SLAVES
2.4.3.2 INTERRUPT-ACKNOWLEDGE cycle capabilities
91 2.5 Interaction between MASTERS and SLAVES
Interaction between MASTERS and SLAVES during address
2.5.1
broadcast phase
2.5.1.1 Flow of the address broadcast phase
99 2.5.1.2 Signaling during the address broadcast phase
Interaction between MASTERS and SLAVES during the data
2.5.2
transfer
107 2.5.2.1 Flow of a write data transfer
2.5.2.2 Flow of a read data transfer
2.5.2.3 Signaling during the data transfer phase
2.5.3 Interaction between MASTERS and SLAVES during cycle
termination
2.5.3.1 Flow of the termination of a cycle
2.5.4 Interaction between the IHV MASTER and SLAVES during
the INTERRUPT-ACKNOWLEDGE cycles
129 2.5.4.1 Flow of an INTERRUPT-ACKNOWLEDGE cycle
2.5.4.2 Signaling during the INTERRUPT-ACKNOWLEDGE cycle
2.6 Data transfer bus timing specifications
CHAPTER 3: VSB DATA TRANSFER BUS ARBITRATION
3.1 Introduction 189
3.1.1 Types of Arbitration
3.2 Arbitration Bus lines
3.2.1 BREQ*
3.2.2 BUSY*
3.2.3 BGIN*/BGOUT*
3.3 Arbitration modules - Basic description
3.3.1 ARBITER
3.3.2 REQUESTER
3.4 Capabilities of the REQUESTER 199
3.4.1 Serial Arbitration
3.4.1 1 Interaction between the ARBITER and SER REQUESTERS 203
3.4.1.2 Signaling during Serial Arbitration 209

822 © - T -
IEC
Section Page
3.4.2 Parallel Arbitration capability 213
3.4.2.1 Flow of an ARBITRATION cycle 213
3.4.2.2 Signaling during the ARBITRATION cycle 219
Power-up sequence 221
3.4.3
3.4.3.1 Flow of the power-up sequence 221
3.4.3.2 Interaction between arbitration bus modules during power-up
3.5 Interaction between the MASTER, its associated REQUESTER
and/or its associated ARBITER 229
3.5.1 Acquisition of the DTB
3.5.2 Release of the DTB 229
3.5.3 Race conditions between MASTER requests and ARBITER grants 231
3.6 Arbitration bus timing specifications 231
CHAPTER 4: ELECTRICAL CHARACTERISTICS OF VSB BOARDS
4.1 Introduction 253
4.1.1 Terminology 253
4.2 Power distribution
4.2.1 D.C. voltage characteristics 257
4.2.2 Connector electrical ratings 257
4.3 Bus driving and receiving requirements 257
4.3.1 General 257
4.3.2 Driving and loading RULES for three-state lines
(AD00-AD31, DS*, PAS*, LOCK*, SIZEO-SIZE1, SPACEO-SPACE1, WR*) 261
4.3.3 Driving and loading RULES for open-collector lines
(AC, ACK*, AD24-AD31, ASACKO*-ASACKI BREQ*, BUSY*, CACHE*,
ERR*, IRQ*, WAIT*) 265
4.3.4 Driving and loading RULES for BGIN* and BGOUT* 269
4.3.5 Receiving RULES for the geographical addressing lines
(GAO-GA2) 271
4.3.6 Additional information 271
4.4 Signal lines interconnection - Summary 273
CHAPTER 5: VSB BACKPLANE SPECIFICATIONS
5.1 Introduction 277
5.2 Backplane physical characteristics 277
5.3 Power distribution 281
5.4 Backplane electrical characteristics 281
5.4.1 Characteristic impedance 281
5.4.2 Termination networks 289
5.5 Signal line interconnection 293
5.5.1 General 293
5.5.2 BGIN*/BGOUT* daisy-chain 295
5.5.3 Geographical addressing 295
5.5.4 Additional information 297
5.6 VSB pin assignment
APPENDIX A 301
822©IEC - 9 -
Figure Page
1-1 Functional modules and sub-buses defined by the VSB standard 23
1-2 Signal timing notation 37
2-1 Data Transfer Bus functional block diagram 39
2-2 Block diagram: MASTER 53
2-3 Block diagram: SLAVE 55
2-4 General flow of a VSB cycle 59
2-5 General flow of an ADDRESS-ONLY cycle 65
2-6 Organization of data 67
2-7 General flow of a SINGLE-TRANSFER cycle 73
2-8 General flow of a BLOCK-TRANSFER cycle 77
2-9 General flow of an INTERRUPT-ACKNOWLEDGE cycle 87
2-10 Flow of the address broadcast phase 97
2-11 Flow of a write data transfer 111
2-12 Flow of a read data transfer 115
2-13 Flow of the termination of the cycle 127
2-14 Flow of an INTERRUPT-ACKNOWLEDGE cycle 133
2-15 Active MASTER, active IHV MASTER
and active PAR REQUESTER,
LOCK*, WR*, SIZEO-SIZE1 and SPACEO-SPACE1 timing,
SINGLE-TRANSFER,
BLOCK-TRANSFER,
INTERRUPT-ACKNOWLEDGE and
ARBITRATION cycles 147
2-16 Active MASTER and SLAVES,
address broadcast timing,
ADDRESS-ONLY,
SINGLE-TRANSFER and
BLOCK-TRANSFER cycles 149
2-17 Active MASTER and SLAVES, cycle termination
ADDRESS-ONLY cycles 151
2-18 Active MASTER and SLAVES,
write data transfer timing,
SINGLE-TRANSFER and
BLOCK-TRANSFER cycles 153
2-19 Active MASTER and SLAVES,
read data transfer timing,
SINGLE-TRANSFER,
BLOCK-TRANSFER and
INTERRUPT-ACKNOWLEDGE cycles 157
2-20 IHV MASTER and INTV SLAVES, selection phase INTERRUPT-
ACKNOWLEDGE cycles 161
2-21 MASTERS and SLAVES intercycle timing 163
2-22 DTB control transfer timing 165
2-23 Skew between ASACKO* and ASACK1* 167
2-24 Skew between ACK* and ERR* 167
3-1 Arbitration bus functional block diagram 189
3-2 Block diagram: ARBITER 195
3-3 Block diagram: SER REQUESTER 197
3-4 Block diagram: PAR REQUESTER 199
3-5 Serial Arbitration flow diagram: two REQUESTERS 205
3-6 General flow of an ARBITRATION cycle 213
3-7 Flow of an ARBITRATION cycle 217
3-8 Flow of the power-up sequence 225
3-9 Active PAR REQUESTER, contending PAR REQUESTER and idle SLAVE
ARBITRATION cycle 237
3-10 Power-up timing 239
822 © IEC - 11 -
Figure Page
4-1 VSB signal levels 259
5-1 VSB backplane dimensions 279
5-2 Cross-section of a backplane microstrip signal line 283
5-3 Z versus line width 285
5-4 Co versus line width 285
5-5 Standard bus termination 291
5-6 BGIN`/BGOUT* daisy-chain illustration 295
5-7 Geographical addressing lines resistor/capacitor circuit 295
Al Flow of the selection phase 303
A2 Selection phase control; a high level block diagram 305
A3 An example for the selection logic 307
Table
2-1 RULES and PERMISSIONS that specify the use of the dotted lines
by the various types of MASTERS 53
2-2 RULES and PERMISSIONS that specify the use of the dotted lines
by the various types of SLAVES 55
2-3 Mnemonics that specify addressing capabilities 63
2-4 Mnemonic that specifies ADDRESS-ONLY capability 65
2-5 Mnemonics that specify the basic data transfer capabilities
of SLAVES 69
2-6 Mnemonic that specifies BLOCK-TRANSFER capability 79
2-7 Mnemonics that specify interrupt capabilities 85
2-8 Mnemonics that specify STATUS/ID transfer capabilities
of IHV MASTERS and INTV SLAVES 91
2-9 Use of SPACED and SPACE1 to select the address space 99
2-10 Encoding of SIZED and SIZE1 for requested size of the transfer 101
2-11 Use of AD00 and ADO1 to select the lowest addressed byte
location to be accessed
2-12 Encoding of SIZEO, SIZE1, ADOO and ADO1 to define the byte
locations to be accessed 103
2-13 Encoding of ASACKO* and ASACK1* to define the size of the SLAVE 105
2-14 Placement of valid data on AD00-AD31 by the active MASTER
during write cycles 117
2-15 Use of ADOO-AD31 by a D32 SLAVE to access byte locations 119
2-16 Use of AD16-AD31 by a D16 SLAVE to access byte locations 121
2-17 Use of AD24-AD31 by a D08 SLAVE to access byte locations 121
2-18 Use of SPACED, SPACE1 and WR* to select an INTERRUPT-ACKNOWLEDGE
cycle 137
2-19 Use of the data lines by D08, D16 and D32 INTV SLAVES
during INTERRUPT-ACKNOWLEDGE cycles 139
2-20 Active MASTER, responding SLAVE, participating SLAVE and idle
SLAVE timing parameters 143
2-21 IHV MASTER, responding INTV SLAVE, contending INTV SLAVE and
idle SLAVE timing parameters 145
2-22 MASTER, timing specifications 169
2-23 SLAVE, timing specifications 179

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822 © IEC
Page
Table
RULES and PERMISSIONS that specify the use of the dotted lines
3-1
by the various types of SER REQUESTERS
Mnemonics that are used to describe REQUESTERS 3-2
Use of SPACEO-SPACE1 and WR* to select an ARBITRATION cycle
3-3
Active PAR REQUESTER, contending PAR REQUESTER and idle SLAVE
3-4
timing parameters
3-5 Power-up timing parameters
Active REQUESTER timing specifications 3-6
245 Contending REQUESTER timing specifications
3-7
249 3-8 Power-up timing specifications
Bus driving and receiving requirements
4-1
4-2 Signal line interconnection - Summary
281 5-1 Bus voltage specification
293 5-2 Signal line termination
Geographical addressing slot assignment 297
5-3
5-4 VSB pin assignment
822 © IEC -
15 -
INTERNATIONAL ELECTROTECHNICAL COMMISSION
IEC 822 VSB
PARALLEL SUB - SYSTEM BUS
OF THE IEC 821 VMEbus
FOREWORD
1) The formal decisions or agreements of the IEC on technical matters,
prepared by Technical Committees on which all the National Committees
having a special interest therein are represented, express, as nearly
as possible, an international consensus of opinion on the subjects
dealt with.
2) They have the form of recommendations for international use and they
are accepted by the National Committees in that sense.
3) In order to promote international unification, the IEC expresses the
wish that all National Committees should adopt the text of the IEC
recommendation for their national rules in so far as national
conditions will permit. Any divergence between the IEC recommendation
and the corresponding national rules should, as far as possible, be
clearly indicated in the latter.
4) The IEC has not laid down any procedure concerning marking as an
indication of approval and has no responsibility when an item of
equipment is declared to comply with one of its recommendations.
PREFACE
This standard has been prepared by Sub-Committee 47B: Microprocessor
Systems, of IEC Technical Committee No. 47: Semiconductor Devices.
The text of this standard is based on the following documents:
Six Months' Rule Report on Voting
47B(CO)22 478(C0)27
Further information can be found in the Report on Voting indicated in
the table above.
The following IEC publications are quoted in this standard:
Publications Nos. 603-2 (1980): Connectors for frequencies below 3 MHz
for use with printed boards, Part 2:
Two-part connectors for printed boards,
for basic grid of 2.54 mm (0.1 in) with
common mounting features.
821 (1987): IEC 821 BUS - Microprocessor system bus
for 1 to 4 byte data.
822 © IEC - 17 -
IEC 822 VSB
PARALLEL SUB - SYSTEM BUS
OF THE IEC 821 VMEbus
CHAPTER 0: SCOPE
The introduction of high performance of 32-bit microprocessors, as
well as the demands placed on microcomputers by the user community
have created a need for multiprocessor systems built from board level
products. The increase in the number of functions that such systems
provided necessitated the introduction of a sophisticated subsystem
bus. The VSB (VME Subsystem Bus) was designed to respond to these
requirements.
It includes a high speed asynchronous data transfer bus which
allows masters to direct the transfer of binary data to and from
slaves. The master initiates bus cycles in order to transfer data
between itself and slaves. The slave detects bus cycles that are
initiated by the active master and, when those cycles select it,
transfers data between itself and the master.
Four types of cycles are defined: an address-only cycle, a single
transfer cycle, a block transfer cycle, and an interrupt acknowledge
cycle. To maximize data transfer rates in multiprocessor systems, the
VSB standard defines a mechanism that allows the master to broadcast
the data to any number of slaves in the course of a single cycle. In
addition, the data transfer mechanism supports dynamic bus sizing as
well as resource locking and data caching.
The arbitration bus is the second of the two sub-buses defined in
the VSB standard. It allows arbiter modules and/or- requester modules
to coordinate the use of the data transfer bus. Two arbitration
methods are defined - a serial arbitration method and a parallel
(distributed) arbitration method. These arbitration methods provide
protocols to implement an array of subsystem architectures. Using the
serial arbitration method, a designer can implement a single master
subsystem that includes a single processor board requiring access to
large amounts of memory. This method could be used to build a system
that gives priority to a primary master that, when it can, grants the
bus to other secondary masters. At the other end of the spectrum, a
multiprocessing subsystem can be implemented using the parallel
arbitration method.
822 © IEC - 19 - (1-1)
CHAPTER 1: INTRODUCTION TO THE IEC 822 VSB BUS STANDARD
1.1 Standard objectives of the IEC 822 VSB parallel Subsystem Bus
of the IEC 821 VMEbus (Subsystem henceforth referred to as VSB)
This VSB bus is a local subsystem extension bus. It allows a
processor board to access additional memory and I/O over a local bus,
removing traffic from the global bus and improving the total through-
put of the system. The system has been conceived with the following
objectives:
a) To improve the performance of multiprocessor systems by allowing
the design of local subsystems.
b) To specify the electrical characteristics required to design boards
that will reliably transfer data over the VSB.
c) To specify the mechanical requirements to be compatible with VSB
systems.
d) To specify protocols that precisely define the interaction between
the VSB and devices interfaced to it.
e) To provide terminology and definitions that describe VSB
protocols.
1.2 VSB system elements
1.2.1 Basic definitions
The structure of the VSB can be described from two points of view:
its mechanical structure and its functional structure.
Because the primary use of the VSB is as a secondary bus, there
are no mechanical specifications of VSB board level, and/or box level
products. It is assumed that products that include the VSB have been
designed to comply with the mechanical specifications of the global
system bus. Therefore, the VSB standard only describes the physical
dimensions of the backplane.
The functional specifications of the VSB describe how the bus
works, what functional modules participate in its various operations,
and the rules that govern their behavior. This paragraph provides
in.formal definitions for the basic terms used to describe both the
mechanical and functional structure of the VSB.
1.2.1.1 Physical structure definition
BOARD
A printed circuit (PC) board, its collection of electronic components,
and at least one 96-pin connector.

(1-2)
IEC - 21 - 822 ©
VSB BACKPLANE
An assembly that includes a printed circuit (PC) board and 96-pin
connectors. The backplane buses the 64 pins on the two outer rows of
the VSB connectors, providing the signal paths needed for VSB
operation.
SLOT
A position where a board can be inserted into a backplane. Each
VSB slot provides at least one 96-pin connector.
SUBRACK
A rigid framework that provides mechanical support for boards
inserted into the backplane, ensuring that the connectors mate
properly and that adjacent boards do not contact each other. It also
guides the cooling airflow through the system, and ensures that
inserted boards are not disengaged from the backplane due to
vibration.
Functional structure definition
1.2.1.2
Figure 1-1, page 23, shows a block diagram of the functional
modules and sub-buses defined by the VSB standard.
BACKPLANE INTERFACE LOGIC
Special interface logic that takes into account the characteristics of
the backplane. The VSB standard prescribes certain requirements for
the design of this logic, which take into account the signal line
impedance, propagation times, termination values, the maximum length
of the backplane and the number of slots allowed.
FUNCTIONAL MODULE
A collection of electronic circuitry that resides on one board and
works to accomplish a specific task. Functional modules are used as a
vehicle for discussing bus protocols, and should not be considered to
constrain the design of actual logic.
DATA TRANSFER BUS
One of the two sub-buses defined in the VSB standard. It allows
MASTERS to direct the transfer of binary data to and from SLAVES.
(The VSB Data Transfer Bus is often abbreviated DTB.) The DTB
contains 32 multiplexed address/data lines and the associated control
signals that are required to execute cycles on the VSB.
MASTER
A functional module that initiates bus cycles in order to transfer
data between itself and VSB SLAVES. The MASTER that is currently
in control of the DTB is referred to as the active MASTER.
SLAVE
module that detects bus cycles initiated by the active
A functional
MASTER and, when those cycles select it, transfers data between itself
and the MASTER. The VSB standard defines a mechanism through
which any number of SLAVES can participate in a bus cycle.

822 © IEC - 23 - (1-3)
SELECTED SLAVE
All SLAVES that are selected by the cycle.
RESPONDING SLAVE
The one selected SLAVE which responds to the active MASTER by
acknowledging the data transfer of the STATUS/ID transfer.
PARTICIPATING SLAVE
Selected SLAVE which chooses to participate in the cycle by
capturing the data carried on the data lines.
IDLE SLAVE
SLAVE which is not selected by the cycle.
CONTENDING SLAVE
SLAVE that has an interrupt request pending and that participates
in an INTERRUPT-ACKNOWLEDGE cycle.
LOCATED IN DATA PROCESSING/ DATA
SLOT 1 DATA COMMUNICATION
STORAGE
DEVICE DEVICE
ARBITER MASTER REQUESTER SLAVE
t
BUS BUS BUS
BUS
INTERFACE INTERFACE INTERFACE INTERFACE
LOGIC LOGIC LOGIC
LOGIC
• ^
DATA TRANSFER BUS
ARBITRATION BUS
VSB BACKPLANE
879/88
Fig. 1-1. Functional modules and sub-buses
defined by the VSB standard.
VSB ARBITRATION BUS
The second of the two sub-buses defined in the VSB standard. It
allows ARBITER modules and/or REQUESTER modules to coordinate the
use of the DTB by VSB MASTERS. The VSB defines two arbitration
methods - a Serial arbitration method and a Parallel arbitration method.

822 © IEC - 25 - (1-4)
REQUESTER
A functional module that resides on the same board as a MASTER
and requests use of the DTB whenever its MASTER needs it. When
implementing Serial arbitration, after requesting use of the DTB, the
REQUESTER waits for the bus to be granted to it by the ARBITER.
In the Parallel arbitration method, the REQUESTER that is associated
with the active MASTER initiates an ARBITRATION cycle. This
ARBITRATION cycle is used to determine which MASTER will be
granted use of the DTB. The VSB standard calls the REQUESTER that
is associated with the active MASTER the active REQUESTER.
CONTENDING REQUESTER
REQUESTER that has a bus request pending and that participates in
an ARBITRATION cycle.
ARBITER
When implementing the Serial arbitration method, the ARBITER
module accepts requests for the DTB from REQUESTERS and grants
control of the DTB to one REQUESTER at a time. There is one and
only one active ARBITER in the Serial arbitration scheme, and it is
always located in slot 1. An ARBITER is not required in the Parallel
arbitration method.
DAISY CHAIN
A special type of signal line that is used to propagate bus grants
from board to board, starting with the board installed in the first slot
and ending with the one installed in the last slot.
GEOGRAPHICAL ADDRESSING
A scheme wherein each slot in the backplane is assigned a unique
address. This address can be read by the board that is installed in"
the slot. The VSB standard defines the use of the geographical
address for two purposes: (1) it forms part of the INTERRUPT ID
used during an INTERRUPT-ACKNOWLEDGE cycle and, (2) it forms
part of the ARBITRATION ID used during a Parallel ARBITRATION
cycle. The geographical address can also be used to set global board
variables such as the base address of a memory board.
1 .2.1 .3 Types of VSB cycles
VSB BUS CYCLE
A sequence of level transitions on the signal lines of the DTB that
results in the transfer of an address and (in most cases) data between
the active MASTER and selected SLAVES. The protocols of the VSB
are fully asynchronous. The active MASTER asserts a strobe signal
indicating that a cycle is in progress. The responding SLAVE acknow-
ledges the MASTER'S signal. However, the responding SLAVE can
delay its acknowledgment for as long as it needs. The DTB cycle is
generally divided into three phases: an address broadcast, zero or
more data transfers, and then cycle termination.

822 © IEC - 27 - (1 -5)
ADDRESS BROADCAST
The phase of a bus cycle which selects one SLAVE as the responding
SLAVE and zero or more SLAVES as participating SLAVES. During the
address broadcast the active MASTER broadcasts the addressing
information and then asserts an address strobe. After the SLAVES
acknowledge the address broadcast, the MASTER terminates the
address broadcast.
DATA TRANSFER
The phase of a cycle during which data is transferred between the
MASTER and the selected SLAVES. It starts when the active MASTER
asserts the data strobe and ends after the responding SLAVE acknow-
ledges the transfer and all participating SLAVES indicate that they are
ready to participate in a new cycle.
CYCLE TERMINATION
The phase of a cycle during which the MASTER terminates the cycle
and SLAVES acknowledge this termination by establishing the inter-
cycle state of bus signals.
DYNAMIC BUS SIZING
The ability of some microprocessors to adjust the number and the
size of data transfers to the amount of data that the responding board
can access in one transfer. During the address broadcast portion of
the cycle, the SLAVE informs the MASTER how many data lines it
actually drives or receives. This information is made available to
on-board logic which can then adjust the amount of data that it
accesses during the data transfer to the capabilities of the SLAVE.
DATA BROADCAST
A broadcast operation is one wherein participating SLAVES capture
the data that is placed on the data lines by the active MASTER during
a write cycle.
DATA BROADCALL
A broadcall operation is one wherein participating SLAVES capture
the data that is placed on the data lines by the responding SLAVE
during a read cycle.
SINGLE-TRANSFER READ CYCLE
A cycle that is used to transfer 1, 2, 3, or 4 bytes from the res-
ponding SLAVE to the active MASTER, and possibly to participating
SLAVES. The cycle begins when the active MASTER broadcasts the
addressing information on the address/data lines. Each SLAVE checks
the address to see if it is to respond to the cycle. If so, it acknow-
ledges the address and retrieves the data from its internal storage.
When the MASTER releases the address/data lines, the responding
SLAVE places its data on them and acknowledges the transfer. The
MASTER as well as participating SLAVES capture the data. After all
selected SLAVES signal their agreement the MASTER terminates the
cycle.
822 © IEC - 29 - (1 -6)
SINGLE-TRANSFER WRITE CYCLE
A cycle that is used to transfer 1, 2, 3, or 4 bytes from the active
MASTER to the selected SLAVES. The cycle begins when the MASTER
broadcasts the addressing information on the address/data lines. Each
SLAVE checks the address to see if it is to participate in the cycle.
The responding SLAVE acknowledges the address broadcast. The
MASTER then switches the address/data lines to carry data, and
places its data on the bus. The selected SLAVES can then store the
data. The responding SLAVE acknowledges the transfer. After all
selected SLAVES signal their agreement the MASTER terminates the
cycle.
BLOCK-TRANSFER READ CYCLE
A DTB cycle that is used to transfer a block of bytes from the
responding SLAVE to the active MASTER, and possibly to participating
SLAVES. This transfer is done using a number of 1, 2, or 4-byte data
transfers. It differs from a series of SINGLE-TRANSFER read cycles in
that the MASTER broadcasts the address only once, at the beginning
of the cycle. It is the responsibility of the selected SLAVES to control
the address for each subsequent data transfer.
BLOCK-TRANSFER WRITE CYCLE
A DTB cycle that is used to transfer a block of bytes from the
active MASTER to the selected SLAVES. This transfer is done using a
series of 1, 2, or 4-byte data transfers. It differs from a series of
SINGLE-TRANSFER write cycles in that the MASTER broadcasts the
address only once, at the beginning of the cycle. It is the respons-
ibility of the selected SLAVES to control the address for each sub-
sequent data transfer.
INDIVISIBLE-ACCESS CYCLE
A DTB cycle that is used to access SLAVE locations indivisibly and
without permitting any other MASTER to access these locations until
the operation is complete.
ADDRESS-ONLY CYCLE
A DTB cycle that consists of an address broadcast, but no data
transfer. The active MASTER terminates the cycle after the SLAVES
acknowledge the address broadcast.
INTERRUPT-ACKNOWLEDGE CYCLE
A DTB cycle that is initiated by a MASTER in response to an inter-
rupt request from a SLAVE. An INTERRUPT-ACKNOWLEDGE cycle
involves two types of SLAVES. During the INTERRUPT-ACKNOWLEDGE
cycle, all contending SLAVES drive an INTERRUPT ID on the bus.
This ID is a combination of the geographical address of the board that
is supplied by the backplane slot, and a priority code that is supplied
by user defined on-board logic. The INTERRUPT ID is used to deter-
mine which of the contending SLAVES will respond to the cycle.

822 © IEC - 31 - (1-7)
ARBITRATION CYCLE
A cycle that is initiated by the active REQUESTER in response to a
bus request, after its associated active MASTER no longer needs the
bus. This cycle is used to select the MASTER that will be granted use
of the DTB. If the active REQUESTER detects a request for the bus,
and if its associated MASTER no longer needs the bus, it initiates an
ARBITRATION cycle. During the ARBITRATION cycle, all contending
REQUESTERS drive an ARBITRATION ID on the bus. This ID is a
combination of the geographical address of the board that is supplied
by the backplane slot, and a priority code that is supplied by user
defined on-board logic. At the end of the. ARBITRATION cycle one of
the contending REQUESTERS becomes the active REQUESTER.
1 .3 VSB standard diagrams
Three types of diagrams are used to help define and describe the
operation of the VSB:
a) Block diagrams show the signal line interconnect requirements of
the functional modules defined by the VSB standard.
b)
Flow diagrams show the stream of events as they would occur
during a VSB operation. The events are stated in words and
sequentially describe the interaction between two or more
functional modules. The VSB standard describes in detail the
behavior of the various functional modules. It discusses how a
module responds to a signal without saying where the signal came
from. Because of this, a protocol specification does not give the
reader a complete picture of what happens over the bus. Flow
diagrams are used to help the reader overcome this difficulty.
c)
Timing diagrams show the timing relationships between signal
transitions. The timing parameters have minimum and/or maximum
limits associated with them. Some of these timing parameters
specify the behavior of the backplane interface logic, while others
specify the behavior of the functional modules.
1.4
Standard terminology
To avoid confusion, and to make very clear what the requirements
for compliance are, many of the paragraphs in this standard are
labeled with sequentially numbered keywords that indicate the type of
information they contain. The keywords are:
RULE
RECOMMENDATION
SUGGESTION
PERMISSION
OBSERVATION
- 33 - (1-8)
822 © IEC
RULE chapter.number:
Rules form the basic framework of the VSB standard. They are
sometimes expressed in text form and sometimes in the form of figures
or tables. Rules are characterized by an imperative style. The upper
case words MUST and MUST NOT are reserved for stating rules in this
standard and are not used for any other purpose.
RECOMMENDATION chapter.number:
Wherever a recommendation appears, designers would be wise to take
the advice given. Doing otherwise might result in some awkward
problem or poor performance. While the VSB has been designed to
support high performance systems, it is possible to design a VSB
system that complies with all the rules, but has poor performance. In
many cases, a designer needs a certain level of experience with VSB
in order to design boards that deliver top performance. Recommend-
ations found in this standard are based on this kind of experience,
and are provided to designers to speed their traversal of the learning
curve.
SUGGESTION chapter. number:
A suggestion in the VSB standard contains advice which is helpful
but not vital. The reader is encouraged to consider the advice before
discarding it. Some decisions made while designing VSB boards are
difficult until experience has been gained with the VSB. Suggestions
are included to help a designer who has not yet gained this
experience. Some suggestions have to do with- designing boards that
can be easily reconfigured for operation with other boa_ rds, or with
designing boards that are easier to debug.
PERMISSION chapter. number:
In some cases a VSB rule does not specifically prohibit a certain
design approach. However, the reader might be left wondering whether
that approach violates the spirit of the rule, or whether it might lead
to some subtle problem. Permissions reassure the reader that a certain
approach is acceptable, and will cause no problems. The upper case
word MAY is reserved for stating permissions in this standard and is
not used for any other purpose.
OBSERVATION chapter.number:
Observations do not offer any specific advice. They usually follow
naturally from what has just been discussed. They spell out the
implications of certain VSB requirements and bring attention to things
that might otherwise be overlooked. They also give the rationale
behind certain requirements, so that the reader understands why they
are needed.
1.4.1 Signal line states
The protocols of the VSB are described in terms of levels and trans-
itions on bus lines. A signal line is always assumed to be in one of
two levels, high or low, or in transition between these two levels.

822 © IEC
- 35 - (1 -9)
On level significant signal lines, the TTL voltage level represents
meaningful information. Signal lines that are described as level signi-
ficant can be either high or low. Whenever the term high is used, it
refers to a high TTL voltage level. The term low refers to a low TTL
voltage level.
Edge significant signal lines mark an event when they make a trans-
ition between the two TTL voltage levels. There are two possible
transitions which can appear on a signal line. A rising edge is the
time during which a signal makes its transition from a low level to a
high level. The falling edge is the time during which a signal makes
its transition from a high level to a low level.
The rise and fall times of bus drivers are the result of a complex
set of interactions involving the impedance of the backplane's signal
lines, the terminations and length of the signal lines, the source
impedance of the drivers, and the capacitive loading of the signal
lines. The VSB standard does not specify rise and fall times. Instead,
it specifies the electrical characteristics for drivers and receivers. It
also specifies all signal timing requirements, taking into account the
worst case bus loading and the effect it has on the propagation delay
times of these drivers. If VSB designers follow these timing require-
ments, then their boards will operate reliably with other VSB compa-
tible boards under worst case conditions.
1.4.2 Use of the asterisk (*)
Some signal names have an asterisk suffix (*) to help define their
usage. The meaning of the asterisk is as follows:
a) An asterisk (*) following the name of a signal which is level
significant denotes that the signal is true or valid when the signal
is low.
b) An asterisk (*) following the name of a signal which is edge
significant denotes that the falling edge is of greater significance
in the protocol than is the rising edge.
1.5 Protocol specification
The primary protocol used in the VSB system is a closed loop
protocol on interlocked bus lines. Each interlocked signal has a source
module and one or more destination modules. It is sent from a specific
module and is acknowledged by the receiving module(s) . An inter-
locked relationship exists between the sending and the receiving
modules until the signal is properly acknowledged. For example, a
MASTER asserts the data strobe which is handshaked later with an
acknowledge signal (no time limit is prescribed by the VSB standard) .
The MASTER does not remove the data strobe until all SLAVES have
acknowledged the data transfer.

(1-10)
822 © IEC - 37 -
The signal lines used on the VSB may be driven by different
modules at different times. They are driven with drivers that can be
turned on and off at each board. It is very important that their
turn-on and turn-off times be carefully controlled to prevent two
drivers from attempting to drive the same signal line to different
levels. A special notation in the timing diagrams is used to specify
their turn-on and turn-off times. It is shown in Figure 1-2.
NOT DRIVEN
OR DRIVEN
NOT
NOT
DRIVEN AND
DRIVEN
DRIVEN
BUT STABLE
NOT STABLE
FALLING RISING
EDGE EDGE
DRIVEN DRIVEN DRIVEN NOT
NOT
HIGH LOW HIGH DRIVEN
DRIVEN
202/87
Fig. 1-2. - Signal timing notation.

822 © IEC - 39 - (2-1)
CHAPTER 2: VSB DATA TRANSFER BUS
2.1 Introduction
The VSB includes a high speed asynchronous multiplexed Data
Transfer Bus (DTB) . Figure 2-1 shows a typical VSB system including
all the functional modules of the DTB. MASTERS use the DTB to select
byte locations provided by SLAVES and to transfer data to or from
those locations. Some MASTERS and SLAVES use all of the DTB lines,
while others use only a subset.
After a MASTER initiates a data transfer cycle, it waits for the
responding SLAVE to acknowledge the transfer before finishing the
cycle. The asynchronous transfer protocols of the VSB allow a SLAVE
to take as long as it needs to respond.
Fig. 2-1. Data Transfer Bus functional block diagram.

822 © IEC - 41 - (2-2)
2.2 Data Transfer Bus lines
The VSB Data Transfer Bus lines can be grouped into three
categories:
a) Addressing lines: ADOO-AD31 - Address/Data
SPACEO - SPACE select 0
SPACE1 - SPACE select 1
SIZEO - SIZE request 0
SIZE1 - SIZE request 1
ASACKO* - Address/Size ACKnowledge 0
ASACK1* - Address/Size ACKnowledge 1
GAO-GA2 - Geographical Addressing
-
b) Data lines: AD00-AD31 Address/Data
c) Control lines: PAS* - Physical Address Strobe
AC - Address decode Complete
WR*
- WRite
-
LOCK* LOCK
WAIT* - WAIT
ASACKO* - Address/Size ACKnowledge 0
ASACK1* Address/Size ACKnowledge 1
DS* - Data Strobe
ACK* - data ACKnowledge
ERR* - data ERRor
IRQ* - Interrupt ReQuest
-
CACHE* CACHEable
This section provides a general description of the Data Transfer Bus
lines to familiarize the reader with their function. The function of some
of the lines might vary during INTERRUPT-ACKNOWLEDGE cycles,
described in Paragraph 2.5.4. In addition, some of the DTB lines are
used in the parallel arbitration method, as described in Chapter 3.
2.2.1 Addressing lines
The active MASTER drives the addressing lines during the address
broadcast phase of the cycle to select the SLAVE that will respond to,
as well as SLAVES that will participate in, the data transfer phase.
2.2.1.1 ADOO-AD31
During the address broadcast phase of a cycle, the active MASTER
drives address lines AD00-AD31 with the address of the byte
location(s) that are to be accessed during the data transfer phase of
the cycle.
The address of a 4-byte group is determined by the level of address
lines AD02-AD31. The address of byte locations within a 4-byte group
differs only by the level of the two least significant bits of the
address lines, i.e., address lines AD00 and AD01. Byte Locations are
categorized as BYTE(0), BYTE(1), BYTE(2) and BYTE(3) according to
the state of AD00 and AD01 in their address, as defined in Para-
graph 2.5.1.2, Table 2-11.
- 43 - (2-3)
822 © IEC
OBSERVATION 2.1:
When access to more than one byte location is requested in a cycle,
the address on address lines AD00-AD31 is the lowest among the
addresses of the byte locations.
2.2.1.2 SPACEO-SPACE1
The active MASTER drives SPACED and SPACE1 with a space code.
It is used to select one of three address spaces, or to initiate an
INTERRUPT-ACKNOWLEDGE or an ARBITRATION cycle. The VSB
defines three separate address spaces of 4 Gbyte each. These three
address spaces are the System Address Space, the I/O Address Space
and the Alternate Address Space.
2.2.1.3 SIZEO-SIZE1
During the address broadcast phase, the active MASTER drives
SIZEO-SIZE1 with a size code. This size code indicates the number of
byte location(s) that the MASTER wishes to access during the data
transfer phase. The VSB standard defines four sizes of data transfer:
Single-Byte, Double-Byte, Triple-Byte and Quad-Byte.
During Single-Byte transfers, the MASTER requests access to one
byte location.
the MASTER requests access to two
During Double-Byte transfers,
consecutive byte locations.
the MASTER requests access to three
During Triple-Byte transfers,
consecutive byte locations.
During Quad-Byte transfers, the MASTER requests access to four
consecutive byte locations.
2.2.1.4 ASACKO *-ASACK1*
ASACKO* and ASACK1* serve a dual function:
The responding SLAVE drives its size code on these lines. This
a)
SLAVE size code informs the active MASTER what is the maximum
number of byte locations that the responding SLAVE can access in
a single transfer. The VSB standard defines three SLAVE sizes:
Single-Byte, Double-Byte and Quad-Byte SLAVES.
A Single-Byte SLAVE responds to data transfer requests by
accessing only one byte location during each data transfer.
A Double-Byte SLAVE responds to data transfer requests by
accessing either one or two byte locations during each data
transfer.
A Quad-Byte SLAVE responds to data transfer requests by
accessing either one, two, three or four byte locations during each
data transfer.
822 © I EC - 45 - (2-4)
b) The first falling edge of either ASACKO* or ASACK1* informs the
active MASTER that the responding SLAVE has finished decoding
the address and that it is ready to start the data transfer phase.
2.2.1.5 GAO-GA2
In the VSB system, each slot in the backplane is assigned a unique
address. This address is set by the voltage levels on GAO-GA2. When
the board is installed in the backplane slot, it uses the levels of
GAO-GA2 to set part of the INTERRUPT ID that it uses during
INTERRUPT-ACKNOWLEDGE cycles. (In addition, as described in
Chapter 3, GAO-GA2 set part of the ARBITRATION ID used during
parallel ARBITRATION cycles.) Chapter 5, Paragraph 5.5.3,
describes how the voltage levels of the geographical addressing bits in
each slot are set.
2.2.2 Data lines AD00-AD31
Data lines ADOO-AD31 are used to carry the data between the active
MASTER and VSB SLAVES. During read cycles, the responding SLAVE
retrieves data from its internal storage and drives it on the data lines,
and the active MASTER captures the data from data lines ADOO-AD31.
During write cycles, the active MASTER drives data lines AD00-AD31
with valid data. The responding SLAVE captures this data and stores
it in its internal storage. Participating SLAVES might also capture the
data transferred during read or write cycles.
2.2.3 Control lines
The control lines coordinate the transfer of the addressing inform-
ation from the active MASTER to VSB SLAVES and of the data between
the active MASTER and the selected SLAVES.
2.2.3.1 PAS*
The active MASTER drives PAS* low to start the
...