CLC/SS V24 - Information technology equipment and audio, video and audio-visual equipment and systems

Describes a high-performance backplane bus for use in microprocessor bases systems. This parallel bus supports single- and block-transfer cycles on a 32-bit non-multiplexed address and data highway. Transmission is governed by an asynchronous handshaken protocol. The bus allocation provides for multiprocessor architectures. This bus also supports inter-module interrupts for facilitating quick response to internal and external events. The mechanics of the boards and chassis are based on EN 60297. Note: -1.This bus is similar to the VME bus. 2.For the price of this publication, please consult the ISO/IEC price-code list.

Applies to interface system components, for use in interconnecting data processing, data storage, and peripheral control devices in a closely coupled configuration. This interface system contains the necessary signals to allow the various system components to interact with each other. lt allows memory and Input/Output direct memory accesses, generation of interrupts, etc. Provides a detailed description of all the elements and features that make up the system bus.

The VSB bus was designed to meet the needs of multiprocessor systems based on high-performance 32-bit microprocessors built up from board assemblies. lt includes a high-speed asynchronous data transfer bus allowing masters to direct the transfer of binary data to and from slaves according to 4 kinds of cycles: address-only, single-transfer, block-transfer and interrupt-acknowledge cycles. It also includes an arbitration bus enabling arbiter modules and/or requester modules to coordinate the use of the data-transfer bus according to two arbitration methods (series or parallel).

Defines ways for new microprocessor systems to perform binary floating point arithmetic in software, in hardware or in any combination of hardware and software. Note: -For the price of this publication, please consult the ISO/IEC price-code list.