EN 60191-3:1999

SLOVENSKI STANDARD
01-september-2002
Mechanical standardization of semiconductor devices - Part 3: General rules for
the preparation of outline drawings of integrated circuits (IEC 60191-3:1999)
Mechanical standardization of semiconductor devices -- Part 3: General rules for the
preparation of outline drawings of integrated circuits
Mechanische Normung von Halbleiterbauelementen -- Teil 3: Allgemeine Regeln für die
Erstellung von Gehäusezeichnungen für integrierte Schaltungen
Normalisation mécanique des dispositifs à semiconducteurs -- Partie 3: Règles
générales pour la préparation des dessins d'encombrement des circuits intégrés
Ta slovenski standard je istoveten z: EN 60191-3:1999
ICS:
01.100.25 5LVEHVSRGURþMD Electrical and electronics
HOHNWURWHKQLNHLQHOHNWURQLNH engineering drawings
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
31.240 Mehanske konstrukcije za Mechanical structures for
elektronsko opremo electronic equipment
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

NORME CEI
INTERNATIONALE IEC
60191-3
INTERNATIONAL
Deuxième édition
STANDARD
Second edition
1999-10
Normalisation mécanique des dispositifs
à semiconducteurs –
Partie 3:
Règles générales pour la préparation
des dessins d'encombrement des circuits intégrés
Mechanical standardization of
semiconductor devices –
Part 3:
General rules for the preparation of outline
drawings of integrated circuits
 IEC 1999 Droits de reproduction réservés  Copyright - all rights reserved
Aucune partie de cette publication ne peut être reproduite ni No part of this publication may be reproduced or utilized in
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électronique ou mécanique, y compris la photo-copie et les including photocopying and microfilm, without permission in
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CODE PRIX
Commission Electrotechnique Internationale
XA
PRICE CODE
International Electrotechnical Commission
Pour prix, voir catalogue en vigueur
For price, see current catalogue

60191-3 © IEC:1999 – 3 –
CONTENTS
Page
FOREWORD . 5
Clause
1 General. 9
2 Terminology and definitions. 9
3 Cross-referencing of packages . 15
4 Terminal identification – Numbering of terminals. 15
5 Dimensions and reference letter symbols. 21
6 Drawing layout . 31
7 Dimensioning and tolerances. 31
8 Inter-conversion of inch and millimetre dimensions, and rules for rounding-off . 31
9 Definition of families. 31
10 Examples of drawings . 33
11 Design procedure for dimensions of integrated circuit packages . 33
12 Rules for mounting integrated circuit packages into carriers. 33
13 Bending of terminals of QUIL packages . 37
14 Pin grid arrays. 41
15 Rule for orientation of integrated circuit packages in handling and
shipping carriers such as stick magazines and rails . 41
Annex A (normative) Limits applicable for the dimensions of integrated circuit
package outlines . 43
Annex B (informative) Example drawings showing cross-referencing of packages,
utilization of reference letter symbols, terminal identification and index area. 49
Annex C (normative) Terminal identification and numbering of terminals of devices with
terminals disposed in three or more rows in each orthogonal direction. 81
Annex D (normative) Recommended dimensions of integrated circuit packages
of form G family. 85
Annex E (normative) General rules for the preparation of outline drawings of packages
of form G intended for automated handling . 87
Annex F (normative) General rules for the preparation of outline drawings
of pin grid arrays . 95
Annex G (normative) Rule for orientation of integrated circuit packages in handling
and shipping carriers such as stick magazines and rails. 103
Annex H (normative) Bottom view method for terminal No. 1 recognition . 107
Annex K (normative) Gate burrs, mold flash and protrusions . 113

60191-3 © IEC:1999 – 5 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
___________
MECHANICAL STANDARDIZATION OF
SEMICONDUCTOR DEVICES –
Part 3: General rules for the preparation of outline drawings
of integrated circuits
FOREWORD
1) The IEC (International Electrotechnical Commission) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, the IEC publishes International Standards. Their preparation is
entrusted to technical committees; any IEC National Committee interested in the subject dealt with may
participate in this preparatory work. International, governmental and non-governmental organizations liaising
with the IEC also participate in this preparation. The IEC collaborates closely with the International Organization
for Standardization (ISO) in accordance with conditions determined by agreement between the two
organizations.
2) The formal decisions or agreements of the IEC on technical matters express, as nearly as possible, an
international consensus of opinion on the relevant subjects since each technical committee has representation
from all interested National Committees.
3) The documents produced have the form of recommendations for international use and are published in the form
of standards, technical reports or guides and they are accepted by the National Committees in that sense.
4) In order to promote international unification, IEC National Committees undertake to apply IEC International
Standards transparently to the maximum extent possible in their national and regional standards. Any
divergence between the IEC Standard and the corresponding national or regional standard shall be clearly
indicated in the latter.
5) The IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with one of its standards.
6) Attention is drawn to the possibility that some of the elements of this International Standard may be the subject
of patent rights. The IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60191-3 has been prepared by subcommittee 47D: Mechanical
standardization of semiconductor devices, of IEC technical committee 47: Semiconductor
devices.
This second edition cancels and replaces the first edition published in 1974, amendment 1
(1983), amendment 2 (1995), IEC 60191-3A (1976), IEC 60191-3B (1978), IEC 60191-3C
(1987), IEC 60191-3D (1988), IEC 60191-3E (1990) and IEC 60191-3F (1994).
The text of this standard is based on the following documents:
FDIS Report on voting
47D/299/FDIS 47D/322/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with ISO/IEC Directives, Part 3.

60191-3 © IEC:1999 – 7 –
Annexes A, C, D, E, F, G, H and K form an integral part of this standard.
Annex B is for information only.
The committee has decided that the contents of this publication will remain unchanged until 2005.
At this date, the publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition; or
• amended.
60191-3 © IEC:1999 – 9 –
MECHANICAL STANDARDIZATION OF
SEMICONDUCTOR DEVICES –
Part 3: General rules for the preparation of outline drawings
of integrated circuits
1 General
1.1 Scope
This part of IEC 60191 gives guidance on the preparation of drawings of integrated circuit
outlines.
1.2 Normative references
The following normative documents contain provisions which, through reference in this text,
constitute provisions of this part of IEC 60191. For dated references, subsequent amendments
to, or revisions of, any of these publications do not apply. However, parties to agreements
based on this part of IEC 60191 are encouraged to investigate the possibility of applying the
most recent editions of the normative documents indicated below. For undated references, the
latest edition of the normative document referred to applies. Members of IEC and ISO maintain
registers of currently valid International Standards.
IEC 60191-1:1966, Mechanical standardization of semiconductor devices – Part 1: Preparation
of drawings of semiconductor devices
IEC 60191-2:1995, Mechanical standardization of semiconductor devices – Part 2: Dimensions
IEC 60191-4:1999, Mechanical standardization of semiconductor devices – Part 4: Coding
system and classification into forms of package outlines for semiconductor devices
ISO 1101-1,  Geometrical Product Specification (GPS) – Geometrical tolerancing –
1)
Generalities, definitions, symbols, indications on drawings
ISO 2692:1988, Technical drawings – Geometrical tolerancing – Maximum material principle
2 Terminology and definitions
For the purpose of this part of IEC 60191, the following definitions apply.
2.1
package outline drawing
the drawing of a package which specifies the dimensional characteristics and other closely
associated features which are required for mechanical interchangeability.
___________
1)
To be published.
60191-3 © IEC:1999 – 11 –
2.2
seating plane
a plane which designates the plane of contact of the package, including any stand-off, with the
surface on which it will be mounted.
NOTE – This plane is often used as the reference plane.
2.3
base plane
a plane drawn parallel to the seating plane through the lowest point of the package, excluding
any stand-off.
2.4
gauging plane
a plane perpendicular to the terminals, at which the position of the terminals is controlled.
NOTE – In some packages, two or more of the above-mentioned planes may coincide.
2.5
terminal position
one of a series or equally spaced locations on a circle or on a row, which may or may not be
occupied by a terminal.
2.6
visual index
a reference feature (e.g. mark, chamfer, notch, tab, depression, etc.) which identifies the first
terminal position.
2.7
index area
the area in which a portion or all of the visual index should lie.
2.8
mechanical index
a feature (e.g. tab, notch, flat, groove, etc.) which provides orientation during automatic
handling.
Where possible, the mechanical index should coincide with the visual index.
2.9
index centre line or datum line
a centre line through a visual index feature (e.g. tab) which is used to orientate the index with
the first terminal position.
2.10
grid reference corner
the first terminal position (viewed from the free end of the terminals) in an alphanumeric grid
system.
2.11
terminal row
a series of equally spaced terminal positions which are located on a straight line.
2.12
terminal circle
a series of equally spaced terminal positions which are located on a circle.

60191-3 © IEC:1999 – 13 –
2.13
gauging zone
a control zone within which positional tolerances for the terminal axes or the planes of terminal
symmetry are specified.
2.14
dambar
metal barrier extending between adjacent leads to restrict the flow of mold compound material
between and along leads.
2.15
dambar protrusion
the presence of excess metal extending outward from the edge of a lead shoulder.
The width of the protrusion is the perpendicular distance from the defined lead edge to the
outermost portion of the excess metal. The length of the protrusion is the largest dimension of
the excess metal parallel to the defined lead edge (see figure 1a).
2.16
dambar intrusion
the absence of metal causing a discontinuity along the intended profile of a lead shoulder.
The depth of the intrusion is the perpendicular distance from the defined lead shoulder edge to
the innermost edge of the region of absent metal. The length of the intrusion is the largest
dimension of the region of absent metal parallel to the defined lead edge (
...