ASTM F1153-92(2002)

NOTICE: This standard has either been superceded and replaced by a new version or discontinued.
Contact ASTM International (www.astm.org) for the latest information.
Designation: F 1153 – 92 (Reapproved 2002)
Standard Test Method for
Characterization of Metal-Oxide-Silicon (MOS) Structures by
Capacitance-Voltage Measurements
This standard is issued under the fixed designation F 1153; the number immediately following the designation indicates the year of
original adoption or, in the case of revision, the year of last revision. A number in parentheses indicates the year of last reapproval. A
superscript epsilon (e) indicates an editorial change since the last revision or reapproval.
1. Scope responsibility of the user of this standard to establish appro-
priate safety and health practices and determine the applica-
1.1 This test method covers procedures for measurement of
bility of regulatory limitations prior to use.
metal-oxide-silicon (MOS) structures for flatband capacitance,
flatband voltage, average carrier concentration within a deple-
2. Referenced Documents
tion length of the semiconductor-oxide interface, displacement
2.1 ASTM Standards:
of flatband voltage after application of voltage stress at
F 388 Method for Measurement of Oxide Thickness on
elevated temperatures, mobile ionic charge contamination, and
Silicon Wafers and Metallization Thickness by Multiple
total fixed charge density. Also covered is a procedure for
Beam Interference (Tolansky Method)
detecting the presence of P-N junctions in the subsurface
F 576 Test Method for Measurement of Insulator Thickness
region of bulk or epitaxial silicon.
and Refractive Index on Silicon Substrates by Ellipsom-
1.2 The procedure is applicable to n-type and p-type bulk
14 16 etry
silicon with carrier concentration from 5 3 10 to 5 3 10
3 + +
F 723 Practice for Conversion Between Resistivity and
carriers per cm , inclusive, and N/N and P/P epitaxial
Dopant Density for Boron-Doped and Phosphorus-Doped
silicon with the same range of carrier concentration.
Silicon
1.3 The procedure is applicable for test specimens with
oxide thicknesses of 50 to 300 nm.
3. Terminology
1.4 The procedure can give an indication of the level of
3.1 Definitions of Terms Specific to This Standard:
defects within the MOS structure. These defects include
3.2 accumulation condition—the region of the C-V curve
interface trapped charge, fixed oxide charge, trapped oxide
for which a 5 V increment toward a more negative voltage for
charge, and permanent inversion layers.
p-type material (Fig. 1), or toward a more positive voltage for
1.5 The precision of the procedure can be affected by
n-type material (Fig. 2), results in less than a 1 % change in the
inhomogeneities in the oxide or in the semiconductor parallel
maximum capacitance, C .
max
to the semiconductor-oxide interface.
3.3 equilibrium capacitance—that capacitance reached after
1.6 The procedure is applicable for measurement of mobile
10 −2 an MOS specimen at a fixed bias is illuminated and then
ionic charge concentrations of 1 3 10 cm or greater.
allowed to stabilize in darkness.
Alternative techniques, such as the triangular voltage sweep
2 3.4 flatband condition, in microelectronics—the point at
method (1), may be required where mobile ionic charge
10 −2 which an external applied voltage causes there to be no internal
concentrations less than 1 3 10 cm must be measured.
potential difference across an MOS structure. Under practical
1.7 The procedure is applicable for measurement of total
10 −2 conditions, metal-semiconductor work-function differences
fixed charge density of 5 3 10 cm or greater. Alternative
and charges in the oxide require the application of an external
techniques, such as the conductance method (2), may be
voltage to produce the flatband condition.
required where the interface trapped-charge density component
10 −2 3.5 flatband voltage, V —the applied voltage necessary to
fb
of total fixed charge of less than 5 3 10 cm must be
produce the flatband condition.
measured.
3.6 flatband capacitance, C —the capacitance of an MOS
fb
1.8 This standard does not purport to address all of the
structure at the flatband voltage.
safety concerns, if any, associated with its use. It is the
3.7 inversion condition—for the purposes of this test
method and for measurements on surfaces that do not exhibit a
This test method is under the jurisdiction of ASTM Committee F01 on permanent inversion layer, the region of the Capacitance-
Electronics and is the direct responsibility of Subcommittee F01.06 on Silicon
Voltage, (C-V) curve for which a 5 V increment toward a more
Materials and Process Control.
Current edition approved May 15, 1992. Published July 1992. Originally
published as F 1153 – 88. Last previous edition F 1153 – 88.
2 3
Boldface numbers in parentheses refer to the list of references at the end of this Discontinued; see 1992 Annual Book of ASTM Standards, Vol 10.05.
test method. Annual Book of ASTM Standards, Vol 10.05.
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NOTICE: This standard has either been superceded and replaced by a new version or discontinued.
Contact ASTM International (www.astm.org) for the latest information.
F 1153 – 92 (2002)
4.4 A voltage stress is applied to the sample at elevated
temperature and the shift in V is measured after cooling. This
fb
shift is interpreted as a measure of the concentration of mobile
ionic charges in the oxide.
4.5 Total fixed-charge density is calculated from the flat-
band voltage.
4.6 The presence of subsurface P-N junctions is detected by
photosensitivity. The specimen is biased into accumulation,
and the capacitance measured and recorded. The specimen is
FIG. 1 Typical Capacitance-Voltage Plot of MOS Device
then illuminated and the capacitance remeasured. An increase
Fabricated with p-Type Silicon
in capacitance due to illumination is interpreted as an indica-
tion of the presence of a P-N junction.
NOTE 1—Light will generate charge in the P-N junction and alter the
capacitance of the junction which is in series with the MOS device. For
the purposes of this test method, the subsurface region is defined as the
region extending from the true surface to a depth at which no light
penetrates. For the visible spectrum, maximum penetration depth is not
well defined, as it depends on the intensity and spectral distribution of the
light source and the carrier concentration of the silicon.
5. Significance and Use
FIG. 2 Typical Capacitance-Voltage Plot of MOS Device
Fabricated with n-Type Silicon
5.1 Net carrier concentration present near the silicon-oxide
interface may constitute an important acceptance requirement.
Where there is not significant doping compensation by impu-
positive voltage for p-type material (Fig. 1), or toward a more
rities of the opposite conductivity type, the material resistivity
negative voltage for n-type material (Fig. 2), results in less than
may be determined from this carrier concentration using
1 % change in the equilibrium minimum capacitance, C .
min
Practice F 723.
3.8 permanent inversion layer—for the purposes of this test
5.2 Flatband voltage is an important parameter in the
method, the region of the C-V curve that exhibits a definite
manufacture of MOS devices. Its value is dependent on the
minimum 88dip,’’ as shown in Fig. 3. The permanent inversion
work function difference between the silicon and the metal
layer is an anomalous condition caused by interface charge or
field plate, interface trapped charge, and fixed or trapped
surface conditions and prevents proper determination of C .
min
charge distributed within the oxide. It can be an indicator of
3.9 total fixed charge density, N —the sum of the nonmo-
tf
anomalies in these values (4).
bile charge densities: oxide fixed charge density, oxide trapped
5.3 Instability of the flatband voltage of an MOS structure
charge density, and interface trapped charge density (3).
subjected to voltage stress at elevated temperatures is a
measure of the mobile ionic charge concentration within the
4. Summary of Test Method
oxide. Most device applications require that mobile ionic
4.1 A specimen MOS structure consisting of a metal field
charge be minimized.
plate on the oxidized silicon substrate is fabricated.
5.4 This test method may be employed for qualification of
4.2 The small-signal, high-frequency capacitance of the
furnaces or other semiconductor device-processing equipment
specimen is measured as a function of a ramped voltage
where such qualification depends on the determination of
applied between the field plate and the silicon substrate.
contamination resulting from high mobile ionic charge concen-
4.3 The surface carrier concentration, flatband capacitance,
tration.
and flatband voltage, are computed from the capacitance and
5.5 The presence of unwanted subsurface P-N junctions
voltage data.
may have deleterious effects on device operation.
6. Interferences
6.1 If the apparatus is not well shielded from electromag-
netic interference caused by radio frequency (r-f) fields, their
presence may affect the measurements since the impedance of
the MOS structure is high and since the test signal used is in the
mV range.
6.2 The presence of any light during the measurements will
adversely affect the results as the capacitance of the MOS
device in the inversion condition is light sensitive.
6.3 The measurement may be affected if the relative humid-
ity of the environment is permitted to exceed 60 %. The use of
NOTE 1—Specimen exhibits permanent inversion layer.
dry N gas flowing into the sample chamber is recommended to
FIG. 3 Capacitance-Voltage Plot of MOS Device Fabricated with 2
p-Type Silicon control excess humidity.
NOTICE: This standard has either been superceded and replaced by a new version or discontinued.
Contact ASTM International (www.astm.org) for the latest information.
F 1153 – 92 (2002)
on high resistivity substrates exhibit high series resistance effects which
6.4 The presence of a permanent surface inversion layer
may require concurrent conductance measurements and subsequent com-
condition can affect the measurement.
putations to determine the true MOS capacitance. This test method is
NOTE 2—A permanent surface inversion layer condition makes it
limited to capacitance-only measurements, but includes a test in 12.1 to
difficult to determine the value for C to be used in the calculations. If
check for the presence of series resistance effects.
min
an incorrect C were chosen, all shift values would still be correct, but
min
7.2.3 Digital Voltmeter (DVM), with sensitivity 1 μV or
doping and fixed charge computations would be wrong.
better, accuracy of 0.5 % of full scale or better, a reproducibil-
6.5 Stray capacitance and inductance caused by excessive
ity of 0.25 % of full scale or better, an input impedance of 10
lengths of connecting cable and by improper zeroing of the
MV or greater, and a common mode rejection 100 dB or
capacitance measuring instrument can cause significant errors
greater at 60 Hz.
in the capacitance measurement. Typical cable lengths should
7.2.4 X-Y Recorder, with a minimum slewing speed of 20
be kept below 1 m.
cm/s, an accuracy of 0.5 % of full scale or better, a linearity of
6.6 Alternating Current, (a-c) test signals greater than 25
0.5 % of full scale or better, and an input impedance of 1 MV
mV rms can lead to errors in the measured capacitance.
or greater. X-axis and y-axis sensitivities shall be 5 mV/cm or
6.7 Series resistance between the MOS capacitor and the
greater.
capacitance measuring instrument can cause significant errors
7.2.5 Stress Bias d-c Power Supply, capable of supplying 0
in the measured capacitance. Sources of series resistance can
to 6100 V (open circuit) with ripple 1 % of the d-c output or
be in the sample itself, in the back contact, or in the test cables.
less, to be used for voltage stressing.
6.8 A leaky oxide which draws significant current can cause
errors in the measured capacitance. 7.3 Standard Capacitors, of accuracy 0.25 % or better at the
6.9 Inability of an inversion layer to form in an MOS measurement frequency. At least one capacitor shall be used
sample will preclude measurement by this test method. for each capacitance meter range used. At least one capacitor
6.10 Very long minority-carrier lifetime in an MOS sample shall be in the range 1 to 10 pF inclusive and one shall be in the
may cause errors in the measurement of C if the inversion range 10 to 100 pF inclusive.
min
layer has not had sufficient time to form.
7.4 Probe Fixture:
7.4.1 Probe, to contact the top field plate; probe force shall
NOTE 3—A maximum lifetime cannot be specified readily. However, an
error will occur if the lamp in 11.9 is not illuminated for sufficient not exceed 1.75 N; probe tip shall have a nominal radius of
duration, or is not of sufficient intensity to generate charge to form the
curvature of 5 μm; probe and holder should be designed such
inversion layer.
that the stray capacitance is less than 1 pF.
6.11 Prolonged negative-bias temperature stressing can re-
7.4.2 Vacuum Chuck, to hold the specimen wafer and
sult in a shift in flatband voltage larger than the shift due to
contact the back surface; capable of reaching a temperature of
mobile ionic charge alone.
300°C, and maintaining set temperature to within 610°C over
6.12 Hysteresis in the capacitance-voltage characteristics of
the specimen area.
an MOS sample can cause significant error in the determination
7.4.3 Light Tight Metal Box, to enclose the specimen during
of mobile ionic charge concentration.
the measurement. Equipped with incandescent lamp, 7 to 20 W.
7. Apparatus 7.4.4 Dry N Gas Flow, to control the humidity in the
sample chamber.
7.1 Facilities, for growing gate quality oxides and for
7.5 Equipment, to measure the temperature of the vacuum
depositing and defining metal field plates on the oxide.
chuck of 7.4.2 with an accuracy of 62°C.
7.2 Electrical Apparatus:
7.2.1 Ramping d-c Voltage Supply, covering the range 6100 7.6 Toolmaker’s Microscope, Shadowgraph or Planimeter,
V and capable of sweeping between any two preset voltages capable of measuring the field plate diameter to an accuracy of
within that range. Sweeping rate shall be variable between 0.1 0.5 % or better or the field plate area to an accuracy of 1 % or
and 1 V/s. Ripple shall be 0.5 % of the d-c output, or less. The better.
supply shall be capable of supplying a fixed preset voltage with
7.7 Shielded Cables, for making electrical connections be-
an accuracy of 610 mV.
tween the probe fixture, ramping voltage supply, capacitance
7.2.2 Capacitance Meter, with full scale ranges of 1 pF to
meter, and digital voltmeter.
1000 pF, or greater, in decade, or smaller, steps. The measure-
7.8 Precision Voltage Source, capable of providing output
ment f
...