ASTM F1153-92(1997)

NOTICE: This standard has either been superseded and replaced by a new version or withdrawn. Contact
ASTM International (www.astm.org) for the latest information.
Designation: F 1153 – 92 (Reapproved 1997)
AMERICAN SOCIETY FOR TESTING AND MATERIALS
100 Barr Harbor Dr., West Conshohocken, PA 19428
Reprinted from the Annual Book of ASTM Standards. Copyright ASTM
Standard Test Method for
Characterization of Metal-Oxide-Silicon (MOS) Structures by
Capacitance-Voltage Measurements
This standard is issued under the fixed designation F 1153; the number immediately following the designation indicates the year of
original adoption or, in the case of revision, the year of last revision. A number in parentheses indicates the year of last reapproval. A
superscript epsilon (e) indicates an editorial change since the last revision or reapproval.
1. Scope priate safety and health practices and determine the applica-
bility of regulatory limitations prior to use.
1.1 This test method covers procedures for measurement of
metal-oxide-silicon (MOS) structures for flatband capacitance,
2. Referenced Documents
flatband voltage, average carrier concentration within a deple-
2.1 ASTM Standards:
tion length of the semiconductor-oxide interface, displacement
F 388 Method for Measurement of Oxide Thickness on
of flatband voltage after application of voltage stress at
Silicon Wafers and Metallization Thickness by Multiple
elevated temperatures, mobile ionic charge contamination, and
Beam Interference (Tolansky Method)
total fixed charge density. Also covered is a procedure for
F 576 Test Method for Measurement of Insulator Thickness
detecting the presence of P-N junctions in the subsurface
and Refractive Index on Silicon Substrates by Ellipsom-
region of bulk or epitaxial silicon.
etry
1.2 The procedure is applicable to n-type and p-type bulk
14 16
F 723 Practice for Conversion Between Resistivity and
silicon with carrier concentration from 5 3 10 to 5 3 10
3 + + Dopant Density for Boron-Doped and Phosphorus-Doped
carriers per cm , inclusive, and N/N and P/P epitaxial
Silicon
silicon with the same range of carrier concentration.
1.3 The procedure is applicable for test specimens with
3. Terminology
oxide thicknesses of 50 to 300 nm.
3.1 Definitions of Terms Specific to This Standard:
1.4 The procedure can give an indication of the level of
3.2 accumulation condition—the region of the C-V curve
defects within the MOS structure. These defects include
for which a 5 V increment toward a more negative voltage for
interface trapped charge, fixed oxide charge, trapped oxide
p-type material (Fig. 1), or toward a more positive voltage for
charge, and permanent inversion layers.
n-type material (Fig. 2), results in less than a 1 % change in the
1.5 The precision of the procedure can be affected by
maximum capacitance, C .
max
inhomogeneities in the oxide or in the semiconductor parallel
3.3 equilibrium capacitance—that capacitance reached after
to the semiconductor-oxide interface.
an MOS specimen at a fixed bias is illuminated and then
1.6 The procedure is applicable for measurement of mobile
10 −2
allowed to stabilize in darkness.
ionic charge concentrations of 1 3 10 cm or greater.
3.4 flatband condition, in microelectronics—the point at
Alternative techniques, such as the triangular voltage sweep
2 which an external applied voltage causes there to be no internal
method (1), may be required where mobile ionic charge
10 −2 potential difference across an MOS structure. Under practical
concentrations less than 1 3 10 cm must be measured.
conditions, metal-semiconductor work-function differences
1.7 The procedure is applicable for measurement of total
10 −2 and charges in the oxide require the application of an external
fixed charge density of 5 3 10 cm or greater. Alternative
voltage to produce the flatband condition.
techniques, such as the conductance method (2), may be
3.5 flatband voltage, V —the applied voltage necessary to
fb
required where the interface trapped-charge density component
10 −2 produce the flatband condition.
of total fixed charge of less than 5 3 10 cm must be
3.6 flatband capacitance, C —the capacitance of an MOS
fb
measured.
structure at the flatband voltage.
1.8 This standard does not purport to address all of the
3.7 inversion condition—for the purposes of this test
safety concerns, if any, associated with its use. It is the
method and for measurements on surfaces that do not exhibit a
responsibility of the user of this standard to establish appro-
permanent inversion layer, the region of the Capacitance-
Voltage, (C-V) curve for which a 5 V increment toward a more
This test method is under the jurisdiction of ASTM Committee F-1 on positive voltage for p-type material (Fig. 1), or toward a more
Electronics and is the direct responsibility of Subcommittee F01.06 on Silicon
negative voltage for n-type material (Fig. 2), results in less than
Materials and Process Control.
Current edition approved May 15, 1992. Published July 1992. Originally
published as F 1153 – 88. Last previous edition F 1153 – 88.
2 3
Boldface numbers in parentheses refer to the list of references at the end of this Discontinued; see 1992 Annual Book of ASTM Standards, Vol 10.05.
test method. Annual Book of ASTM Standards, Vol 10.05.
NOTICE:¬This¬standard¬has¬either¬been¬superceded¬and¬replaced¬by¬a¬new¬version¬or¬discontinued.¬
Contact¬ASTM¬International¬(www.astm.org)¬for¬the¬latest¬information.¬
F 1153
4.5 Total fixed-charge density is calculated from the flat-
band voltage.
4.6 The presence of subsurface P-N junctions is detected by
photosensitivity. The specimen is biased into accumulation,
and the capacitance measured and recorded. The specimen is
then illuminated and the capacitance remeasured. An increase
in capacitance due to illumination is interpreted as an indica-
tion of the presence of a P-N junction.
NOTE 1—Light will generate charge in the P-N junction and alter the
FIG. 1 Typical Capacitance-Voltage Plot of MOS Device
capacitance of the junction which is in series with the MOS device. For
Fabricated with p-Type Silicon
the purposes of this test method, the subsurface region is defined as the
region extending from the true surface to a depth at which no light
penetrates. For the visible spectrum, maximum penetration depth is not
well defined, as it depends on the intensity and spectral distribution of the
light source and the carrier concentration of the silicon.
5. Significance and Use
5.1 Net carrier concentration present near the silicon-oxide
interface may constitute an important acceptance requirement.
Where there is not significant doping compensation by impu-
FIG. 2 Typical Capacitance-Voltage Plot of MOS Device
rities of the opposite conductivity type, the material resistivity
Fabricated with n-Type Silicon
may be determined from this carrier concentration using
Practice F 723.
1 % change in the equilibrium minimum capacitance, C .
min
5.2 Flatband voltage is an important parameter in the
3.8 permanent inversion layer—for the purposes of this test
manufacture of MOS devices. Its value is dependent on the
method, the region of the C-V curve that exhibits a definite
work function difference between the silicon and the metal
minimum 88dip,’’ as shown in Fig. 3. The permanent inversion
field plate, interface trapped charge, and fixed or trapped
layer is an anomalous condition caused by interface charge or
charge distributed within the oxide. It can be an indicator of
surface conditions and prevents proper determination of C .
min
anomalies in these values (4).
3.9 total fixed charge density, N —the sum of the nonmo-
tf
5.3 Instability of the flatband voltage of an MOS structure
bile charge densities: oxide fixed charge density, oxide trapped
subjected to voltage stress at elevated temperatures is a
charge density, and interface trapped charge density (3).
measure of the mobile ionic charge concentration within the
oxide. Most device applications require that mobile ionic
4. Summary of Test Method
charge be minimized.
4.1 A specimen MOS structure consisting of a metal field
5.4 This test method may be employed for qualification of
plate on the oxidized silicon substrate is fabricated.
furnaces or other semiconductor device-processing equipment
4.2 The small-signal, high-frequency capacitance of the
where such qualification depends on the determination of
specimen is measured as a function of a ramped voltage
contamination resulting from high mobile ionic charge concen-
applied between the field plate and the silicon substrate.
tration.
4.3 The surface carrier concentration, flatband capacitance,
5.5 The presence of unwanted subsurface P-N junctions
and flatband voltage, are computed from the capacitance and
may have deleterious effects on device operation.
voltage data.
4.4 A voltage stress is applied to the sample at elevated
6. Interferences
temperature and the shift in V is measured after cooling. This
fb
6.1 If the apparatus is not well shielded from electromag-
shift is interpreted as a measure of the concentration of mobile
netic interference caused by radio frequency (r-f) fields, their
ionic charges in the oxide.
presence may affect the measurements since the impedance of
the MOS structure is high and since the test signal used is in the
mV range.
6.2 The presence of any light during the measurements will
adversely affect the results as the capacitance of the MOS
device in the inversion condition is light sensitive.
6.3 The measurement may be affected if the relative humid-
ity of the environment is permitted to exceed 60 %. The use of
dry N gas flowing into the sample chamber is recommended to
control excess humidity.
6.4 The presence of a permanent surface inversion layer
condition can affect the measurement.
NOTE 1—Specimen exhibits permanent inversion layer.
NOTE 2—A permanent surface inversion layer condition makes it
FIG. 3 Capacitance-Voltage Plot of MOS Device Fabricated with
p-Type Silicon difficult to determine the value for C to be used in the calculations. If
min
NOTICE:¬This¬standard¬has¬either¬been¬superceded¬and¬replaced¬by¬a¬new¬version¬or¬discontinued.¬
Contact¬ASTM¬International¬(www.astm.org)¬for¬the¬latest¬information.¬
F 1153
an incorrect C were chosen, all shift values would still be correct, but
7.2.3 Digital Voltmeter (DVM), with sensitivity 1 μV or
min
doping and fixed charge computations would be wrong.
better, accuracy of 0.5 % of full scale or better, a reproducibil-
ity of 0.25 % of full scale or better, an input impedance of 10
6.5 Stray capacitance and inductance caused by excessive
MV or greater, and a common mode rejection 100 dB or
lengths of connecting cable and by improper zeroing of the
greater at 60 Hz.
capacitance measuring instrument can cause significant errors
in the capacitance measurement. Typical cable lengths should 7.2.4 X-Y Recorder, with a minimum slewing speed of 20
be kept below 1 m. cm/s, an accuracy of 0.5 % of full scale or better, a linearity of
0.5 % of full scale or better, and an input impedance of 1 MV
6.6 Alternating Current, (a-c) test signals greater than 25
mV rms can lead to errors in the measured capacitance. or greater. X-axis and y-axis sensitivities shall be 5 mV/cm or
greater.
6.7 Series resistance between the MOS capacitor and the
capacitance measuring instrument can cause significant errors
7.2.5 Stress Bias d-c Power Supply, capable of supplying 0
in the measured capacitance. Sources of series resistance can to 6100 V (open circuit) with ripple 1 % of the d-c output or
be in the sample itself, in the back contact, or in the test cables.
less, to be used for voltage stressing.
6.8 A leaky oxide which draws significant current can cause
7.3 Standard Capacitors, of accuracy 0.25 % or better at the
errors in the measured capacitance.
measurement frequency. At least one capacitor shall be used
6.9 Inability of an inversion layer to form in an MOS
for each capacitance meter range used. At least one capacitor
sample will preclude measurement by this test method.
shall be in the range 1 to 10 pF inclusive and one shall be in the
6.10 Very long minority-carrier lifetime in an MOS sample
range 10 to 100 pF inclusive.
may cause errors in the measurement of C if the inversion
min 7.4 Probe Fixture:
layer has not had sufficient time to form.
7.4.1 Probe, to contact the top field plate; probe force shall
not exceed 1.75 N; probe tip shall have a nominal radius of
NOTE 3—A maximum lifetime cannot be specified readily. However, an
curvature of 5 μm; probe and holder should be designed such
error will occur if the lamp in 11.9 is not illuminated for sufficient
duration, or is not of sufficient intensity to generate charge to form the
that the stray capacitance is less than 1 pF.
inversion layer.
7.4.2 Vacuum Chuck, to hold the specimen wafer and
contact the back surface; capable of reaching a temperature of
6.11 Prolonged negative-bias temperature stressing can re-
sult in a shift in flatband voltage larger than the shift due to 300°C, and maintaining set temperature to within 610°C over
the specimen area.
mobile ionic charge alone.
6.12 Hysteresis in the capacitance-voltage characteristics of
7.4.3 Light Tight Metal Box, to enclose the specimen during
an MOS sample can cause significant error in the determination the measurement. Equipped with incandescent lamp, 7 to 20 W.
of mobile ionic charge concentration.
7.4.4 Dry N Gas Flow, to control the humidity in the
sample chamber.
7. Apparatus
7.5 Equipment, to measure the temperature of the vacuum
7.1 Facilities, for growing gate quality oxides and for
chuck of 7.4.2 with an accuracy of 62°C.
depositing and defining metal field plates on the oxide.
7.6 Toolmaker’s Microscope, Shadowgraph or Planimeter,
7.2 Electrical Apparatus:
capable of measuring the field plate diameter to an accuracy of
7.2.1 Ramping d-c Voltage Supply, covering the range 6100
0.5 % or better or the field plate area to an accuracy of 1 % or
V and capable of sweeping between any two preset voltages
better.
within that range. Sweeping rate shall be variable between 0.1
7.7 Shielded Cables, for making electrical connections be-
and 1 V/s. Ripple shall be 0.5 % of the d-c output, or less. The
tween the probe fixture, ramping voltage supply, capacitance
supply shall be capable of supplying a fixed preset voltage with
meter, and digital voltmeter.
an accuracy of 610 mV.
7.8 Precision Voltage Source, capable of providing output
7.2.2 Capacitance Meter, with full scale ranges of 1 pF to
voltages from − 100 to + 100 V. The accuracy of this source
1000 pF, or greater, in decade, or smaller, steps. The measure-
shall be 0.1 % or better.
ment frequency shall be in the range 0.9 to 1.1 MHz inclusive.
7.9 A d-c Current Detector, capable of measuring currents
The accuracy shall be 0.5 % of full scale or better for each
in the range from 100 nA to 1 mA, inclusive, with an accuracy
ran
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