SIST-TS CLC/TS 50590:2015

SLOVENSKI STANDARD
01-junij-2015
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Electricity metering data exchange - Lower layer PLC profile using adaptive multi-carrier
spread spectrum for CX1 networks
Ta slovenski standard je istoveten z: CLC/TS 50590:2015
ICS:
35.240.50 Uporabniške rešitve IT v IT applications in industry
industriji
91.140.50 Sistemi za oskrbo z elektriko Electricity supply systems
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

TECHNICAL SPECIFICATION CLC/TS 50590

SPÉCIFICATION TECHNIQUE
TECHNISCHE SPEZIFIKATION
April 2015
ICS 35.240.60; 91.140.50
English Version
Electricity metering data exchange - Lower layer PLC profile
using Adaptive Multi Carrier Spread-Spectrum (AMC-SS)
modulation
This Technical Specification was approved by CENELEC on 2014-11-11.

CENELEC members are required to announce the existence of this TS in the same way as for an EN and to make the TS available promptly
at national level in an appropriate form. It is permissible to keep conflicting national standards in force.

CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic,
Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia,
Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland,
Turkey and the United Kingdom.

European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
CEN-CENELEC Management Centre: Avenue Marnix 17, B-1000 Brussels
© 2015 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members.
Ref. No. CLC/TS 50590:2015 E
CONTENTS
Foreword . 5
1 Scope . 6
2 Normative references . 6
3 Terms, definitions and acronyms . 6
3.1 Terms and definitions . 6
3.2 Acronyms . 8
4 General description . 9
5 PHY layer specification . 12
5.1 Overview . 12
5.2 PHY protocol data unit . 13
5.2.1 PPDU structure . 13
5.2.2 PHY header . 15
5.2.3 PHY data . 15
5.3 PHY frame transmission . 16
5.3.1 General . 16
5.3.2 Forward error correction encoding . 18
5.3.3 Interleaving . 19
5.3.4 PSK / DPSK mapping . 20
5.3.5 Carrier frequency mapping . 22
5.3.6 Modulation . 24
5.4 EMC requirements . 27
5.5 PHY layer services . 27
5.5.1 General . 27
5.5.2 P_data.request . 28
5.5.3 P_data.indication . 28
6 Data link layer specification . 30
6.1 Overview . 30
6.2 MAC protocol data unit . 30
6.2.1 MPDU structure . 30
6.2.2 Frame forwarding sector number . 32
6.2.3 MAC-channel identification number . 33
6.2.4 Network identification number. 33
6.2.5 Link address . 33
6.2.6 Data block length . 33
6.2.7 Total number of frame retransmissions . 33
6.2.8 Frame retransmission down counter . 34
6.2.9 Reference zero-crossing delay . 34
6.2.10 Logical link control field . 34
6.2.11 Frame header check sequence . 38
6.2.12 Data block and frame check sequence . 38
6.2.13 Scrambling . 38
6.3 MAC frame transmission . 38
6.4 The LLC protocol data unit . 41

– 3 – CLC/TS 50590:2015
6.5 Message transmission in LLC layer . 41
6.5.1 General . 41
6.5.2 DL_data.request . 42
6.5.3 DL_data_identifier.confirm . 43
6.5.4 DL_data.indication . 45
6.5.5 DL_data.response . 46
6.5.6 DL_data.confirm . 47
6.5.7 DL_data_ack.response . 47
6.5.8 DL_data_ack.confirm . 48
6.5.9 DL_control.indication . 49
6.5.10 Transmission from slave node . 50
6.5.11 Transmission from master node . 53
6.5.12 Acknowledged unicast transmission . 55
6.6 Clock synchronisation . 61
6.7 Status enquiry . 62
6.8 PHY-link test . 62
6.9 PHY quality data enquiry . 63
7 Layer-2-network capability . 63
7.1 Overview . 63
7.2 Registration procedure . 64
7.2.1 General . 64
7.2.2 Registration of a new slave node . 65
7.2.3 Data link connection time-out . 68
7.2.4 Re-establishing of data link connection after power-down . 68
7.3 Coordination of master nodes . 69
7.4 Cell change by slave node . 69
Annex A (normative) . 72
A.1 Window functions . 72
Annex B (normative) Logical Link Control Functions . 101
B.1 Master node messages for data link control (PRM=1, DLS=0) . 101
B.2 Master node messages for higher layer servicing (PRM=1, DLS=1) . 111
B.3 Slave node messages for data link control functions (PRM=0, DLS=0) . 117
B.4 Slave node messages for higher layer servicing (PRM=0, DLS=1) . 125
Annex C (informative) Examples of network scenarios . 127
C.1 Example of a network . 127
C.1 General . 127
C.2 Examples of an s-MN becoming a master node . 127
Annex D (normative) Configuration and time parameters . 130

TABLE OF FIGURES
Figure 1 – Layers of AMC-SS profile. . 10
Figure 2 – Primitives . 11
Figure 3 – PHY layer processing steps during PPDU transmission . 12
Figure 4 – Bit-oriented PPDU structure without TS. 13
Figure 5 – Structure of transmit signal (PHY frame) consisting of overlapped
modulated symbols . 14

Figure 6 –General structure of a convolutional encoder with constraint length 7,
used in this particular example (solid connections) for rate ½ encoder . 18
Figure 7 – Combining of overlapped modulated symbols . 26
Figure 8 – Combining of overlapped modulated symbols followed by IFI . 27
Figure 9 – Primitives between layer 2 and layer 1 . 28
Figure 10 – MPDU structure . 31
Figure 11 – Formats of logical link control field . 34
Figure 12 – Pseudo-noise sequence generator . 38
Figure 13 – Frame transmission procedure used by SEND/NO REPLY service. . 39
Figure 14 – Frame transmission procedure with simultaneous forwarding . 40
Figure 15 – Frame transmission procedures used by REQUEST/RESPOND
service. . 41
Figure 16 – Example of data collection by polling . 51
Figure 17 – Example of data collection using quick-check procedure . 53
Figure 18 – Example of acknowledged unicast transmission with retry . 56
Figure 19 – – Example of acknowledged multicast/broadcast transmission . 58
Figure 20 – – Example of two multicast/broadcast transmissions with an error . 59
Figure 21 – – Example of broadcast with message retransmission . 60
Figure 22 – Example of non-acknowledged multicast/broadcast transmission . 61
Figure 23 – Example of PHY link test. . 62
Figure 24 – Example of link quality enquiry . 63
Figure 25 – Example of slave node registration procedure . 66
Figure 26 – Example of new multicast address assignment . 67
Figure 27 – Example of cell change by slave node . 70
Figure C.1 – Example of NSC . 140
Figure C.2 – Example of an s-MN becoming a master node . 141
Figure C.3 – Example of cell splitting . 141
Figure C.4 – Example of switching off a p-MN . 142
Figure C.5 – Example of cell spreading in NSC . 142

– 5 – CLC/TS 50590:2015
Foreword
This document (CLC/TS 50590:2015) has been prepared by CLC/TC 13 "Electrical energy
measurement and control".
The following date is fixed:
(doa) 2015-07-24
• latest date by which the existence of
this document has to be announced
at national level
Attention is drawn to the possibility that some of the elements of this document may be the
subject of patent rights. CENELEC [and/or CEN] shall not be held responsible for identifying any
or all such patent rights.
This document has been prepared under a mandate given to CENELEC by the European
Commission and the European Free Trade Association.

1 Scope
This Technical Specification specifies the physical layer, medium access control layer
and logical link control layer for communication on an electrical distribution network
between a master node and one or more slave nodes using a compatibly extendable
form (CX1) of Adaptive Multi-Carrier Spread Spectrum (AMC-SS) technique. The
adaptive cellular communication network technology provided in this specification may
be used for automated meter reading as well as for other distribution network
applications.
The[GK1] physical layer provides a modulation technique that efficiently utilizes the
allowed bandwidth within the CENELEC A band (3 kHz – 95 kHz), offering a very robust
communication in the presence of narrowband interference, impulsive noise, and
frequency selective attenuation. The physical layer of AMC-SS is defined in Clause 5 of
The data link (DL) layer consists of three parts, the ‘Medium Access Control’ (MAC)
sub-layer, the Logical Link Control (LLC) sub-layer and the ‘Convergence’ sub-layer.
The data link layer allows the transmission of data frames through the use of the power
line physical channel. It provides data services, frame integrity control, routing,
registration, multiple access, and cell change functionality. The MAC sub-layer and the
LLC sub-layer of AMC-SS are defined in Clause 6 of CLC/TS 50590:2015. The
Convergence sub-layer is defined in this document.
2 Normative references
The following documents, in whole or in part, are normatively referenced in this
document and are indispensable for its application. For dated references, only the
edition cited applies. For undated references, the latest edition of the referenced
document (including any amendments) applies.
EN 50065-1, Signaling on low-voltage electrical installations in the frequency range
3 kHz to 148,5 kHz – Part 1: General requirements, frequency bands and electromagnetic
disturbances
DIN 43863–5:2012-04, Identification number for measuring devices applying for all
manufacturers
3 Terms, definitions and acronyms
3.1 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
3.1.1
device identifier
property that universally identifies a node
3.1.2
frame forwarding
procedure of PHY frame retransmission by a slave node or simultaneously by several
slave nodes
– 7 – CLC/TS 50590:2015
3.1.3
higher layer entity
entity of the layer or sub-layer in OSI model, which is situated above the layer or sub-
layer of the entity offering the services. A possible convergence sub-layer between the
higher layer entity and the entity offering the services may be a null layer, which is as
simple as possible without a special convergence capability
3.1.4
MAC frame
MAC sub-layer Protocol Data Unit (MPDU)
3.1.5
master node
node which controls and manages the resources of a network cell
3.1.6
message
LLC sub-layer Protocol Data Unit (MPDU)
3.1.7
network
set of network nodes that can communicate by complying with this specification and are
identified by the same value of N_NIN
3.1.8
network cell
set of network nodes that can communicate by complying with this specification and
share a single master node, which is identified by the CIN
3.1.9
node
any one element of a network cell which is able to transmit to and receive from other
network elements
3.1.10
slave node
any node of a network cell which is not operating as a master node
3.1.11
PHY frame
a PHY Layer Protocol Data Unit (PPDU)
3.1.12
registration
procedure of master node assignment to a slave node
3.1.13
slave node registration
assignment of dynamic address information to a slave node
3.1.14
symbol
waveform used in the communication channel that persists for a fixed period of time

3.2 Acronyms
AC  Alternating Current
ACK  Acknowledgement
AGC  Automatic Gain Control
AMC-SS Adaptive Multi-Carrier Spread-Spectrum
BNC  Backbone Network Connection
BTO  Beacon Time-Out Period
CCV  Code Connection Vector
CENELEC European Committee for Electrotechnical Standardization
CFL  Carrier Frequency List
CIN  Channel Identification Number
CL  Convergence Sub-Layer
CONV Convolutional Code
COSEM Companion Specification for Energy Metering
CRC  Cyclic Redundancy Check
CRCINITVAL CRC Initialization Value
CWD  Contention Window Duration
CX1  Compatibly extendable form [JK3]of AMC-SS PLC
D_ACK  Data Acknowledgement
DB  Data Block
DBL  Data Block Length
DFC  Data Flow Control
D8PSK Differential Eight Phase Shift Keying
DBPSK Differential Binary Phase Shift Keying
DID  Device Identifier
DL  Data Link
DLL  Data Link Layer
DLMS Device Language Message Specification
DLS  Data Link Services
DP  Data Priority
DPSK Differential Phase Shift Keying
DQPSK Differential Quadrature Phase Shift Keying
FCB  Frame Count Bit
FCS  Frame Check Sequence
FCV  Frame Count Bit Valid
FEC  Forward Error Correction
FH  Frequency Hopping
FHCS Frame Header Check Sequence
FMS  Frequency mapping schemes
FX  Frame Forwarding
FXDC Frame Forwarding Down-Counter
FXS  Frame Forwarding Sector Address
FXT  Total Number of Frame Retransmissions
HLE  Higher Layer Entity
HTB  Header Tail Bits
Hz  Hertz
IEC  International Electrotechnical Commission
IFI  Interframe Interval
ITD  Initial Transmission Delay
kHz  kilo Hertz
L_FC  Link Function Code
L_NIN Lower Byte of Network Identification Number
LA  Link Address
LCN  Link Channel Number
LLC  Logical Link Control
LLCF  Logical Link Control Field
LPDU LLC Sub-Layer Protocol Data Unit
LSB  Least Significant Byte
LTS  Length of Training Sequence

– 9 – CLC/TS 50590:2015
N_NIN Node Network Identification Number
M_CIN Master Channel Identification Number
MAC  Medium Access Control
MA  Multicast Link-Address
MCN  Multicast Number
MN  Master Node
MPDU MAC Protocol Data Unit
MSB  Most Significant Byte
NIN  Network Identification Number
NLA  New Link Address
NMAx New Multicast Addresses
NSC  Network with Spreading/Shrinking Cells
p-MN  Primary Master Node
OSI  Open System Interconnection
PDDTH Power-Down Duration Threshold
PDS  PHY Data Symbol
PDU  Protocol Data Unit
PDZ  PHY Data Zero Symbol
PHS  PHY Header Symbol
PHY  Physical Layer
PHZ  PHY Header Zero Symbol
PPDU PHY Protocol Data Unit
PRM  Primary Bit
PRMB  Preamble
PSDU PHY Service Data Unit
PSK  Phase Shift Keying
RC  Repetition Code
RES  Reserved
RN  Relaying Node
RZCO Reference Zero-Crossing Offset
s-MN  Secondary Master Node
SCA  Scrambling Code Array
SCL  Scrambling Code Length
SN  Slave Node
SYNC  Synchronization Sequence
SYNCR  Synchronization Sequence Reference Symbols
SYNCS  Synchronization Sequence Symbols
S_CIN Slave Channel Identification Number
S_FXENA Slave Frame Forwarding Enable
S_FXS Slave Frame Forwarding Sector
S_MAx  Slave Multicast Addresses
S_LA  Slave Link-Address
TB  Tail Bits
TLA  Temporary Link Address
TM  Transmit Mode
TNCW Total Number of Contention Windows
TNS  Total Number of Symbols
TS  Training Sequence
TSS  Training Sequence Symbol
TSA  Training Sequence Array
TSL  Training Sequence Length

4 General description
Layers 1 and 2 transport the higher layer messages between the nodes of a low voltage
distribution network. Layer 1 (physical layer, PHY) generates a physical signal that is
sent over the medium. The data link layer (DLL, layer 2) is split up into three sub-layers:
medium access control sub-layer (MAC, sub-layer 2a), logical link control sub-layer

(LLC, sub-layer 2b) and convergence sub-layer (CL, sub-layer 2c). The first two sub-
layers of the data link layer perform the formatting of the frames, handle channel access
and frame forwarding procedures, provide data integrity checks and are responsible for
addressing, segmentation and message retransmission. The convergence layer
provides adaptation to the specific higher layer protocol and may be transparent. The
convergence layer is not part of this document but is defined in the profile specification.
The convergence sub-layer provides a mapping between the primitives that are used by
the higher layer entity, and the primitives of the logical link control sub-layer. Layer 2
also provides functionality of multiplexing and prioritization between different higher
layer entities or applications (within a network node) and layer-2 networking.
Furthermore, multiplexing of different protocol elements with DLMS/COSEM elements is
specified herein. The structure of the lower layer PLC profile is shown in Figure 1.

Higher Layers 1 Higher Layers N
Higher Layers 2
●●●
(Layers 3 to 7) (Layers 3 to 7)
(Layers 3 to 7)
Convergence Sub-Layer
(Sub-Layer 2c)
CLC/TS 50590
Logical Link Control Sub-Layer
(Sub-Layer 2b)
Medium Access Control Sub-Layer
(Sub-Layer 2a)
Physical Layer
(PHY, Layer 1)
Figure 1 – Layers of AMC-SS profile
Information between layers is exchanged via primitives (see Figure 2). The following
primitives are used for the communication between the logical link control sub-layer and
the convergence sub-layer: DL_data.request, DL_data_identifier.confirm,
DL_data.indication, DL_data.response, DL_data.confirm, DL_data_ack.response,
DL_data_ack.confirm and DL_control.indication. For communication between the data
link layer (LLC + MAC) and the physical layer the primitives P_data.request and
P_data.indication are used.
.
– 11 – CLC/TS 50590:2015
DL_control.indication DL_control.indication
DL_data.request
P_data.request
P_data.indication
DL_data_identifier.confirm DL_data.indication
Physical
DL_data.response
medium
DL_data_ACK.response
P_data.request
P_data.indication
DL_data.confirm
DL_data_ACK.confirm
CL LLC,MAC PHY PHY LLC,MAC CL
Figure 2 – Primitives
5 PHY layer specification
5.1 Overview
To generate physical signals, the AMC-SS physical layer uses a multi-carrier spread
spectrum technique in combination with Differential Phase Shift Keying (DPSK) and
forward-error-correction (FEC) coding.
This technique provides the following advantages:
− Robustness against time–frequency-selective fading;
− Robustness against pulse and narrowband interference, pulsating non-gaussian
noise and combinations of them;
− Robustness against unwanted intermodulation effects;
− Lower linearity requirements for the analogue front end;
− High power efficiency as a result of low peak-to-average power ratio of the
transmitted signal;
− Good electromagnetic compatibility between neighbouring systems.
The Figure 3 shows the block diagram of different data processing steps performed by
the physical layer during the transmission of a PHY protocol data unit (PPDU).

FEC
PSK/
encoder
DPSK
Carrier
mapper
frequency Modulator
mapper
FEC Inter-
encoder leaver
Figure 3 – PHY layer processing steps during PPDU transmission
Neither FEC-encoding nor interleaving is performed on the training sequence (TS). The
bits of the synchronisation sequence (SYNC), the PHY header and PHY data are
encoded with a FEC code. Encoded bit-sequences of the PHY header and PHY data are
additionally interleaved. The training sequence and the encoded and interleaved bit
sequences are mapped to the carrier phase angels depending on a PSK or a DPSK
scheme and then to the carrier frequencies. The result of the PSK/DPSK and carrier
frequency mapping is a sequence of unmodulated symbols containing modulation
parameter. In the modulator these symbols are modulated and combined to a transmit
signal, which is coupled into the physical channel – power-line.
The PHY layer processing steps during the reception of the PPDU are implementation
specific and out of scope of this specification.
TS
SYNC
Transmit
signal
PHY Header,
PHY Data
PPDU
Preamble
– 13 – CLC/TS 50590:2015
5.2 PHY protocol data unit
5.2.1 PPDU structure
5.2.1.1 General
The PPDU (i. e. PHY frame) consists of the preamble, the PHY header and the PHY
data field. The preamble contains a training sequence (TS) and the synchronisation
sequence SYNC. The PSK encoded elements of the TS are defined by the parameter
TSL and the parameter array TSA (see Annex D).
Figure 4 below shows the bit-oriented structure of the PPDU (except training sequence),
which is defined in Table 1 below.
SYNC TM HTB PSDU TB
Figure 4 – Bit-oriented PPDU structure without TS
The bits of the PPDU (except TS) are numbered from 0 to L+28, where L is the length of
PSDU in bits. In the following these bits are denoted as d , d , …, d , …, d .
0 1 k L+28
Table 1 – PPDU structure without TS
Field Bit number Bits Name Value
SYNC 10 to 0 11 Synchronisation bit 0x247 - allowed value;
sequence 0x000 to 0x246 - unused;
0x248 to 0x7FF - unused.
a
TM 15 to 11 5 PHY data transmit 0x00 to. 0x14 - TM0 to TM20;
a
mode number
0x15 to 0x1F – reserved for
future use.
res. 16 1 Reserved bit for 0x0 - allowed value;
future use 0x1 - not allowed.
HTB 22 to 17 6 PHY header tail bits 0x00     - allowed value;
0x01 to 0x3F - not allowed.
a
PSDU 23 to L+22 L PHY service data PSDU = MPDU (cf. Table 9).
unit
b b
TB L+23 to L+28 6 PHY data tail bits 0x00     - allowed value;
0x01 to 0x3F - not allowed.
a
L is the length of PSDU in bits. The value of L is handed over to the PHY layer from MAC sub-layer
together with MPDU = PSDU and the value of TM using the primitive P_data.request defined in
Sub-section 5.5.
b
PPDU does not contain TB if TM = 16 to 20
For the transmission of the TS, SYNC, PHY header and PHY data different transmit
modes are used (see Table 2 below).
Figure 5 shows symbolically the transmit signal (corresponding transmitted PHY frame)
consisting of overlapped modulated symbols at the output of the modulator (cf. Figure 7
and Figure 8). The detailed PHY frame structure is described in the following sub-
sections.
0 10 11 15
16 17 22 23
(L bits)
0 10 0 4 0 0 5 0
0 5
Preamble
PHY Header
PHY Data
Part of PPDU
PHY Data PHY Header Preamble
res.
L-1 L+22
L+23
L+28
ITD /(IFI) (IFI)
● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●

Figure 5 – Structure of transmit signal (PHY frame) consisting of overlapped modulated symbols

Preamble PHY Header
PHY Data
TSS
TSS DT of TS
TSSLTS-1
SYNCR
SYNCR DT of SYNC
SYNCR
SYNCS
SYNCS DT of SYNC
SYNCS7
SYNCS
SYNCS
SYNCS
PHS
PHS DT of PHY header
PHS7
PHS
PHS
PHS
PHZ
DT of PHY header
PHZ
PDR0
PDR DT of PHY data
PDR
N-1
PDS
DT of PHY data
PDS1
PDS
PDS8
PDS
PDS
M-2
PDS
M-1
DT of PHY data
PDZ0
PDZ
– 15 – CLC/TS 50590:2015
5.2.1.2 Preamble
Each PHY frame starts with the preamble, which is used for bit and block
synchronization and for automatic gain control (AGC) adaptation. As shown in Figure 5,
the preamble starts with a training sequence (TS) of symbols TSS to TSS , followed
0 LTS-1
by reference symbols SYNCR to SYNCR and symbols SYNCS to SYNCS of the
0 7 0 87
synchronisation sequence.
The modulated TS symbols TSS to TSS are generated using the corresponding
0 LTS-1
parameters from Table 2 and the parameter TLS and TSA (see. Annex D), that are
defining the PSK encoding of the TS. Note that neither FEC-encoding nor interleaving is
performed on the TS (see Table 2).
The modulated symbols of the synchronisation sequence SYNCS , i = 0, …, 87 are
i
generated by repetition encoding and differential modulation of SYNC, which is defined
as the following bit sequence (cf. Table 1):
SYNC = (d , …, d ) = (1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0).
0 10
The symbols SYNCR to SYNCR serve as initial reference symbols for differential
0 7
modulation of the first eight symbols SYNCS to SYNCS respectively. The initial carrier
0 7
frequency phases of the modulated symbols SYNCR to SYNCR are defined by the
0 7
parameter array RPA0 (see Annex D).
5.2.2 PHY header
The PHY header starts with the bits of the transmit mode (TM) field. These bits are
denoted as d , d , …, d They indicate the number of the transmission mode, which
11 12 15
is used to transmit data contained within the field PHY Data. The bits d to d (fields
11 22
TM, Res. and HTB) of the PHY header are convolutionally encoded with the rate 1/8,
which is defined in the sub-section 5.3.2.3. The purpose of the zero PHY header tail bits
(HTB) d to d , is to return the encoder to its initial state. The encoded bit sequence is
17 22
interleaved and mapped to the phase angels and then to the carrier frequencies
according to the DBPSK rule and the frequency mapping scheme FMS1 respectively.
The preamble symbols SYNCS to SYNCS are used as references for differential
80 87
modulation of the first eight symbols PHS to PHS respectively.
0 7
At the end of the PHY header, eight zero symbols PHZ to PHZ are inserted in order to
0 7
ensure that the modulated symbols of the PHY header and PHY data do not overlap in
time. This is necessary because the PHY data may be transmitted in a different
transmission mode than the PHY header. A zero symbol is a symbol which consists of
all zero samples for the duration of T , where T is defined in Table 2 (cf. Figure 8).The
S S
transmit mode for the PHY data is defined by the field TM in the PHY header and can
be any of transmit modes TM0 to TM20 from Table 2. The parameter of the transmit
mode used for the PHY header are the same as of the PHY data transmit mode TM0 (cf.
Table 2).
5.2.3 PHY data
The PHY-data field always contains a PHY service data unit (PSDU). Furthermore, for
transmit modes TM0 to TM16, it also contains six zero tail bits (TB) in order to return
the convolutional encoder to its initial state. For TM16 to TM20 there is no TB field
because a repetition block code is used, see Table 2. It needs to be noted that the total
size of PSDU can vary between 96 bits and 2152 bits.
As explained in the previous chapter, the transmit mode of the PHY data is defined by
the TM field of the PHY header.

The bits d up to d (fields PSDU and, if available, TB) of the PHY data are FEC
23 L+28
encoded. The encoded bit sequence is interleaved and mapped to the phase angels and
then to the carrier frequencies according to the used DPSK rule and the frequency
mapping scheme respectively.
The first N symbols of PDR to PDRN-1 serve as initial reference symbols for differential
modulation of the corresponding carrier of the first N symbols PDS to PDS N-1
respectively. The number N is equal to the length of the frequency hopping cycle, which
is the number of modulated symbols contained therein (Nfhc). It depends on the number
of used carrier frequencies (Ncf) and the number of simultaneously used carriers (Nsuc)
in the PHY data transmission mode. The value of Nfhc is defined as:
Nfhc = Ncf / Nsuc = 1, 3, 5, 7 or 8 (cf. Table 2). The initial carrier frequency phases of
the modulated symbols PDR to PDR to PDRN-1 , N = 1, 3, 5, 7 or 8 are user-specific.
0 0
At the end of the PHY data two additional zero symbolsPDZ and PDZ are transmitted
0 1
(see zero symbol definition in Sub-section 5.2.2). This ensures a complete transmission
of the previous symbols PDS and PDS (see Figure 8).
M-2 M-1
5.3 PHY frame transmission
5.3.1 General
The PHY layer of the AMC-SS allows the transmission of the PSDU using one of the 21
transmit modes TM0 to TM20. They differ from each other by the used FEC code, type
of DPSK, frequency hopping scheme etc. (see Table 2 below), allowing a flexible trade-
off between bit-rate and noise immunity. This is necessary for the adaptation of the
MAC layer to the conditions of the communication channel.
The TS and SYNC of the preamble (PRMB) and the PHY header are transmitted in the
predefined transmit modes. The transmit mode for the PHY data field is determined by
the MAC entity using the primitive P_data.request (see Sub-section 5.5). The number of
this mode is transmitted in the TM field of the PHY header to indicate it to the receiver
for a correct reception of the PHY data.
The following Table 2 contains the parameters of the transmit modes for the preamble,
PHY header and PHY data field. The transmit modes TM0 to TM15 are arranged by
increasing data bit rate. The additionally defined transmission modes TM16 to TM20
use more simple transmission schemes allowing a low-cost implementation of the
receiver.
The PHY layer processing steps during the transmission of the PHY frame as shown in
Figure 3 are described in following sub-sections.

– 17 – CLC/TS 50590:2015
Table 2 – Parameter of preamble, PHY header and PHY data transmit modes

4800 39.0 89.5 6.764 8 1 8 FMS0 72 154 W0 PSK -- 1 --
TS
600 39.0 89.5 6.764 8 1 8 FMS1 72 154 W0 DBPSK RC 1/8 --
SYNC
600 39.0 89.5 6.764 8 1 8 FMS1 72 154 W0 DBPSK CONV 1/8 96
PHY header
600 39.0 89.5 6.764 8 1 8 FMS1 72 154 W0 DBPSK CONV 1/8 96
TM0
850 41.5 88.7 10.850 5 1 5 FMS2 58 128 W1 DBPSK CONV 1/7 120
TM1
1200 39.0 89.5 6.764 8 1 8 FMS1 72 154 W0 DQPSK CONV 1/8 192
TM2
1600 39.0 89.5 6.764 8 1 8 FMS1 72 154 W0 DQPSK CONV 1/6 192
TM3
2400 41.5 88.7 10.850 5 1 5 FMS2 58 128 W1 DQPSK CONV 1/5 240
TM4
3200 41.5 88.7 10.850 8 1 8 FMS1 72 154 W0 DQPSK CONV 1/3 192
TM5
TM6 4000 41.5 88.7 10.850 5 1 5 FMS2 58 128 W1 DQPSK CONV 1/3 240
TM7 4800 39.0 89.5 6.764 8 1 8 FMS1 72 154 W0 DQPSK CONV 1/2 180
TM8 6000 41.5 88.7 10.850 5 1 5 FMS2 58 128 W1 DQPSK CONV 1/2 150
TM9 8000 44.2 88.7 2.7125 16 2 8 FMS3 58 128 W1 DQPSK CONV 1/3 224
9000 41.5 88.7 10.850 5 1 5 FMS2 58 128 W1 D8PSK CONV 1/2 225
TM10
12000 44.2 88.7 2.7125 16 2 8 FMS3 58 128 W1 DQPSK CONV 1/2 224
TM11
18000 44.2 88.7 2.7125 16 2 8 FMS3 58 128 W1 D8PSK CONV 1/2 336
TM12
27000 41.5 88.7 5.425 9 3 3 FMS4 58 128 W1 D8PSK CONV 1/2 486
TM13
32000 46.9 88.7 5.425 8 8 1 FMS5 128 128 W2 D8PSK CONV 1/2 480
TM14
64000 33.3 88.7 2.7125 20 20 1 FMS6 163 179 W3 D8PSK CONV 1/2 600
TM15
600 39.0 89.5 6.764 8 1 8 FMS1 72 154 W0 DBPSK RC 1/8 128
TM16
900 39.6 90.0 7.773 7 1 7 FMS7 55 134 W4 DBPSK RC 1/7 98
TM17
1200 41.5 88.7 10.850 5 1 5 FMS2 58 128 W1 DBPSK RC 1/5 50
TM18
1800 39.6 90.0 7.773 7 1 7 FMS7 55 134 W4 DQPSK RC 1/7 192
TM19
3000 40.1 87.4 10.629 5 1 5 FMS8 46 98 W5 DQPSK RC 1/5 100
TM20
PHY data PRMB
Nominal data bit
rate
bit/s
Lower -3dB-
frequency of
TX-signal
kHz
Upper -3dB-
frequency of
TX-signal
kHz
Carrier frequency
spacing
kHz
Number of carrier
frequencies
Number of
simultaneously
used carriers
Frequency
hopping cycle
length
symbols
Frequency
mapping scheme
(see Annex A)
Symbol-to symbol
shift DT
(samples)
Symbol duration
T
S
(samples)
Window function
W (see Annex A)
Type of
modulation
Forward error
correction code
Code rate
Interleaving block
length L (see
INTL
also A.2)
bits
5.3.2 Forward error correction encoding
5.3.2.1 General
Two types of FEC are used by AMC-SS based on repetition block codes (RC) and
convolutional codes (CONV). The bits d to d of the synchronisation sequence SYNC
0 10
are encoded using the repetition code with code rate 1/8. The PHY header bits d to d
11 22
are encoded by the rate 1/8 convolutional encoder with constraint length K = 7, see
Table 3. Depending on the used transmission mode, the PHY data bits are encoded by
convolutional encoder (TM0 to TM15) or repetition encoder (TM16 to TM20). If
repetition encoder is used, the PHY data block does not contain tail bits.
5.3.2.2 Repetition encoding
The repetition encoder uses the repetition block code (N,1,N) with a rate of 1/N, with N
being the number of used carrier frequencies (Ncf). The encoder repeats every bit d of
k
the SYNCS or PHY data N times creating the code word of encoded bits
C =c , .,c , ., c , n= 0.N−1, where C is defined as:
k k ,0 k ,n k ,N−1 k

c = 0,n= 0,.N−1 d = 0

k ,n k
C =

k
c = 1,n= 0,.N−1 d = 1

k ,n k

The resulting encoded bits are denoted as c=c , i= N⋅k+n, n= 0,1,, N−1.
i k ,n
5.3.2.3 Convolutional encoding
The six convolutional encoders that are based on binary convolutional codes with
constraint length K=7 and code rates 1/N = 1/8, 1/7, 1/6, 1/5, 1/3 and 1/2 that are used
for different transmission modes (see Table 2). The general structure of the
convolutional encoder is shown in Figure 6.
c
k,0
d
k
-1 -1 -1 -1 -1 -1
Z Z Z Z Z Z
c
k,1
(c )
k,N-1
Figure 6 –General structure of a convolutional encoder with constraint length 7,
used in this particular example (solid connections) for rate ½ encoder
. . .
. . .
– 19 – CLC/TS 50590:2015
Before the encoding of the PHY header, the initial state of the shift register in the
encoder is zero. The code construction of each rate 1/N convolutional encoder is
defined by the code connection vectors listed in Table 3.
Table 3 – Code connection vectors for convolutional encoder
Code rate = 1/N
1/8 1/7 1/6 1/5 1/3 1/2
CCV 1101011 1110101 1111011 1111101 1011011 1111001
CCV 1001001 1100111 1101001 1011001 1100101 1011011
CCV 1110101 1111011 1011101 1011101 1111101 --
CCV 1111011 1011101 1011101 1011101 -- --
CCV 1011101 1011101 1110011 1100111 -- --
CCV 1011101 1100111 1011111 -- -- --
CCV 1100111 1011111 -- -- -- --
CCV 1011111 -- -- -- -- --
Depending on the code connection vectors, the shift register taps are connected to N
modulo2-summer generating the code word C = (c , .,c , ., c ),
k k ,0 k ,n k ,N−1
n= 0,1,, N−1 from the bit d at the input of the encoder and bits d to d in the
k k-1 k-6
shit register stages. The solid connections in the encoder structure in Figure 6
correspond to the rate ½ encoder defined in Table 3. The dashed connections
symbolise possible code connections in the encoder for other code rates.
The code words from the output of the encoder are serialised into a stream of encoded
bits c=c , i= N⋅k+n, n= 0,1,, N−1.
i k ,n
With the shift of the last header tail bit d or the last tail bit d into the register, the
22 L+28
encoder returns to its initial state finishing the encoding of the PHY header ore PHY
data respectively (i.e., c is the last encoded bit of the PHY header). For encoding of
the PHY data, the convolutional encoder shall be reinitialised according to a used
transmit mode and with all zero in the shift register.
5.3.3 Interleaving
The encoded bits of PHY header and PHY data are segmented into input blocks of the
length L (sc ,.,sc ,.,sc ), where sc =c ,.,sc =c . Padding bits
INTL
0 i L −1 0 i L −1 i+L −1
INTL INTL INTL
shall be added, if needed, to fill up the final block. Padding bits are generated by a
pseudo-noise sequence generator shown in Figure 12 starting with all ones as initial
state.
In the input block an intra-block interleaving is performed. The result is an output block
(oc ,.,oc ,.,oc ) containing the i
...