IEC 62586-2:2017/AMD1:2021

IEC 62586-2 ®
Edition 2.0 2021-09
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
AM ENDMENT 1
AM ENDEMENT 1
Power quality measurement in power supply systems –
Part 2: Functional tests and uncertainty requirements

Mesure de la qualité de l'alimentation dans les réseaux d'alimentation –
Partie 2: Essais fonctionnels et exigences d'incertitude

IEC 62586-2:2017-03/AMD1:2021-09(en-fr)

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IEC 62586-2 ®
Edition 2.0 2021-09
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
AM ENDMENT 1
AM ENDEMENT 1
Power quality measurement in power supply systems –

Part 2: Functional tests and uncertainty requirements

Mesure de la qualité de l'alimentation dans les réseaux d'alimentation –

Partie 2: Essais fonctionnels et exigences d'incertitude

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 17.220.20 ISBN 978-2-8322-9930-2

– 2 – IEC 62586-2:2017/AMD1:2021
© IEC 2021
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
POWER QUALITY MEASUREMENT IN POWER SUPPLY SYSTEMS –

Part 2: Functional tests and uncertainty requirements

AMENDMENT 1
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and
in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports,
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preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with
may participate in this preparatory work. International, governmental and non-governmental organizations liaising
with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for
Standardization (ISO) in accordance with conditions determined by agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
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any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter.
5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
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indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this document may be the subject of patent
rights. IEC shall not be held responsible for identifying any or all such patent rights.
Amendment 1 to IEC 62586-2:2017 has been prepared by IEC technical committee 85:
Measuring equipment for electrical and electromagnetic quantities.
The text of this amendment is based on the following documents:
FDIS Report on voting
85/770/FDIS 85/795/RVD
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this Amendment is English.

© IEC 2021
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/standardsdev/publications/.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct understanding
of its contents. Users should therefore print this document using a colour printer.

_____________
5.1.4 Single "power-system influence quantities"
c d
Replace in Table 4 the footnotes and with:
c
This signal represents a crest factor of 2 and applies to voltage signals.
d
This signal represents a crest factor of 3 and applies to current signals.

6.2.2.2 Variations due to single influence quantities
Replace Subclause 6.2.2.2 by the following:
Each test shall last at least 1 s.
No. Target of the test Testing points Complementary test Test criterion (if
according to Table 3 conditions according test is applicable)
to Table 4
A2.3.1 Measure influence of P3 for voltage S1 for frequency TC10/12(unc)
frequency on measurement magnitude
S3 for frequency
uncertainty (for further
calculations as required in
8)
A2.3.2 Measure influence of P3 for voltage S1 for harmonics TC10/12(unc) on
harmonics on measurement magnitude ch1 compared to a
uncertainty (for further reference voltage
calculations as required in
8)
6.4.1 General
Clarification about units of y axis; replace Figure 1 by the following:

– 4 – IEC 62586-2:2017/AMD1:2021
© IEC 2021
Figure 1 – Overview of test for dips according to test A4.1.1

© IEC 2021
Clarification about units of y axis; replace Figure 2 by the following:

Figure 2 – Detail 1 of waveform for test of dips according to test A4.1.1
Replace Figure 3 by the following (clarification about hysteresis):

Figure 3 – Detail 2 of waveform for tests of dips according to A4.1.1

– 6 – IEC 62586-2:2017/AMD1:2021
© IEC 2021
In Figure 4, correction of values, by expressing them in % of U and by adding a significant
din
digit. Replace Figure 4 by the following:
U U U U U U U U
rms(½) rms(½) rms(½) rms(½) rms(½) rms(½) rms(½) rms(½)
N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7
100 % U 70,7 % U 0 % U 0 % U 0 % U 63,6 % U 90 % U 90 % U
din din din din din din din din

U U U U U U U U
rms(½) rms(½) rms(½) rms(½) rms(½) rms(½) rms(½) rms(½)
N + 8 N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15
90 % U 92 % U 94 % U 94 % U 94 % U 94 % U 94 % U 94 % U
din din din din din din din din

Figure 4 – Detail 3 of waveform for tests of dips according to test A4.1.1
In Figure 5, correction of signal level to match test point P3 for dips/interruptions, and correction
of scale now expressed in % of U . Replace Figure 5 by the following:
din
Figure 5 – Detail 1 of waveform for test of dips according to test A4.1.2

© IEC 2021
In Figure 6, correction of signal level to match test point P3 for dips/interruptions, and correction
of scale now expressed in % of U . Replace Figure 6 by the following:
din
Figure 6 – Detail 2 of waveform for tests of dips according to test A4.1.2
In Figure 7, correction of the scale, now expressed in % of U . Replace Figure 7 by the
din
following:
Figure 7 – Detail 1 of waveform for test of swells according to test A4.1.2

– 8 – IEC 62586-2:2017/AMD1:2021
© IEC 2021
In Figure 8, correction of the scale, now expressed in % of U . Replace Figure 8 by the
din
following:
Figure 8 – Detail 2 of waveform for tests of swells according to test A4.1.2
Update of the scale in Figure 9 as follows:

Figure 9 – Sliding reference voltage test
6.13 Rapid voltage changes (RVC)
Replace the entire Subclause 6.13 by the following:

© IEC 2021
6.13 Rapid voltage changes (RVC)
6.13.1 RVC parameters and evaluation
An RVC event is characterized by four parameters:
• start time,
• duration,
,
• ∆U
max
• ∆U .
ss
The start time of an RVC event shall be time-stamped with the time that the "voltage-is-steady-
state" logic signal became false and initiated the RVC event.
The event duration of an RVC event is 100/120 half cycles shorter than the duration that the
"voltage-is-steady-state" logic signal is false.
The ∆U of one RVC event is the maximum absolute difference between any of the U
max rms(½)
values during the RVC event, and the final arithmetic mean 100/120 U value just prior to
rms(½)
the RVC event. For polyphase systems, the ∆U is the largest ∆U on any channel.
max max
The ∆U of one RVC event is the absolute difference between the final arithmetic mean
ss
100/120 U value just prior to the RVC event, and the first arithmetic mean 100/120 U
rms(½) rms(½)
value after the RVC event (at the time where the "voltage-is-steady-state" signal becomes true).
For polyphase systems, the ∆U is the largest ∆U on any channel.
ss ss
Figure 18 – Example of RVC event

– 10 – IEC 62586-2:2017/AMD1:2021
© IEC 2021
6.13.2 General
6.13.2.1 General intents
The voltage test signals implemented are defined in this Subclause 6.13. The tests focus on
showcasing the 5 general scenarios of how RVC events could be detected, whilst placing
particular emphasis on the following features: amplitude, duration, start time and end time, poly-
phase system, etc.
The test results and the relevant analysis are provided here as well.
The test cases below are designed for both Class A and Class S. If U (one cycle) is
rms(1)
selected for Class S RVC, then 100/120 half cycles shall be replaced throughout the event
evaluation with 50/60 full cycles.
6.13.2.2 Uncertainty of results
Magnitude measurement uncertainty:
– Class A: The measurement uncertainty shall not exceed ±0,2 % U ;
din
– Class S: The measurement uncertainty shall not exceed ±1,0 % U .
din
Duration measurement uncertainty:
– Class A: ±1 cycle, commencement uncertainty (half cycle) plus the conclusion uncertainty
(half cycle).
– Class S: If U is used, then the uncertainty is ±1 cycle. If U is used, then the
rms(1/2) rms(1)
uncertainty is ±2 cycles.
6.13.2.3 Setup values
– RVC threshold (5,0 %)
– RVC hysteresis (2,5 %)
– U threshold = 90,0 % U
dip din
– U threshold = 110,0 % U
swell din
6.13.2.4 Type of functional tests
The following types of tests are specified hereafter:
– No RVC tests (slow change, small change, big change-dips/swells);
– RVC setup test (threshold, hysteresis);
– RVC parameters test (start time, ΔU ΔU , duration);
max, ss
– RVC polyphase test (start time, ΔU ΔU , duration);
max, ss
– VSS voltage-is-steady-state test rule: all the immediately preceding 100/120 U values
rms(½)
(1 s) remain within an RVC threshold, reduced by hysteresis, from the arithmetic mean of
those 100/120 U values.
rms(½)
NOTE Only negative RVC events and only when the initial VSS = 100 % U have been specified in these tests.
din
However, the same results should be achieved also for positive RVC events and initial VSS is different from
100 % U .
din
All tests are rather quality than quantity tests. Due to uncertainty in simulation and
measurements, uncertainty of ±2 half cycles are accepted.

© IEC 2021
6.13.3 "No RVC" tests
6.13.3.1 Test 1
No. Target of the test Testing points Complementary test Test criterion (if
according to Table 3 conditions test is applicable)
A13.1.1 To verify that no RVC event P4 for frequency Test shall be conducted No RVC shall be
will be detected if the voltage according to Table 8 detected
magnitude changes too
slowly.
See NOTE
NOTE An RMS voltage is in a steady-state condition if all the immediately preceding 100 U values (1 s) remain
rms(½)
within RVC threshold from the arithmetic mean of those 100 U values. The validity of this test for 60 Hz networks
rms(½)
is under consideration.
Table 8 – Specification of test A13.1.1
a
t = 0 t = 100 half t = 300 half t = 400 half t = 600 half t
Test definition 0 1 2 3 4 end
cycles cycles cycles cycles
(start test)
(start ramp (start ramp up)
down)
U 100 % U 100 % U 92 % U 92 % U 100 % U 100 % U
din din din din din din
vss
a
This sequence of test is described in Figure 19; theoretical limits are described in Figure 20.

Figure 19 – Test A13.1.1 waveform

– 12 – IEC 62586-2:2017/AMD1:2021
© IEC 2021
Figure 20 – Test A13.1.1 waveform with RVC limits and arithmetic mean at 50 Hz
6.13.3.2 Test 2
No. Target of the test Testing points Complementary test Test criterion (if
according to Table 3 conditions test is applicable)
A13.1.2 To verify that no RVC event P4 for frequency Test shall be conducted No RVC shall be
will be detected if the voltage according to Table 9 detected
magnitude changes less than
the threshold.
See NOTE
NOTE An RMS voltage is in a steady-state condition if all the immediately preceding 100 U values (1 s) remain
rms(½)
within RVC threshold from the arithmetic mean of those 100 U values. The validity of this test for 60 Hz networks
rms(½)
is under consideration.
Table 9 – Specification of test A13.1.2
Test t = 0 t = 100 half t = 150 half t N.A. N.A.
end
0 1 2
a
definition
cycles cycles
(start test)
(step down) (step up)
U 100 % U 97 % U 100 % U 100 % U N.A. N.A.
din din din din
vss
a
This sequence of test is described in Figure 21; theoretical limits are described in Figure 22.

© IEC 2021
Figure 21 – Test A13.1.2 waveform

Figure 22 – Test A13.1.2 waveform with RVC limits and arithmetic mean at 50 Hz

– 14 – IEC 62586-2:2017/AMD1:2021
© IEC 2021
6.13.3.3 Test 3
No. Target of the test Testing points Complementary test Test criterion (if
according to Table 3 conditions test is applicable)
A13.1.3 To verify that if a dip/swell is P4 for frequency Test shall be conducted No RVC shall be
detected during an RVC according to Table 10 detected
event, including the disabled
One dip shall be
100/120 half cycles, then the
detected
RVC event would be
discarded and recorded as a
Dip duration 80: half
dip/swell.
cycles ± 2 half
cycles
See NOTE
NOTE If a voltage dip or voltage swell is detected during an RVC event, including the disabled 100 half cycles,
then the RVC event is discarded because the event is not an RVC event. It is a voltage dip or voltage swell. The
validity of this test for 60 Hz networks is under consideration.

Table 10 – Specification of test A13.1.3
a
t = 0 t = 100 half t = 170 half t = 250 half t N.A.
Test definition end
0 1 2 3
cycles cycles cycles
(start test)
st nd
(step up)
(1 step down) (2 step down)
U 100 % U 93 % U 85 % U 100 % U 100 % U N.A.
din din din din din
vss
a
This sequence of test is described in Figure 23; theoretical limits are described in Figure 24.

Figure 23 – Test A13.1.3 waveform

© IEC 2021
Figure 24 – Test A13.1.3 waveform with RVC limits and arithmetic mean at 50 Hz
6.13.4 "RVC threshold and setup" test
No. Target of the test Testing points Complementary test Test criterion (if
according to Table 3 conditions test is applicable)
A13.2.1 To verify that the above P4 for frequency Test shall be conducted One RVC shall be
mentioned RVC setup values according to Table 11 detected:
as specified in 6.13.2.3 are
Start: 100 half
valid.
cycles
RVC threshold cannot be
ΔU : 7,0 % U
exactly tested, but to verify it max din
is TRUE when RVC
ΔU : 7,0 % U
ss din
ΔU > RVC threshold.
max
Duration: 0 to 2 half
cycles
Table 11 – Specification of test A13.2.1
a
t = 0 t = 100 half t N.A. N.A. N.A.
Test definition end
0 1
cycles
(start test)
(step down)
U 100 % U 93 % U 93 % U N.A. N.A. N.A.
din din din
vss
a
This sequence of test is described in Figure 25; theoretical limits are described in Figure 26.

– 16 – IEC 62586-2:2017/AMD1:2021
© IEC 2021
Figure 25 – Test A13.2.1 waveform

Figure 26 – Test A13.2.1 waveform with RVC limits and arithmetic mean at 50 Hz

© IEC 2021
6.13.5 "RVC parameters" test
No. Target of the test Testing points Complementary test Test criterion (if test
according to Table 3 conditions is applicable)
A13.3.1 To verify that the above P4 for frequency Test shall be One RVC detected:
mentioned RVC parameters conducted according
Start: 100 half cycles
are valid. to Table 12
ΔU : 8,0 % U
See NOTE max din
ΔU : 2,0 % U
ss din
Duration: 49 half
cycles ± 2 half cycles
NOTE The following parameters can be tested:
– RVC start time stamp: an RVC event is time-stamped with the time at which the "voltage-is-steady-state" logic
signal became false and initiated the RVC event.
– RVC ΔU is the maximum absolute difference between any of the U values during the RVC event and the
max rms(½)
final arithmetic mean 100/120 U value just prior to the RVC event. For polyphase systems, the ΔU is the
rms(½) max
largest ΔU on any channel.
max
– RVC ΔU : is the absolute difference between the final arithmetic mean 100/120 U value just prior to the
ss rms(½)
RVC event and the first arithmetic mean 100/120 U value after the RVC event (at the time where the
rms(½)
"voltage-is-steady-state" signal becomes true). For polyphase systems, the ΔU is the largest ΔU on any
ss ss
channel.
– RVC duration: is 100/120 half cycles shorter than the length of time during which the "voltage-is-steady-state"
logic signal is false.
Table 12 – Specification of test A13.3.1
Test t = 0 t = 100 half t = 150 half t
end
0 1 2
a
definition
cycles cycles
(start test)
(step down) (step up)
U 100 % U 92 % U 98 % U 98 % U
din din din din
vss
a
This sequence of test is described in Figure 27; theoretical limits are described
in Figure 28.
– 18 – IEC 62586-2:2017/AMD1:2021
© IEC 2021
Figure 27 – Test A13.3.1 waveform

Figure 28 – Test A13.3.1 waveform with RVC limits and arithmetic mean at 50 Hz

© IEC 2021
6.13.6 "RVC polyphase" test
No. Target of the test Testing points Complementary test Test criterion (if test
according to Table 3 conditions is applicable)
A13.4.1 To verify that in a polyphase P4 for frequency Test shall be One polyphase RVC
system, RVC detection conducted according shall be detected:
depends on the combined to Table 13
Start: 120 half cycles
VSS (voltage-is-steady-state)
logic signal. This signal is
ΔU : 8,0 % U
max din
the logical AND of the
"voltage-is-steady-state"
ΔU : 2,0 % U
ss din
logic signal of each voltage
channel.
Duration: 59 half
cycles ± 2 half cycles
See NOTE
NOTE For polyphase systems, the combined "voltage-is-steady-state" logic signal is the logical AND of the
"voltage-is-steady-state" logic signal of each voltage channel. The following parameters can be tested:
– RVC start time stamp: an RVC event is time-stamped with the time at which the combined "voltage-is-steady-
state" logic signal became false and initiated the RVC event.
– RVC ΔU : For polyphase systems, the ΔU is the largest ΔU on any channel.
max max max
– RVC ΔU : For polyphase systems, the ΔU is the largest ΔU on any channel.
ss ss ss
– RVC duration: the event is 100/120 half cycles shorter than the length of time during which the combined "voltage-
is-steady-state" logic signal is false.

Table 13 – Specification of test A13.4.1
a
t = 0 t = 100 half t = 120 half t = 140 half t = 160 half t = 180 half
Test definition
0 1 2 3 4 5
cycles cycles cycles cycles cycles
(start test)
U 100 % U 97 % U 97 % U 97 % U 97 % U 97 % U
din din din din din din
vss phase 1
U 100 % U 100 % U 92 % U 92 % U 92 % U 100 % U
din din din din din din
vss phase 2
U 100 % U 100 % U 100 % U 92 % U 98 % U 98 % U
din din din din din din
vss phase 3
a
t = 200 half tend N.A. N.A. N.A. N.A.
Test definition
cycles
U 100 % U 100 % U N.A. N.A. N.A. N.A.
din din
vss phase 1
U 100 % U 100 % U N.A. N.A. N.A. N.A.
din din
vss phase 2
U 98 % U 98 % U N.A. N.A. N.A. N.A.
din din
vss phase 3
a
This sequence of test is described in Figure 29; theoretical limits are described in Figure 47.

– 20 – IEC 62586-2:2017/AMD1:2021
© IEC 2021
Figure 29 – Test A13.4.1 waveform at 50 Hz

Figure 47 – Test A13.4.1 waveform with RVC limits and VSS at 50 Hz

© IEC 2021
6.13.7 "Voltage is in steady-state condition" tests
6.13.7.1 Test 1 (One RVC detected)
No. Target of the test Testing points Complementary test Test criterion (if test
according to Table 3 conditions is applicable)
A13.5.1 To verify that, if the second P4 for frequency Test shall be One RVC detected:
RVC event starts before the conducted according
Start: 100 half cycles
VSS (voltage-is-steady-state) to Table 14
logic signal changes to
ΔU : 9,0 % U
max din
TRUE, only one RVC event
will be detected.
ΔU : 4,0 % U
ss din
See NOTE
Duration: 99 half
cycles ± 2 half cycles
NOTE A single RVC is detected. This test will confirm that the meter does not return the VSS signal to true before
100 half cycles (for the test, 40 half cycles is used). The validity of this test for 60 Hz networks is under consideration.

Table 14 – Specification of test A13.5.1
Test t = 0 t = 100 half t = 130 half t = 170 half t = 200 half t
end
0 1 2 3 4
a
definition
cycles cycles cycles cycles
(start test)
U 100 % U 93 % U 98 % U 91 % U 96 % U 96 % U
din din din din din din
vss
a
This sequence of test is described in Figure 30; the theoretical limits are described in Figure 31.

Figure 30 – Test A13.5.1 waveform

– 22 – IEC 62586-2:2017/AMD1:2021
© IEC 2021
Figure 31 – Test A13.5.1 waveform with RVC limits and arithmetic mean at 50 Hz
6.13.7.2 Test 2 (Two RVC detected)
No. Target of the test Testing point
...