IEC 63093-14:2019

IEC 63093-14 ®
Edition 1.0 2019-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Ferrite cores – Guidelines on dimensions and the limits of surface irregularities –
Part 14: EFD-cores
Noyaux ferrites – Lignes directrices relatives aux dimensions et aux limites des
irrégularités de surface –
Partie 14: Noyaux EFD
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IEC 63093-14 ®
Edition 1.0 2019-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Ferrite cores – Guidelines on dimensions and the limits of surface irregularities –

Part 14: EFD-cores
Noyaux ferrites – Lignes directrices relatives aux dimensions et aux limites des

irrégularités de surface –
Partie 14: Noyaux EFD
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 29.100.10 ISBN 978-2-8322-6764-6

– 2 – IEC 63093-14:2019 © IEC 2019
CONTENTS
FOREWORD . 4
1 Scope . 6
2 Normative references . 6
3 Terms and definitions . 6
4 Primary dimensions . 7
4.1 General . 7
4.2 Dimensions of EFD-cores . 7
4.2.1 Principal dimensions . 7
4.2.2 Effective parameter and A values . 8
min
4.3 Dimensional limits for coil formers. 8
4.4 Locations of pins and base outlines . 9
4.5 Pin diameter . 12
5 Mounting . 12
6 Definitions and limits of surface irregularities . 12
6.1 General . 12
6.2 Examples of surface irregularities . 12
6.3 Chips and ragged edges . 12
6.3.1 General . 12
6.3.2 Chips and ragged edges located on the mating surface . 12
6.3.3 Chips and ragged edges located on other surfaces . 13
6.4 Cracks . 15
6.5 Pull-out . 16
6.6 Crystallites . 16
6.7 Flash . 16
6.8 Pores . 17
Annex A (informative) EFD-core design . 18
Annex B (informative) Limits for allowable chipping areas . 19

Figure 1 – Dimensions of EFD-cores . 7
Figure 2 – Main dimensions of coil formers for EFD-cores . 8
Figure 3 – Locations of pins (SMD type) viewed from the upper side of the board . 10
Figure 4 – Locations of pins (PTH type) viewed from the upper side of the board . 11
Figure 5 – Examples of surface irregularities . 12
Figure 6 – Locations of chips and ragged edges . 13
Figure 7 – Locations of cracks . 15
Figure 8 – Location of pull-out . 16
Figure 9 – Location of crystallite . 16
Figure 10 – Location of flash . 17
Figure 11 – Location of pore . 17

Table 1 – Dimensions of EFD-cores . 7
Table 2 – Effective parameter and A values for EFD-cores . 8
min
Table 3 – Dimensional limits of coil formers for EFD-cores . 9
Table 4 – Area and length reference of irregularities for visual inspection . 14
Table 5 – Limits for cracks . 15
Table B.1 – Limits for allowable chipping areas. 19

– 4 – IEC 63093-14:2019 © IEC 2019
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
FERRITE CORES –
GUIDELINES ON DIMENSIONS AND
THE LIMITS OF SURFACE IRREGULARITIES –

Part 14: EFD-cores
FOREWORD
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