IEC 62276:2025

IEC 62276 ®
Edition 4.0 2025-03
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Single crystal wafers for surface acoustic wave (SAW) device applications –
Specifications and measuring methods

Tranches monocristallines pour applications utilisant des dispositifs à ondes
acoustiques de surface (OAS) – Spécifications et méthodes de mesure

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IEC 62276 ®
Edition 4.0 2025-03
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Single crystal wafers for surface acoustic wave (SAW) device applications –

Specifications and measuring methods

Tranches monocristallines pour applications utilisant des dispositifs à ondes

acoustiques de surface (OAS) – Spécifications et méthodes de mesure

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.140  ISBN 978-2-8327-0246-8

– 2 – IEC 62276:2025 © IEC 2025
CONTENTS
FOREWORD . 5
1 Scope . 7
2 Normative references. 7
3 Terms and definitions . 7
3.1 Flatness . 7
3.2 Appearance defects . 11
3.3 Other terms and definitions . 11
3.4 Terms and definitions related to LN and LT wafers . 12
4 Requirements . 13
4.1 General . 13
4.2 Diameters and tolerances . 13
4.3 Thickness and tolerance . 14
4.4 Orientation flat . 14
4.5 Secondary flat . 14
4.6 Front (propagation) surface roughness . 14
4.7 Back surface roughness . 14
4.8 Warp . 14
4.9 TV5 and TTV . 14
4.10 LTV and PLTV . 15
4.11 Front surface defects . 16
4.12 Tolerance of surface orientation . 16
4.13 Inclusions . 16
4.14 Position of seed in synthetic quartz wafer . 16
4.15 Electrical twins in synthetic quartz wafer . 16
4.16 Bevel . 16
4.17 Bulk resistivity (conductivity) for reduced LN and reduced LT . 16
4.18 Transmittance . 16
4.19 Lightness . 17
4.20 Colour difference . 17
5 Sampling plan . 17
5.1 General . 17
5.2 Sampling. 17
6 Test methods . 18
6.1 Diameter . 18
6.2 Thickness . 18
6.3 Existence and position of OF and SF . 18
6.4 Dimensions of OF and SF . 18
6.5 Orientation of OF and SF . 18
6.6 TV5 . 18
6.7 Warp . 18
6.8 TTV, LTV and PLTV . 18
6.9 Front surface defects . 18
6.10 Inclusions . 18
6.11 Position of seed in synthetic quartz wafer . 18
6.12 Electrical twins in synthetic quartz wafer . 19
6.13 Bevel . 19

6.14 Front surface and back surface roughness . 19
6.15 Orientation . 19
6.16 Bulk resistivity . 19
6.17 Transmittance . 19
6.18 Lightness . 19
6.19 Colour difference . 19
7 Identification, labelling, packaging, delivery condition . 19
7.1 Packaging . 19
7.2 Labelling and identification . 20
7.3 Delivery condition . 20
8 Measurements of orientation by X-ray . 20
8.1 Measurement principle . 20
8.2 Measurement method . 21
8.3 Measuring surface orientation . 21
8.4 Measuring OF flat orientation . 21
8.5 Typical wafer orientations and reference planes . 21
9 Measurement of bulk resistivity . 22
9.1 Resistance measurement . 22
9.2 Electrode . 23
9.3 Bulk resistivity . 23
10 Visual inspections – Front surface defects and inclusions inspection method . 24
11 Measurement of thickness and thickness variation. 25
11.1 Measurement principle . 25
11.1.1 Contact measurement . 25
11.1.2 Contactless measurement . 25
11.2 Sample . 25
11.3 Measurement method . 25
11.3.1 Contact measurement . 25
11.3.2 Contactless measurement . 25
12 Measurement of transmittance . 26
12.1 Measurement principle . 26
12.2 Sample . 26
12.3 Measurement method . 26
13 Measurement of lightness and colour difference . 26
13.1 Measurement principle . 26
13.2 Sample . 26
13.3 Measurement method . 27
Annex A (normative) Expression using Euler angle description for piezoelectric single
crystals . 29
Annex B (informative) Manufacturing process for SAW wafers . 32
B.1 Crystal growth methods . 32
B.1.1 Czochralski growth method . 32
B.1.2 Vertical Bridgman method . 35
B.1.3 Hydrothermal temperature gradient method . 36
B.2 Standard mechanical wafer manufacturing . 36
B.2.1 Process flow-chart . 36
B.2.2 Cutting both ends and cylindrical grinding . 37
B.2.3 Marking orientation . 37

– 4 – IEC 62276:2025 © IEC 2025
B.2.4 Slicing . 38
B.2.5 Double-sided lapping . 38
B.2.6 Bevelling (edge rounding) . 38
B.2.7 Polishing . 38
Annex C (informative) Measurement principle of lightness and colour difference . 39
Bibliography . 40

Figure 1 – Wafer sketch and measurement points . 8
Figure 2 – Schematic diagram of a TTV . 8
Figure 3 – Schematic diagram of a warp . 9
Figure 4 – Schematic diagram of a sori . 9
Figure 5 – Example of the distribution of sites for measurement of the LTV . 10
Figure 6 – LTV defined within each site on the wafer surface . 10
Figure 7 – Measurement method by X-ray . 20
Figure 8 – Relationship between cut angle and lattice planes . 21
Figure 9 – Measuring circuit . 22
Figure 10 – Resistance measuring equipment. 22
Figure 11 – Shape of electrode . 23
Figure 12 – Measurement points for lightness and colour difference determination . 27
Figure A.1 – Definition of Euler angles to rotate coordinate system (X, Y, Z) onto
(𝔁𝔁 , 𝔁𝔁 , 𝔁𝔁 ) . 29
1 2 3
Figure A.2 – SAW wafer coordinate system . 30
Figure A.3 – Relationship between the crystal axes, Euler angles, and SAW
orientation for some wafer orientations . 31
Figure B.1 – Czochralski crystal growth method . 33
Figure B.2 – Example of non-uniformity in crystals grown from different starting melt
compositions . 35
Figure B.3 – Schematic of a Vertical Bridgman furnace and example of temperature
distribution. 36
Figure B.4 – Process flow-chart . 37
Figure C.1 – Sketch for CIE LAB colour space . 39

Table 1 – Roughness, warp, TV5 and TTV specification limits . 15
Table 2 – LTV and PLTV specification for LN and LT . 15
Table 3 – Sampling plan . 17
Table 4 – Crystal planes to determine surface and OF orientations . 21
Table 5 – Electrode size . 23
Table A.1 – Selected SAW substrate orientations and corresponding Euler angles . 30

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SINGLE CRYSTAL WAFERS FOR SURFACE ACOUSTIC WAVE (SAW)
DEVICE APPLICATIONS – SPECIFICATIONS AND MEASURING METHODS

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
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9) IEC draws attention to the possibility that the implementation of this document may involve the use of (a)
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shall not be held responsible for identifying any or all such patent rights.
IEC 62276 has been prepared by IEC technical committee 49: Piezoelectric, dielectric and
electrostatic devices and associated materials for frequency control, selection and detection. It
is an International Standard.
This fourth edition cancels and replaces the third edition published in 2016. This edition
constitutes a technical revision.
This edition includes the following significant technical changes with respect to the previous
edition:
a) The terms and definitions, the technical requirements, sampling frequency, test methods
and measurement of transmittance, lightness, colour difference for LN and LT have been
added in order to meet the needs of industry development;
b) The term “inclusion” (mentioned in 4.13 and 6.10) and its definition have been added
because there was no definition for it in Clause 3;

– 6 – IEC 62276:2025 © IEC 2025
c) The specification of LTV and PLTV, and the corresponding description of sampling
frequency for LN and LT have been added, because they are the key performance
parameters for the wafers;
d) The tolerance of Curie temperature specification for LN and LT have been added in order
to meet the development requirements of the industry;
e) Measurement of thickness, TV5, TTV, LTV and PLTV have been completed, including
measurement principle and method of thickness, TV5, TTV, LTV and PLTV.
The text of this International Standard is based on the following documents:
Draft Report on voting
49/1454/CDV 49/1460/RVC
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/publications.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
• reconfirmed,
• withdrawn, or
• revised.
SINGLE CRYSTAL WAFERS FOR SURFACE ACOUSTIC WAVE (SAW)
DEVICE APPLICATIONS – SPECIFICATIONS AND MEASURING METHODS

1 Scope
This document applies to the manufacture of synthetic quartz, lithium niobate (LN), lithium
tantalate (LT), lithium tetraborate (LBO), and lanthanum gallium silicate (LGS) single crystal
wafers intended for use as substrates in the manufacture of surface acoustic wave (SAW) filters
and resonators.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies.
For undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 60758:2016, Synthetic quartz crystal – Specifications and guidelines for use
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminology databases for use in standardization at the following
addresses:
• IEC Electropedia: available at https://www.electropedia.org/
• ISO Online browsing platform: available at https://www.iso.org/obp
3.1 Flatness
3.1.1
fixed quality area
FQA
central area of a wafer surface, defined by a nominal edge exclusion, X, over which the specified
values of a parameter apply
Note 1 to entry: The boundary of the FQA is at all points (e.g. along wafer flats) the distance X away from the
perimeter of the wafer of nominal dimensions as shown in Figure 1.
3.1.2
reference plane
plane used as a reference for flatness measurements
Note 1 to entry: The reference plane can be one of the following types:
a) for measurements in which the wafer is clamped, the reference plane is the flat chuck surface that is identical
with the back surface of the wafer;
b) for measurements in which the wafer is not clamped, the reference plane is defined by the surface height at three
points on the front surface of the wafer within the FQA;
c) for measurements in which the wafer is not clamped, the reference plane is defined by the least-squares fit to
the front surface of the wafer using the surface height at all measured points within the FQA.

– 8 – IEC 62276:2025 © IEC 2025
3.1.3
site
square area on the front surface of the wafer with one side parallel to the OF
Note 1 to entry: Flatness parameters are assessed either globally for the FQA, or for each site individually.
3.1.4
TV5
thickness variation for five points
difference between the maximum thickness and the minimum thickness at the centre and four
peripheral points of the wafer as shown in Figure 1
Dimensions in millimetres
Figure 1 – Wafer sketch and measurement points
3.1.5
TTV
total thickness variation
difference between the maximum thickness d and the minimum thickness d of a wafer as
1 2
shown in Figure 2
Figure 2 – Schematic diagram of a TTV
Note 1 to entry: Measurement of TTV is performed on a clamped wafer with the reference plane as defined in
3.1.2 a).
3.1.6
warp
maximum distance between the highest point and the lowest point on the front surface of an
unclamped wafer from the reference plane, where the three-point reference plane is used

Figure 3 – Schematic diagram of a warp
Note 1 to entry: The warp describes the deformation of a wafer that is not clamped, as shown in Figure 3.
Note 2 to entry: The reference plane is defined by the surface height at three points on the front surface of the
wafer as described in 3.1.2 b).
3.1.7
sori
maximum distance between the highest point and the lowest point on the front surface of an
unclamped wafer from the reference plane, where the least-squares fit reference plane is used

Figure 4 – Schematic diagram of a sori
Note 1 to entry: The sori describes the deformation of a wafer that is not clamped, as shown in Figure 4.
Note 2 to entry: The reference plane is defined by the least-squares fit to the front surface of the wafer as described
in 3.1.2 c).
3.1.8
LTV
local thickness variation
difference between the maximum value and the minimum value of a wafer thickness at each
site of the wafer surface
– 10 – IEC 62276:2025 © IEC 2025

Note 1 to entry: All sites existing within the fixed quality area (FQA) on the wafer surface possess their own LTV
value.
Figure 5 – Example of the distribution of sites for measurement of the LTV

Figure 6 – LTV defined within each site on the wafer surface
Note 2 to entry: Measurement is performed on a clamped wafer with the reference plane as defined in 3.1.2 a). An
example of the distribution of sites for measurement of the LTV is shown in Figure 5. The LTV is defined within each
site, as illustrated in Figure 6.
3.1.9
PLTV
percent local thickness variation
percentage of sites whose local thickness variation values fall within the specified value
Note 1 to entry: As with the LTV, measurement is performed on a clamped wafer with the reference plane defined
in 3.1.2 a).
3.1.10
FPD
focal plane deviation
maximum distance between a point on the wafer surface within the fixed quality area and the
three-point reference plane
Note 1 to entry: The three-point reference plane is defined in 3.1.2 b).
Note 2 to entry: If the point on the wafer surface is above the three-point reference plane, the FPD is positive. If
that point is below the three-point reference plane, the FPD is negative.

3.2 Appearance defects
3.2.1
contamination
foreign matter on a surface of wafer which cannot be removed after cleaning
3.2.2
crack
fracture that extends to the surface of the wafer and that can or cannot penetrate the entire
thickness
3.2.3
scratch
shallow groove or cut below the established plane of the surface, with a length to width ratio
greater than 5:1
3.2.4
chip
region where material has been removed from the surface or edge of the wafer
Note 1 to entry: The size of a chip can be expressed by its maximum radial depth and peripheral chord length.
3.2.5
dimple
smooth surface depression larger than 3 mm diameter
3.2.6
pit
non-removable surface anomaly
EXAMPLE A hollow, typically resulting from a bulk defect or faulty manufacturing process.
3.2.7
orange peel
pear skin
large-featured, roughened surface visible to the unaided eye under diffuse illumination
3.3 Other terms and definitions
3.3.1
manufacturing lot
lot established by agreement between the customer and the supplier
3.3.2
orientation flat
OF
flat portion of a wafer perimeter indicating the crystal orientation
Note 1 to entry: Generally, the OF corresponds to the SAW propagation direction (see Figure 1).
3.3.3
secondary flat
SF
flat portion of a wafer perimeter shorter than the orientation flat
Note 1 to entry: When present, the SF indicates wafer polarity and can serve to distinguish different wafer cuts (see
Figure 1).
– 12 – IEC 62276:2025 © IEC 2025
3.3.4
back surface roughness
roughness that scatters and suppresses spurious bulk waves at the back surface of a wafer
3.3.5
surface orientation
crystallographic orientation of the axis perpendicular to the polished surface of the wafer
3.3.6
description of orientation and SAW propagation
indication of the surface orientation and the SAW propagation direction, separated by the
symbol "-"
Note 1 to entry: Specification of a 0° orientation is normally omitted.
Note 2 to entry: Description of wafer orientation rule is shown in Annex A.
3.3.7
tolerance of surface orientation
maximum permissible angular deviation of the surface orientation measured by X-ray diffraction
from the specified surface orientation
3.3.8
bevel
slope of the perimeter edge of a wafer
Note 1 to entry: The process of forming a slope is called "bevelling".
Note 2 to entry: Machining of the perimeter edge of a wafer can be performed through bevelling or edge rounding.
Whereas bevelling produces a flat slope, edge rounding (as the term implies) produces a rounded edge.
Note 3 to entry: Both bevelling and edge rounding, and their tolerances, are subject to agreement between the user
and the supplier.
3.3.9
diameter of wafer
diameter of circular portion of wafer excluding the OF and SF regions
3.3.10
wafer thickness
thickness measured at the centre of the wafer
3.3.11
inclusion
foreign material (solid, liquid or vapor) within a piezoelectric crystal, detectable by examination
of scattered light
3.3.12
electrical twins in synthetic quartz wafer
synthetic quartz wafer in which regions with the common Z-axis exist showing a polarity reversal
of the electrical X-axis
Note 1 to entry: Electrical twins can result from extreme conditions (temperature and pressure, for example) during
processing.
3.4 Terms and definitions related to LN and LT wafers
3.4.1
colour difference
*
∆E
ab
difference in colour at different parts of the object surface

*
Note 1 to entry: In the CIE LAB colour space, ∆E is the value representing the colour difference of different parts
ab
of the object surface.
3.4.2
lightness
L*
relative light-dark properties of the object surface
Note 1 to entry: In the CIE LAB colour space, L* is the coordinates representing the lightness of the colour of the
object.
3.4.3
reduced LN
LN treated with a reduction process
Note 1 to entry: Reduced LN is sometimes referred to as "black LN".
3.4.4
reduced LT
LT treated with a reduction process
Note 1 to entry: Reduced LT is sometimes referred to as "black LT".
3.4.5
reduction process
process comprising a reduction-oxidation (REDOX) reaction to increase conductivity to reduce
the harmful effects of pyroelectricity
3.4.6
transmittance
𝝉𝝉
ratio of transmitted power through the sample to incident power on the sample, expressed in
percent
4 Requirements
4.1 General
The specifications listed in Clause 4 apply in the absence of superseding agreements between
user and supplier. Manufacturing process for SAW wafers are shown in Annex B, these
specifications are expected to evolve and change as existing processes are refined and new
ones are developed. For wafers that are typically used in conjunction with a photolithographic
stepper equipment, LTV is typically specified as one of the flatness criteria. When using
projection lithography for full wafer exposure, FPD is often more relevant than TTV, as the
system will perform a tilt correction referenced off the front surface. Sori is often more
meaningful than warp since the least-squares derived reference plane used in that
measurement typically provides a more accurate representation of the wafer surface.
4.2 Diameters and tolerances
– 76,2 mm ± 0,25 mm (henceforth referred to as 76,2 mm wafer, commonly referred to as a
"3 inch" wafer);
– 100,0 mm ± 0,5 mm (henceforth referred to as 100 mm wafer, commonly referred to as a
"4 inch" wafer);
– 125,0 mm ± 0,5 mm (henceforth referred to as 125 mm wafer, commonly referred to as a
"5 inch" wafer);
– 150,0 mm ± 0,5 mm (henceforth referred to as 150 mm wafer, commonly referred to as a
"6 inch" wafer).
– 14 – IEC 62276:2025 © IEC 2025
4.3 Thickness and tolerance
Thickness is 0,18 mm to 0,80 mm. Tolerance for diameter of up to 100 mm is ±0,03 mm. For
diameter greater than 100 mm, thickness tolerance is to be agreed between the buyer and the
manufacturer.
4.4 Orientation flat
a) Dimensions of OF and tolerances
– 22,0 mm ± 3,0 mm unless otherwise agreed upon (for a 76,2 mm wafer);
– 32,5 mm ± 3,0 mm unless otherwise agreed upon (for a 100 mm wafer);
– 42,5 mm ± 3,0 mm unless otherwise agreed upon (for a 125 mm wafer);
– 47,5 mm ± 3,0 mm unless otherwise agreed upon (for a 150 mm wafer).
b) Orientation tolerance
Orientation tolerance: ±30′
Orientation of the OF shall be perpendicular to SAW propagation unless otherwise agreed
upon by the user and the supplier. Orientation of the OF for synthetic quartz wafers is in the
lesser X (-X) direction [1 1 –2 0].
4.5 Secondary flat
a) Dimensions of SF and tolerances
Dimensions and these tolerances of the SF are specified as reference values.
– 11,2 mm ± 4 mm unless otherwise agreed upon (for 76,2 mm wafer);
– 18,0 mm ± 4 mm unless otherwise agreed upon (for 100 mm wafer);
– 27,5 mm ± 4 mm unless otherwise agreed upon (for 125 mm wafer);
– 37,5 mm ± 4,5 mm unless otherwise agreed upon (for 150 mm wafer).
b) Orientation tolerance of SF
Orientation tolerances of the SF are measured with respect to the OF and are agreed on by
the user and the supplier with a typical value being ±1,0°.
Laser marking can be used as an alternative method to indicate the front surface.
4.6 Front (propagation) surface roughness
The front surface shall be polished. Surface roughness details are subject to agreement
between the user and the supplier.
4.7 Back surface roughness
As agreed upon by the user and the supplier (see Table 1).
4.8 Warp
As specified in Table 1.
4.9 TV5 and TTV
As specified in Table 1.
Table 1 – Roughness, warp, TV5 and TTV specification limits
W arp TV5 TTV
Diameter of Roughness of back
Material specified specified specified
wafer surface
value value value
(R )
μm μm μm
a
0,5 μm or greater 30 10 10
76,2 mm
(3 inch)
Less than 0,5 μm 20 10 10
Synthetic
quartz
0,5 μm or greater 40 10 10
100 mm
(4 inch)
Less than 0,5 μm 30 10 10
2,0 μm or greater 50 15 15
76,2 mm
LN, LT 2,0 μm to 0,5 μm 40 15 15
(3 inch)
Less than 0,5 μm 40 10 10
2,0 μm or greater 50 20 20
100 mm
2,0 μm to 0,5 μm 40 15 15
(4 inch)
Less than 0,5 μm 40 10 10
2,0 μm or greater 60 20 20
125 mm
LN, LT 2,0 μm to 0,5 μm 50 15 15
(5 inch)
Less than 0,5 μm 40 10 10
2,0 μm or greater 60 20 20
150 mm
2,0 μm to 0,5 μm 50 15 15
(6 inch)
Less than 0,5 μm 40 10 10
0,5 μm or greater 40 15 15
76,2 mm
(3 inch)
Less than 0,5 μm 40 10 15
LBO
0,5 μm or greater 40 10 10
100 mm
(4 inch)
Less than 0,5 μm 40 10 10
0,5 μm or greater 40 15 15
76,2 mm
(3 inch)
Less than 0,5 μm 40 10 10
LGS
0,5 μm or greater 40 20 20
100 mm
(4 inch)
Less than 0,5 μm 40 10 10
4.10 LTV and PLTV
When required, LTV and PLTV for LN and LT are specified in Table 2.
Table 2 – LTV and PLTV specification for LN and LT
Maximum LTV PLTV
Grade
(5 mm × 5 mm site) (3 mm from edge excluded)
I 0,5 μm ≥ 95 %
II 1 μm ≥ 95 %
III 2 μm ≥ 95 %
– 16 – IEC 62276:2025 © IEC 2025
4.11 Front surface defects
a) Scratches
No scratches on visual inspection.
b) Chips
1) Edge chips:
– Radial depth: less than 0,5 mm;
– Peripheral chord length: less than 1,0 mm.
2) Surface:
No chips on visual inspection.
c) Cracks
No cracks on visual inspection.
d) Contamination
No contamination on visual inspection.
e) Others
Other defects such as dimples, pits, and orange peel: no such defects on visual inspection.
4.12 Tolerance of surface orientation
– Synthetic quartz: ±10′;
– LN, LT, LBO: ±20′;
– LGS: ±10′.
4.13 Inclusions
LN/LT/LBO/LGS: No visible inclusions on naked eye inspection.
Synthetic quartz: material satisfies the specification Grade II of IEC 60758:2016, 4.1.3.
4.14 Position of seed in synthetic quartz wafer
The seed shall be included within ±3,5 mm centre width of the Z′ direction and parallel to the
X-direction of the centre of the wafer.
4.15 Electrical twins in synthetic quartz wafer
No electrical twins in synthetic quartz wafer.
4.16 Bevel
The bevel shall be as agreed upon by the user and the supplier.
4.17 Bulk resistivity (conductivity) for reduced LN and reduced LT
8 12 -12 -8
LN: 1,0 × 10 Ω·cm < BR < 1,0 × 10 Ω·cm (1,0 × 10 Ω/cm < BC < 1,0 × 10 Ω/cm).
10 13 -13 -10
LT: 1,0 × 10 Ω·cm < BR < 1,0 × 10 Ω·cm (1,0 × 10 Ω/cm < BC < 1,0 × 10 Ω/cm).
4.18 Transmittance
The requirement of transmittance is as agreed upon by the user and the supplier, according to
the product specifications.
4.19 Lightness
The requirement of lightness is as agreed upo
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