EN IEC 63373:2022
(Main)Dynamic on-resistance test method guidelines for GaN HEMT based power conversion devices
Dynamic on-resistance test method guidelines for GaN HEMT based power conversion devices
In general, dynamic ON-resistance testing is a measure of charge trapping phenomena in GaN power transistors. This publication describes the guidelines for testing dynamic ON-resistance of GaN lateral power transistor solutions. The test methods can be applied to the following: a) GaN enhancement and depletion-mode discrete power devices [1] b) GaN integrated power solutions c) the above in wafer and package levels Wafer level tests are recommended to minimize parasitic effects when performing high precision measurements. For package level tests, the impact of package thermal characteristics should be considered so as to minimize any device under test (DUT) self-heating implications. The prescribed test methods may be used for device characterization, production testing, reliability evaluations and application assessments of GaN power conversion devices. This document is not intended to cover the underlying mechanisms of dynamic ON-resistance and its symbolic representation for product specifications.
Richtlinien für Prüfverfahren des dynamischen Einschaltwiderstandes bei GaN-HEMT-Leistungswandlern
Lignes directrices pour les méthodes d’essai de résistance dynamique à l’état passant des dispositifs de conversion de puissance fondés sur les HEMT en GaN
IEC 63373:2022 En règle générale, l’essai de résistance dynamique à l’état passant est une mesure des phénomènes de piégeage de charge dans les transistors de puissance en GaN. L'IEC 63373:2022 donne des lignes directrices pour l’essai de résistance dynamique à l’état passant des solutions de transistors de puissance latéraux en GaN. Les méthodes d’essai peuvent être appliquées aux éléments suivants: a) dispositifs de puissance discrets en GaN à mode d’enrichissement et de déplétion; b) solutions de puissance intégrées en GaN; c) dispositifs et solutions ci-dessus au niveau des plaquettes et des boîtiers. Les méthodes d’essai spécifiées peuvent être utilisées pour la caractérisation des dispositifs, les essais de production, les évaluations de fiabilité et les évaluations de l’application des dispositifs de conversion de puissance en GaN. Le présent document n’est pas destiné à couvrir les mécanismes sous-jacents de la résistance dynamique à l’état passant et sa représentation symbolique pour les spécifications du produit.
Smernice za dinamične metode preskusov odpornosti za naprave za pretvorbo energije na osnovi GaN HEMT (IEC 63373:2022)
Preskušanje dinamične odpornosti je na splošno merjenje pojavov zajetja naboja v močnostnih tranzistorjih GaN. Ta publikacija opisuje smernice za preskušanje dinamične odpornosti rešitev lateralnih močnostnih tranzistorjev. Preskusne metode je mogoče uporabiti za:
a) ločene naprave za napajanje z izboljšavo GaN in načinom praznjenja [1];
b) rešitve za napajanje z vgrajeno tehnologijo GaN;
c) zgoraj omenjene naprave na ravni rezin in paketov.
Preskusi na ravni rezin so priporočljivi za zmanjšanje parazitskih učinkov pri izvajanju zelo natančnih meritev. Pri preskusih na ravni paketov je priporočljivo upoštevati vpliv toplotnih značilnosti paketa, s čimer se zmanjšajo morebitne posledice samosegrevanja naprav, ki se preskušajo (DUT).
Predpisane preskusne metode je mogoče uporabiti za karakterizacijo naprav, proizvodno preskušanje, vrednotenje zanesljivosti in ocene uporabe naprav za pretvorbo energije GaN. Ta dokument ne zajema osnovnih mehanizmov dinamične odpornosti in njene simbolične predstavitve za specifikacije izdelkov.
General Information
Overview
EN IEC 63373:2022 - Dynamic on-resistance test method guidelines for GaN HEMT based power conversion devices - is a CLC-adopted European version of IEC 63373:2022. It provides practical, standardized guidelines for measuring dynamic ON-resistance (RDS(on) under switching) of lateral GaN HEMT power devices. The standard targets charge-trapping-related effects (current collapse) that cause increased ON-resistance during real switching conditions and outlines test approaches for wafer- and package-level characterization, production testing, reliability evaluation and application assessment.
Key topics and technical requirements
- Scope and applicability
- Applies to GaN lateral HEMT technologies including enhancement- and depletion-mode discrete devices, integrated power solutions, at wafer and package levels.
- Not intended to explain underlying physical trapping mechanisms or to set symbolic product specifications.
- Test methods and circuits
- Describes standardized approaches for hard-switching, soft-switching and resistive switching conditions.
- Includes common test vehicles such as the inductive/resistive “double-pulse” circuit and pulsed I–V methods, plus soft‑switching test circuits with independent gate/drain pulsing.
- Measurement best practices
- Recommends wafer-level testing to minimize parasitic inductance/capacitance for high-precision dynamic ON-resistance results.
- For package-level tests, requires consideration of package thermal characteristics to avoid DUT self-heating biasing measurements.
- Test intent
- Methods may be used for datasheet characterization, process control, production testing, reliability assessments and application-level evaluation of GaN power conversion devices.
- Document metadata
- EN IEC 63373:2022 is based on IEC TC47 work and relates to JEDEC JEP173 background; the standard was approved March 2022.
Applications and who uses this standard
- Power semiconductor manufacturers - to characterize GaN HEMT dynamic ON-resistance for device development, process control and datasheet validation.
- Test labs and QA teams - to implement repeatable production and reliability tests that quantify switching-related losses (current collapse).
- Power electronics designers and system integrators - to evaluate device behavior under hard and soft switching topologies (e.g., buck, boost, PFC, ZVS/LLC) and optimize converter efficiency.
- Reliability engineers - to assess degradation modes related to charge trapping and to design stress/qualification tests.
Related standards
- IEC 63373:2022 (international edition) - same content as EN IEC 63373:2022.
- JEDEC JEP173 (informative background referenced in the IEC foreword).
Keywords: EN IEC 63373:2022, dynamic ON-resistance, GaN HEMT, current collapse, double-pulse test, pulsed I–V, wafer-level testing, package thermal effects, GaN power devices.
Frequently Asked Questions
EN IEC 63373:2022 is a standard published by CLC. Its full title is "Dynamic on-resistance test method guidelines for GaN HEMT based power conversion devices". This standard covers: In general, dynamic ON-resistance testing is a measure of charge trapping phenomena in GaN power transistors. This publication describes the guidelines for testing dynamic ON-resistance of GaN lateral power transistor solutions. The test methods can be applied to the following: a) GaN enhancement and depletion-mode discrete power devices [1] b) GaN integrated power solutions c) the above in wafer and package levels Wafer level tests are recommended to minimize parasitic effects when performing high precision measurements. For package level tests, the impact of package thermal characteristics should be considered so as to minimize any device under test (DUT) self-heating implications. The prescribed test methods may be used for device characterization, production testing, reliability evaluations and application assessments of GaN power conversion devices. This document is not intended to cover the underlying mechanisms of dynamic ON-resistance and its symbolic representation for product specifications.
In general, dynamic ON-resistance testing is a measure of charge trapping phenomena in GaN power transistors. This publication describes the guidelines for testing dynamic ON-resistance of GaN lateral power transistor solutions. The test methods can be applied to the following: a) GaN enhancement and depletion-mode discrete power devices [1] b) GaN integrated power solutions c) the above in wafer and package levels Wafer level tests are recommended to minimize parasitic effects when performing high precision measurements. For package level tests, the impact of package thermal characteristics should be considered so as to minimize any device under test (DUT) self-heating implications. The prescribed test methods may be used for device characterization, production testing, reliability evaluations and application assessments of GaN power conversion devices. This document is not intended to cover the underlying mechanisms of dynamic ON-resistance and its symbolic representation for product specifications.
EN IEC 63373:2022 is classified under the following ICS (International Classification for Standards) categories: 31.080.99 - Other semiconductor devices. The ICS classification helps identify the subject area and facilitates finding related standards.
You can purchase EN IEC 63373:2022 directly from iTeh Standards. The document is available in PDF format and is delivered instantly after payment. Add the standard to your cart and complete the secure checkout process. iTeh Standards is an authorized distributor of CLC standards.
Standards Content (Sample)
SLOVENSKI STANDARD
01-maj-2022
Smernice za dinamične metode preskusov odpornosti za naprave za pretvorbo
energije na osnovi GaN HEMT (IEC 63373:2022)
Dynamic on-resistance test method guidelines for GaN HEMT based power conversion
devices (IEC 63373:2022)
Richtlinien für Prüfverfahren des dynamischen Einschaltwiderstandes bei GaN-HEMT-
Leistungswandlern (IEC 63373:2022)
Lignes directrices pour les méthodes d’essai de résistance dynamique à l’état passant
des dispositifs de conversion de puissance fondés sur les HEMT en GaN (IEC
63373:2022)
Ta slovenski standard je istoveten z: EN IEC 63373:2022
ICS:
31.080.99 Drugi polprevodniški elementi Other semiconductor devices
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.
EUROPEAN STANDARD EN IEC 63373
NORME EUROPÉENNE
EUROPÄISCHE NORM March 2022
ICS 31.080.99
English Version
Dynamic on-resistance test method guidelines for GaN HEMT
based power conversion devices
(IEC 63373:2022)
Lignes directrices pour les méthodes d'essai de résistance Richtlinien für Prüfverfahren des dynamischen
dynamique à l'état passant des dispositifs de conversion de Einschaltwiderstandes bei GaN-HEMT-Leistungswandlern
puissance fondés sur les HEMT en GaN (IEC 63373:2022)
(IEC 63373:2022)
This European Standard was approved by CENELEC on 2022-03-17. CENELEC members are bound to comply with the CEN/CENELEC
Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration.
Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC
Management Centre or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other language made by translation
under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the
same status as the official versions.
CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic,
Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the
Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia, Slovakia, Slovenia, Spain, Sweden, Switzerland,
Turkey and the United Kingdom.
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
CEN-CENELEC Management Centre: Rue de la Science 23, B-1040 Brussels
© 2022 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members.
Ref. No. EN IEC 63373:2022 E
European foreword
The text of document 47/2690/CDV, future edition 1 of IEC 63373, prepared by IEC/TC 47
"Semiconductor devices" was submitted to the IEC-CENELEC parallel vote and approved by
CENELEC as EN IEC 63373:2022.
The following dates are fixed:
• latest date by which the document has to be implemented at national (dop) 2022-12-17
level by publication of an identical national standard or by endorsement
• latest date by which the national standards conflicting with the (dow) 2025-03-17
document have to be withdrawn
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CENELEC shall not be held responsible for identifying any or all such patent rights.
Any feedback and questions on this document should be directed to the users’ national committee. A
complete listing of these bodies can be found on the CENELEC website.
Endorsement notice
The text of the International Standard IEC 63373:2022 was approved by CENELEC as a European
Standard without any modification.
IEC 63373 ®
Edition 1.0 2022-02
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Dynamic on-resistance test method guidelines for GaN HEMT based power
conversion devices
Lignes directrices pour les méthodes d’essai de résistance dynamique à l’état
passant des dispositifs de conversion de puissance fondés sur les HEMT en
GaN
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.080.99 ISBN 978-2-8322-1076-6
– 2 – IEC 63373:2022 © IEC 2022
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative references . 6
3 Terms, definitions, symbols and abbreviated terms . 6
3.1 Terms and definitions . 6
3.2 Symbols and abbreviated terms . 6
4 Test circuits and waveforms . 7
4.1 General . 7
4.2 Inductive and resistive switching methods . 7
4.3 Pulsed current-voltage (I-V) method . 10
5 Requirements . 12
Bibliography . 14
Figure 1 – Inductive-resistive load “double-pulse” test circuit for hard-switching
evaluation . 8
Figure 2 – Depiction of the hard-switching “double-pulse” test circuit (showing its
similarity to a boost converter) . 8
Figure 3 – Simplified flowchart for inductive and/or resistive switching based dynamic
on-resistance test . 9
Figure 4 – Representative continuous-pulse hard-switching waveforms for measuring
dynamic on-resistance using the test circuits in Figure 1 and Figure 2 . 10
Figure 5 – Example test circuit for soft-switching on-resistance measurement (the gate
and drain terminals are pulsed with independent voltage signals) . 10
Figure 6 – Simplified flowchart for soft switching based dynamic on-resistance test . 11
Figure 7 – Illustrative timing diagram for measuring dynamic ON-resistance under
OFF-state stress in soft-switching mode . 12
IEC 63373:2022 © IEC 2022 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
DYNAMIC ON-RESISTANCE TEST METHOD GUIDELINES
FOR GaN HEMT BASED POWER CONVERSION DEVICES
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and
in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports,
Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC Publication(s)”). Their
preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with
may participate in this preparatory work. International, governmental and non-governmental organizations liaising
with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for
Standardization (ISO) in accordance with conditions determined by agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence between
any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter.
5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any
services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent
rights. IEC shall not be held responsible for identifying any or all such patent rights.
IEC 63373 has been prepared by IEC technical committee 47: Semiconductor devices. It is an
International Standard.
This standard is based upon JEP173 [1]. It is used with permission of the copyright holder,
JEDEC Solid State Technology Association.
The text of this International Standard is based on the following documents:
Draft Report on voting
47/2690/CDV 47/2735/RVC
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.
___________
Numbers in square brackets refer to the Bibliography.
– 4 – IEC 63373:2022 © IEC 2022
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/standardsdev/publications.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The "colour inside" logo on the cover page of this document indicates
that it contains colours which are considered to be useful for the correct understanding
of its contents. Users should therefore print this document using a colour printer.
IEC 63373:2022 © IEC 2022 – 5 –
INTRODUCTION
This document is intended for use in the GaN power semiconductor and related power electronic
industries, and provides guidelines for measuring the dynamic ON-resistance of GaN power
devices.
Gallium Nitride (GaN) lateral power High Electron Mobility Transistor (HEMT) conducts through
a two-dimensional electron gas (2DEG) in ON-state operation. Due to the various stress
conditions that the device encounters during power electronic switching applications, some
charge could get trapped in specific regions of the transistor structure. The trapped electrons
cause an increased ON-resistance when operated in a switching environment. This
phenomenon is known as current collapse and the ON-resistance at switching operation is
called dynamic ON-resistance in order to distinguish from DC ON-resistance. Increased
dynamic ON-resistance translates to higher power loss, thereby reducing overall system
efficiency. Not verifying the dynamic ON-resistance characteristic can put GaN device reliability
at risk [2].
The test methods provided in this document can be used as a guideline for measuring dynamic
ON-resistance of GaN power device, focused on lateral HEMT technologies. These
...
The article discusses EN IEC 63373:2022, which provides guidelines for testing the dynamic ON-resistance of GaN HEMT power conversion devices. Dynamic ON-resistance testing is used to measure charge trapping phenomena in GaN power transistors. The guidelines cover testing for GaN enhancement and depletion-mode discrete power devices, as well as integrated power solutions, at both the wafer and package levels. Wafer level tests are recommended to minimize parasitic effects, while package level tests should consider the thermal characteristics of the package. The prescribed test methods outlined in the article can be used for device characterization, production testing, reliability evaluations, and application assessments of GaN power conversion devices. However, it is important to note that this document does not explain the underlying mechanisms of dynamic ON-resistance or its symbolic representation for product specifications.
기사 제목: EN IEC 63373:2022 - GaN HEMT 기반 전력 변환 장치를 위한 동적 온 저항 테스트 방법 가이드라인 기사 내용: 일반적으로 동적 온 저항 테스트는 GaN 전력 트랜지스터에서의 차지 포획 현상을 측정하는 방법이다. 이 출판물은 GaN 측면 전력 트랜지스터 솔루션의 동적 온 저항 테스트에 대한 가이드라인을 설명한다. 이 테스트 방법은 다음과 같이 적용될 수 있다: a) GaN 개선 및 공진형 이산 전력 장치 [1], b) GaN 통합 전력 솔루션, c) 웨이퍼 및 패키지 레벨에서 위의 항목들. 웨이퍼 레벨 테스트는 정밀도가 높은 측정을 수행할 때 부가적인 효과를 최소화하기 위해 권장된다. 패키지 레벨 테스트에서는 패키지 열 특성의 영향을 고려하여 장치 자가 가열 영향을 최소화해야 한다. 규정된 테스트 방법은 GaN 전력 변환 장치의 장치 특성화, 생산 테스트, 신뢰성 평가 및 응용 평가에 사용할 수 있다. 그러나 이 문서는 동적 온 저항의 기본 메커니즘과 제품 사양에 대한 상징적 표현을 다루지 않는다.
記事のタイトル：EN IEC 63373:2022 - GaN HEMTベースの電力変換デバイスのダイナミックオン抵抗テスト方法のガイドライン 記事の内容：一般的に、ダイナミックオン抵抗テストは、GaNパワートランジスタでの電荷トラッピング現象の測定手法です。この出版物では、GaNレータルパワートランジスタソリューションのダイナミックオン抵抗テストのためのガイドラインについて説明しています。テスト方法は、以下のようなものに適用できます：a）GaNセルフアッシュメントおよびデプレッションモードの離散的なパワーデバイス [1] b）統合されたGaNパワーソリューション c）ウエハレベルおよびパッケージレベルでの上記のテスト。ウエハレベルのテストは、高精度な測定を行う際に寄生効果を最小限に抑えるために推奨されています。パッケージレベルのテストでは、パッケージの熱特性の影響を考慮し、テストデバイス（DUT）の自己加熱の影響を最小限に抑える必要があります。所定のテスト方法は、GaNパワー変換デバイスのデバイス特性評価、生産テスト、信頼性評価、および応用評価に使用することができます。ただし、この文書は、ダイナミックオン抵抗の基礎的なメカニズムや製品仕様の符号化表現については説明していません。
Questions, Comments and Discussion
Ask us and Technical Secretary will try to provide an answer. You can facilitate discussion about the standard in here.
Loading comments...