EN 60749-28:2017

2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.Semiconductor devices - Mechanical and climatic test methods - Part 28: Electrostatic discharge (ESD) sensitivity testing - Charged device model (CDM) - device level (IEC 60749-28:2017)31.080.01Polprevodniški elementi (naprave) na splošnoSemiconductor devices in generalICS:Ta slovenski standard je istoveten z:EN 60749-28:2017SIST EN 60749-28:2017en01-oktober-2017SIST EN 60749-28:2017SLOVENSKI
STANDARD
EUROPEAN STANDARD NORME EUROPÉENNE EUROPÄISCHE NORM
EN 60749-28
June 2017 ICS 31.080.01
English Version
Semiconductor devices - Mechanical and climatic test methods - Part 28: Electrostatic discharge (ESD) sensitivity testing - Charged device model (CDM) - device level (IEC 60749-28:2017)
Dispositifs à semiconducteurs - Méthodes d'essai mécaniques et climatiques - Partie 28: Essai de sensibilité aux décharges électrostatiques (DES) - Modèle de dispositif chargé par contact direct (DC-CDM) (IEC 60749-28:2017)
Halbleiterbauelemente - Mechanische und klimatische Prüfverfahren - Teil 28: Prüfung der Empfindlichkeit gegen elektrostatische Entladungen (ESD) - Charged Device Model (CDM) - Device Level (IEC 60749-28:2017) This European Standard was approved by CENELEC on 2017-05-02. CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC Management Centre or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the same status as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Serbia, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and the United Kingdom. European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique Europäisches Komitee für Elektrotechnische Normung CEN-CENELEC Management Centre: Avenue Marnix 17,
B-1000 Brussels © 2017 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members.
Ref. No. EN 60749-28:2017 E SIST EN 60749-28:2017

The following dates are fixed: • latest date by which the document has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2018-02-02
• latest date by which the national standards conflicting with the document have to be withdrawn (dow) 2020-05-02
Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights. CENELEC shall not be held responsible for identifying any or all such patent rights.
Endorsement notice The text of the International Standard IEC 60749-28:2017 was approved by CENELEC as a European Standard without any modification. In the official version, for Bibliography, the following note has to be added for the standard indicated:
IEC 60749-26 NOTE Harmonized as EN 60749-26. SIST EN 60749-28:2017

IEC 60749-28 Edition 1.0 2017-03 INTERNATIONAL STANDARD
Semiconductor devices – Mechanical and climatic test methods –
Part 28: Electrostatic discharge (ESD) sensitivity testing – Charged device
model (CDM) – device level
INTERNATIONAL ELECTROTECHNICAL COMMISSION
ICS 31.080.01
ISBN 978-2-8322-4139-4
– 2 – IEC 60749-28:2017 © IEC 2017 CONTENTS FOREWORD . 5 INTRODUCTION . 7 1 Scope . 8 2 Normative references . 8 3 Terms and definitions . 8 4 Required equipment . 9 4.1 CDM ESD tester . 9 4.1.1 General . 9 4.1.2 Current-sensing element . 10 4.1.3 Ground plane . 10 4.1.4 Field plate/field plate dielectric layer . 10 4.1.5 Charging resistor . 11 4.2 Waveform measurement equipment . 11 4.2.1 General . 11 4.2.2 Cable assemblies . 11 4.2.3 Equipment for high-bandwidth waveform measurement . 11 4.2.4 Equipment for 1,0 GHz waveform measurement . 11 4.3 Verification modules (metal discs) . 11 4.4 Capacitance meter . 11 4.5 Ohmmeter . 12 5 Periodic tester qualification, waveform records, and waveform verification requirements . 12 5.1 Overview of required CDM tester evaluations . 12 5.2 Waveform capture hardware . 12 5.3 Waveform capture setup . 12 5.4 Waveform capture procedure . 12 5.5 CDM tester qualification/requalification procedure . 13 5.5.1 CDM tester qualification/requalification procedure . 13 5.5.2 Conditions requiring CDM tester qualification/requalification . 13 5.5.3 1 GHz oscilloscope correlation with high bandwidth oscilloscope . 14 5.6 CDM tester quarterly and routine waveform verification procedure . 14 5.6.1 Quarterly waveform verification procedure . 14 5.6.2 Routine waveform verification procedure . 14 5.7 Waveform characteristics . 14 5.8 Documentation . 16 5.9 Procedure for evaluating full CDM tester charging of a device . 16 6 CDM ESD testing requirements and procedures . 17 6.1 Device handling . 17 6.2 Test requirements . 17 6.2.1 Test temperature and humidity . 17 6.2.2 Device test . 17 6.3 Test procedures . 17 6.4 CDM test recording / reporting guidelines . 18 7 CDM classification criteria . 18 Annex A (normative)
Verification module (metal disc) specifications and cleaning guidelines for verification modules and testers . 19 SIST EN 60749-28:2017

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A.1 Tester verification modules and field plate dielectric . 19 A.2 Care of verification modules . 19 Annex B (normative)
Capacitance measurement of verification modules (metal discs) sitting on a tester field plate dielectric . 20 Annex C (informative)
CDM test hardware and metrology improvements . 21 Annex D (informative)
CDM tester electrical schematic . 23 Annex E (informative)
Sample oscilloscope setup and waveform . 24 E.1 General . 24 E.2 Settings for the 1 GHz bandwidth oscilloscope . 24 E.3 Settings for the high-bandwidth oscilloscope . 24 E.4 Setup . 24 E.5 Sample waveforms from a 1 GHz oscilloscope . 24 E.6 Sample waveforms from an 8 GHz oscilloscope . 25 Annex F (informative)
Field-induced CDM tester discharge procedures . 27 F.1 General . 27 F.2 Single discharge procedure . 27 F.3 Dual discharge procedure . 27 Annex G (informative)
Waveform verification procedures . 29 G.1 Factor/offset adjustment method . 29 G.2 Software voltage adjustment method. 32 G.3 Example parameter recording tables . 34 Annex H (informative)
Determining the appropriate charge delay
for full charging of a large module or device . 36 H.1 General . 36 H.2 Procedure for charge delay determination . 36 Annex I (informative)
Electrostatic discharge (ESD) sensitivity testing direct contact charged device model (DC-CDM) . 38 I.1 General . 38 I.2 Standard test module . 38 I.3 Test equipment (CDM simulator) . 38 I.3.1 Test equipment design. 38 I.3.2 DUT (device under test) support . 38 I.3.3 Metal bar/board . 39 I.3.4 Equipment setup . 39 I.4 Verification of test equipment . 39 I.4.1 General description of verification test equipment . 39 I.4.2 Instruments for measurement . 41 I.4.3 Verification of test equipment, using a current probe . 41 I.5 Test procedure . 42 I.5.1 Initial measurement . 42 I.5.2 Tests . 42 I.5.3 Intermediate and final measurement . 43 I.6 Failure criteria . 43 I.7 Classification criteria . 43 I.8 Summary . 43 Bibliography . 44
Figure 1 – Simplified CDM tester hardware schematic . 10 SIST EN 60749-28:2017

– 4 – IEC 60749-28:2017 © IEC 2017 Figure 2 – CDM characteristic waveform and parameters . 16 Figure D.1 – Simplified CDM tester electrical schematic . 23 Figure E.1 – 1 GHz TC 500, small verification module . 25 Figure E.2 – 1 GHz TC 500, large verification module . 25 Figure E.3 – 8 GHz TC 500, small verification module
(oscilloscope adjusts for attenuation) . 26 Figure E.4 – GHz TC 500, large verification module (oscilloscope adjusts for attenuation) . 26 Figure F.1 – Single discharge procedure
(field charging, ICDM Pulse, and slow discharge) . 27 Figure F.2 – Dual discharge procedure
(field charging, 1st ICDM pulse, no field, 2nd ICDM pulse) . 28 Figure G.1 – An example of a waveform verification flow for qualification and quarterly checks using the factor/offset adjustment method . 30 Figure G.2 – An example of a waveform verification flow for the routine checks using the factor/offset adjustment method . 31 Figure G.3 – Example of average Ipeak for the large verification module –
high bandwidth oscilloscope . 32 Figure G.4 – An example of a waveform verification flow for qualification
and quarterly checks using the software voltage adjustment method . 33 Figure G.5 – An example of a waveform verification flow for the routine checks using the software voltage adjustment method . 34 Figure H.1 – An example characterization of charge delay vs. Ip . 37 Figure I.1 – Examples of discharge circuit where the discharge is caused by closing the switch . 39 Figure I.2 – Verification test equipment for measuring the discharge current flowing to the metal bar/board from the standard test module . 40 Figure I.3 – Current waveform. 40 Figure I.4 – Measurement circuit for verification method using a current probe . 41
Table 1 – CDM waveform characteristics for a 1 GHz bandwidth oscilloscope . 15 Table 2 – CDM waveform characteristics for a high-bandwidth (≥ 6 dez) oscilloscope . 15 Table 3 – CDM ESDS device classification levels . 18 Table A.1 – Specification for CDM tester verification modules (metal discs) . 19 Table G.1 – Example waveform parameter recording table
for the factor/offset adjustment method . 35 Table G.2 – Example waveform parameter recording table
for the software voltage adjustment method . 35 Table I.1 – Dimensions of the standard test modules . 38 Table I.2 – Specified current waveform . 40 Table I.3 – Range of peak current Ip1 for test equipment . 41 Table I.4 – Specification of peak current Ip1 for the current probe verification method . 42
IEC 60749-28:2017 © IEC 2017 – 5 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION ____________
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –
Part 28: Electrostatic discharge (ESD) sensitivity testing –
Charged device model (CDM) – device level
FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with may participate in this preparatory work. International, governmental and non-governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions determined by agreement between the two organizations. 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any misinterpretation by any end user. 4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications transparently to the maximum extent possible in their national and regional publications. Any divergence between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter. 5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any services carried out by independent certification bodies. 6) All users should ensure that they have the latest edition of this publication. 7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and members of its technical committees and IEC National Committees for any personal injury, property damage or other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is indispensable for the correct application of this publication. 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. International Standard IEC 60749-28 has been prepared by IEC technical committee 47: Semiconductor devices in collaboration with IEC technical committee 101: Electrostatics. This standard is based on ESDA/JEDEC Joint Standard ANSI/ESDA/JEDEC JS-002 which resulted from the merging of JESD22-C101 and ANSI/ESD S5.3.1). It contains the essential elements from both standards. The co-operation of ANSI/ESDA/JEDEC is gratefully acknowledged.
– 6 – IEC 60749-28:2017 © IEC 2017 The text of this International Standard is based on the following documents: FDIS Report on voting 47/2362/FDIS 47/2379/RVD
Full information on the voting for the approval of this International Standard can be found in the report on voting indicated in the above table. This document has been drafted in accordance with the ISO/IEC Directives, Part 2. A list of all parts in the IEC 60749 series, published under the general title Semiconductor devices –Mechanical and climatic test methods, can be found on the IEC website. The committee has decided that the contents of this document will remain unchanged until the stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to the specific document. At this date, the document will be
• reconfirmed, • withdrawn, • replaced by a revised edition, or • amended. A bilingual version of this publication may be issued at a later date.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates that it contains colours which are considered to be useful for the correct understanding of its contents. Users should therefore print this document using a colour printer.
IEC 60749-28:2017 © IEC 2017 – 7 –
INTRODUCTION The earliest electrostatic discharge (ESD) test models and standards simulate a charged object approaching a device and discharging through the device. The most common example is IEC 60749-26, the human body model (HBM). However, with the increasing use of automated device handling systems, another potentially destructive discharge mechanism, the charged device model (CDM), becomes increasingly important. In the CDM, a device itself becomes charged (e.g. by sliding on a surface (tribocharging) or by electric field induction) and is rapidly discharged (by an ESD event) as it closely approaches a conductive object. A critical feature of the CDM is the metal-metal discharge, which results in a very rapid transfer of charge through an air breakdown arc. The CDM test method also simulates metal-metal discharges arising from other similar scenarios, such as the discharging of charged metal objects to devices at different potential. Accurately quantifying and reproducing this fast metal-metal discharge event is very difficult, if not impossible, due to the limitations of the measuring equipment and its influence on the discharge event. The CDM discharge is generally completed in a few nanoseconds, and peak currents of tens of amperes have been observed. The peak current into the device will vary considerably depending on a large number of factors, including package type and parasitics. The typical failure mechanism observed in MOS devices for the CDM model is dielectric damage, although other damage has been noted. The CDM charge voltage sensitivity of a given device is package dependent. For example, the same integrated circuit (IC) in a small area package can be less susceptible to CDM damage at a given voltage compared to that same IC in a package of the same type with a larger area. It has been shown that CDM damage susceptibility correlates better to peak current levels than charge voltage.
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MECHANICAL AND CLIMATIC TEST METHODS –
Part 28: Electrostatic discharge (ESD) sensitivity testing –
Charged device model (CDM) – device level
1 Scope
This part of IEC 60749 establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this document. To perform the tests, the devices are assembled into a package similar to that expected in the final application. This CDM document does not apply to socketed discharge model testers. This document describes the field-induced (FI) method. An alternative, the direct contact (DC) method, is described in Annex I.
The purpose of this document is to establish a test method that will replicate CDM failures and provide reliable, repeatable CDM ESD test results from tester to tester, regardless of device type. Repeatable data will allow accurate classifications and comparisons of CDM ESD sensitivity levels. 2 Normative references There are no normative references in this document. 3 Terms and definitions For the purposes of this document, the following terms and definitions apply. ISO and IEC maintain terminological databases for use in standardization at the following addresses: • IEC Electropedia: available at http://www.electropedia.org/ • ISO Online browsing platform: available at http://www.iso.org/obp 3.1
CDM ESD
charged device model electrostatic discharge electrostatic discharge (ESD) using the charged device model (CDM) to simulate the actual discharge event that occurs when a charged device is quickly discharged to another object at a lower electrostatic potential through a single pin or terminal 3.2
CDM ESD tester
charged device model electrostatic discharge tester equipment that simulates the device level CDM ESD event using the non-socketed test method Note 1 to entry: "Equipment" is referred to as "tester" in this document. SIST EN 60749-28:2017

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3.3
dielectric layer thin insulator placed atop the field plate used to separate the device from the field plate 3.4
field plate conductive plate used to elevate the potential of the device under test (DUT) by capacitive coupling Note 1 to entry: See Figure 1. 3.5
ground plane conductive plate used to complete the circuitry for grounding/discharging the DUT Note 1 to entry: See Figure 1. 3.6
software voltage user/operator-entered voltage that, when combined with the scale factor or offset, sets the actual field plate voltage on the system in order to achieve the waveform parameters Note 1 to entry: Waveform parameters are defined in Table 1 or Table 2. 3.7
test condition
TC tester plate voltage that meets the waveform parameter conditions
Note 1 to entry:
The waveform parameter conditions are found in a particular column of Table 1 and Table 2. 4 Required equipment 4.1 CDM ESD tester 4.1.1 General Figure 1 represents the hardware schematic for a CDM tester setup to conduct field-induced CDM ESD testing assuming the use of a resistive current probe. The DUT may be an actual device or it may be one of the two verification modules (metal discs) described in Annex A. The pogo pin shall be connected to the ground plane with a 1 Ω current path with a minimum bandwidth (BW) of 9 gigahertz (GHz). The 1 Ω pogo pin to ground connection of the resistive current sensor may be a parallel combination of a 1 Ω resistor between the pogo pin and the ground plane, and the 50 Ω impedance of the oscilloscope and its coaxial cable. In Figure 1, K1 is the switch between charging the field plate and grounding the field plate. The CDM ESD testers used within the context of this document shall meet the waveform characteristics specified in Figure 2, and Table 1 and Table 2, without additional passive or active devices, such as ferrites, in the probe's assembly. SIST EN 60749-28:2017

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Figure 1 – Simplified CDM tester hardware schematic When constructing the test equipment, the parasitics in the charge and discharge paths should be minimized since the resistance inductance-capacitance (RLC) parasitics in the equipment greatly influence the test results. For existing equipment, it is recommended to contact qualified service personnel to determine compliance to this document upon removal of ferrite components. 4.1.2 Current-sensing element A current-sensing element shall be incorporated into the ground plane. The resistance of this element shall have a value of (1,0
± 10 %) Ω. A resistor, as specified in 4.1.1, shall be used as the current-sensing element. The value of resistance (including the 50 Ω cable/oscilloscope termination) shall be measured using an ohmmeter as described in 4.5. The resistance value shall be used to calculate the first peak current. The current-sensing element shall have a minimum frequency response of 9 GHz (specified by a maximum roll-off of 3 dB at 9 GHz). 4.1.3 Ground plane The probe assembly shall contain a square ground plane with the probe pin centred within it as shown in Figure 1. The dimensions of the ground plane shall be 63,5 mm × 63,5 mm ± 6,35 mm (2,5 inches × 2,5 inches ± 0,25 inches). 4.1.4 Field plate/field plate dielectric layer The field plate shall have a surface flatness to vary no more than ± 0,127 mm (0,005 inches). The field plate dielectric layer should be made with an FR4 or similar epoxy-glass material. For FR4, the thickness and thickness tolerance of this dielectric layer should be 0,381 mm ± 0,025(Ø4 mm (0,015 inches ± 0,001 inches) in order to result in a capacitance measurement (as specified in normative Annex B) in the range specified in Table A.1. If a different material is used, the material thickness is chosen to result in a capacitance measurement in the range specified in Table A.1. IEC Field plate Charging resistor K1 Dielectric layer DUT Ground plate HV supply Pogo pin (ground pin) Pogo pin to ground resistance = 1 50 Ω coax to 50 Ω oscilloscope input SIST EN 60749-28:2017

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4.1.5 Charging resistor The charging resistor shown in Figure 1 shall nominally be 100 MΩ or greater. Resistor values higher than 100 MΩ may be used, but this may not allow very large devices (refer to 5.9 and Annex H) to charge fully before being discharged by the probe assembly. This effect can be overcome by adding a delay between discharges in the CDM tester programming software. If using a resistor greater than 100 MΩ, it is recommended that the tester or the device itself be characterized to determine if a delay is needed for discharging large devices. A procedure for this large device delay characterization is given in Annex H. 4.2 Waveform measurement equipment 4.2.1 General The CDM waveform measurement equipment shall consist of the following components. 4.2.2 Cable assemblies Cable assemblies with combined internal tester cable and external cable total loss of no more than 2 dB at frequencies up to 9 GHz and a nominal 50 Ω impedance. 4.2.3 Equipment for high-bandwidth waveform measurement 4.2.3.1 High-bandwidth oscilloscope An oscilloscope or transient digitizer with a minimum real-time (single shot) 3 dB BW of at least 6 GHz and ≥ 20 gigasample/s sampling rate with a nominal 50 Ω input impedance. 4.2.3.2 Attenuator A 20 dB attenuator with a precision of ±0,5 dB, at least 12 GHz BW, and an impedance of 50 Ω ± 5,0 Ω. 4.2.4 Equipment for 1,0 GHz waveform measurement 4.2.4.1 1 GHz oscilloscope An oscilloscope or transient digitizer with a real-time (single shot) 3 dB BW of 1 GHz with a nominal 50 Ω input impedance. The sampling rate shall be ≥ 5 gigasample/s. NOTE The user has the option of using a higher BW oscilloscope and using a hardware or software filter to produce a bandwidth and sampling rate equivalent to that specified in 4.2.4.1. 4.2.4.2 Attenuator A 20 dB attenuator with a precision of ± 0,5 dB, at least 4 GHz BW, and an impedance of 50 Ω ± 5 Ω. 4.3 Verification modules (metal discs)
The large verification module shall have a capacitance of (55 ± 5 %) pF and the small verification module shall have a capacitance of (6,8 ± 5 %) pF. Refer to normative Annex A for information on the verification module physical dimensions and normative Annex B for information on the capacitance measurement procedure. 4.4 Capacitance meter Capacitance meter with a resolution of 0,2 pF, a measurement accuracy of 3 %, and a measurement frequency of 1,0 MHz as described in normative Annex B. SIST EN 60749-28:2017

– 12 – IEC 60749-28:2017 © IEC 2017 4.5 Ohmmeter The ohmmeter used to measure the resistance of the resistive probe shall be capable of measuring to an accuracy of 0,01 Ω. Use of Kelvin 4-wire connections is recommended. 5 Periodic tester qualification, waveform records, and waveform verification requirements 5.1 Overview of required CDM tester evaluations The CDM tester shall be qualified, re-qualified, and periodically verified as described in 5.5 and 5.6.
NOTE 1 Dielectric layers, ground planes (ground plates), the coaxial discharging resistor (probe), the distance between the ground plane and the field plate, the verification modules and the discharge contacts (e.g., pogo pins) are key elements of the tester construction. Any change to these elements requires a waveform verification. NOTE 2 Changes in the shape of the discharge pulse, even though they can still be within specification, can indicate degradation of the discharge path. 5.2 Waveform capture hardware Waveform capture requires the following instrumentation and tester set voltage procedure: • an oscilloscope − as specified in 4.2; • an attenuator and cable assembly as defined in 4.2; • verification modules (as described in 4.3) − with the dimensions and attributes listed in normative Annex A and the method of measurement listed in normative Annex B. 5.3 Waveform capture setup The waveform capture setup shall be carried out as follows. a) Clean the verification modules. Avoid skin contact with the modules prior to, and during testing. A recommended procedure is described in normative Annex A. b) Using an alcohol wipe, clean the discharge probe and the field charge plate on which the device is placed to remove any surface contamination that could result in charge loss. Ensure the pogo pin is free of particulates. c) Attach the appropriate 20 dB attenuator as described in 4.2.3.2 to the oscilloscope. Attach one end of the external cable assembly, as described in 4.2.2, to the attenuator and the other end to the CDM tester. Verify all connections in the measurement chain are tight. See informative Annex E for an example of oscilloscope settings and captured waveforms. 5.4 Waveform capture procedure The waveform capture procedure shall be carried out as follows. a) Place the verification module to be used on the field plate dielectric, ensuring intimate contact between the field plate dielectric and verification module. b) Set the potential of the field plate to the needed voltage for the test condition being run. c) Align the ground pin to approximately the centre of the verification module. d) Either the single discharge or dual discharge method as described in Clause F.2 or Clause F.3 respectively can be used, but the discharge method chosen should be consistent with how products will be tested. When using the dual discharge method, waveforms for positive and negative pulses require a change in the oscilloscope trigger conditions to capture only positive or negative pulses. e) Discharge the verification module at least ten times at the polarity being verified. SIST EN 60749-28:2017

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f) Observe at least ten successive waveforms during the set of discharges above and record the average waveform parameters for Ip, Tr, full width at half maximum (FWHM), and Ip2 for this group of waveforms as shown in Figure 2. g) If the waveform characteristics do not meet the requirements as defined in either Table 1 or Table 2 for the target test condition (see 5.6 and 5.7 for the appropriate table and test conditions to use), re-clean the verification modules and ground pin, check that all connections are tight, make adjustments in the field plate voltage and repeat steps a) to g). If this still does not work, check the system vacuum or look at replacement of the ground pin. Consult the tester manufacturer for more information. Repeat the procedure for the opposite polarity. 5.5 CDM tester qualification/requalification procedure 5.5.1 CDM tester qualification/requalification procedure The intent of the qualification/requalification procedure is to determine the field plate voltage needed for each test condition setting (125 – 1(Ø000) in Table 3 to produce peak current in the ranges corresponding to Table 1 and Table 2, and therefore corresponding to the classification levels as specified in Table 3. Two alternative procedures for how to qualify and routinely check the CDM test system are introduced in Annex G. These procedures are based on generally available CDM test systems and offer two methods for adjusting the field plate voltage to meet the waveform parameters of Table 1 or Table 2. CDM test system manufacturers, or test system operators, may develop alternate qualification procedures from the two procedures in Annex G, as long as they result in waveforms that meet the requirements of Table 1 or Table 2 for the various test conditions. It is recommended that settings determined from this qualification procedure be recorded for a particular test system, oscilloscope BW and polarity. This allows for detection of drift over time on the system, which may indicate a larger issue with the system. See Clause G.3 for examples. Perform the setup and waveform capture steps as described in 5.3 and 5.5 under test conditions 125 – 1(Ø000 in Table 2 for both positive and negative polarities using both small and large verification modules, and measuring with the high bandwidth oscilloscope as specified in 4.2.3.1. Refer to Annex G for example flowcharts of the procedures. If local site test voltage ranges will always be narrower than the range above (for example test conditions 125 – 500), it is permissible to perform the qualification within that narrower range. 5.5.2 Conditions requiring CDM tester qualification/requalification CDM tester qualification and requalification as described in 5.5 is required in the following situations: • acceptance testing when the CDM tester is delivered; usually performed by the manufacturer during installation; • periodic requalification in accordance with the manufacturer’s recommendations; the maximum time between requalification tests is one year; • after service or repair that could affect the waveform. SIST EN 60749-28:2017

– 14 – IEC 60749-28:2017 © IEC 2017 5.5.3 1 GHz oscilloscope correlation with high bandwidth oscilloscope During first acceptance testing, the tester manufacturer shall use a high bandwidth oscilloscope as specified in 4.2.3.1 for initial waveform capture. If the test site only has a 1 GHz oscilloscope as specified in 4.2.4.1, the tester manufacturer and end user shall confirm using appropriate bandwidth filtering techniques and comparison with the oscilloscope from the tester manufacturer that the user’s oscilloscope measures tester waveforms as defined in Table 1 for quarterly and routine waveform acceptance. NOTE The Bessel-Thomson software filter option on many oscilloscopes is a recommended high-bandwidth waveform filter as it aligns well with actual 1 GHz oscilloscope data. Oscilloscope correlation verification shall be repeated if the test site changes 1 GHz oscilloscopes. 5.6 CDM tester quarterly and routine waveform verification procedure 5.6.1 Quarterly waveform verification procedure Perform the setup and waveform capture steps as described in 5.3 and 5.5 under test conditions 125 – 1(Ø000 in Table 1 using the 1 GHz oscilloscope as specified in 4.2.4.1 or Table 2 using the high-bandwidth oscilloscope as specified in 4.2.3.1. Both verification modules shall be checked at positive and negative polarities. Recommendation is to use the high bandwidth oscilloscope if the option exists. Refer to Annex G for example flowcharts of the procedures. If local site test voltage ranges will always be narrower than the range above (for example test conditions 125 – 500), it is permissible to perform the qualification within that narrower range. Tester waveform verification shall be performed at least once per quarter. 5.6.2 Routine waveform verification procedure 5.6.2.1 General Perform the setup and waveform capture steps as described in 5.3 and 5.5 under test condition 500 in Table 1 (1 GHz oscilloscope) or Table 2 (high-bandwidth oscilloscope) for both positive and negative polarities using the verification module that most closely corresponds to the size package that will be tested. Refer to Annex G for example flowcharts of the procedures. 5.6.2.2 Routine verification frequency Initially, upon tester qualification or requalification, routine waveform verification should be completed at least once per shift. If CDM stress testing is performed on consecutive shifts, waveform checks at the end of one shift may also serve as the initial check for the following shift. Longer periods between routine waveform checks may be used if no changes in waveforms are observed for several consecutive checks. The test frequency and method chosen shall be documented. If, at any time, the waveforms no longer meet the specified limits, all ESD stress test data collected subsequent to the previous satisfactory waveform check shall be marked invalid and shall not be used for classification. 5.7 Waveform characteristics The waveforms shall appear as show
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