oSIST prEN IEC 63378-3:2024

SLOVENSKI STANDARD
01-junij-2024
Standardizacija toplotnih lastnosti pri polprevodniških ohišjih - 3. del: Simulacijski
modeli toplotnih vezij diskretnih polprevodniških ohišij za prehodno analizo
Thermal standardization on semiconductor packages - Part 3: Thermal circuit simulation
models of discrete semiconductor packages for transient analysis
Normalisation thermique des boîtiers de semiconducteurs - Partie 3: Modèles de
simulation de circuits thermiques de boîtiers de semiconducteurs discrets pour analyse
transitoire
Ta slovenski standard je istoveten z: prEN IEC 63378-3:2024
ICS:
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

47D/967/CDV
COMMITTEE DRAFT FOR VOTE (CDV)

PROJECT NUMBER:
IEC 63378-3 ED1
DATE OF CIRCULATION: CLOSING DATE FOR VOTING:
2024-04-26 2024-07-19
SUPERSEDES DOCUMENTS:
47D/949/CD, 47D/953A/CC
IEC SC 47D : SEMICONDUCTOR DEVICES PACKAGING
SECRETARIAT: SECRETARY:
Japan Mr Hiroyoshi Yoshida
OF INTEREST TO THE FOLLOWING COMMITTEES: PROPOSED HORIZONTAL STANDARD:

TC 91
Other TC/SCs are requested to indicate their interest, if
any, in this CDV to the secretary.
FUNCTIONS CONCERNED:
EMC ENVIRONMENT QUALITY ASSURANCE SAFETY
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Attention IEC-CENELEC parallel voting
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CENELEC, is drawn to the fact that this Committee Draft
for Vote (CDV) is submitted for parallel voting.
The CENELEC members are invited to vote through the
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This document is still under study and subject to change. It should not be used for reference purposes.
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Recipients of this document are invited to submit, with their comments, notification of any relevant “In Some
Countries” clauses to be included should this proposal proceed. Recipients are reminded that the CDV stage is
the final stage for submitting ISC clauses. (SEE AC/22/2007 OR NEW GUIDANCE DOC).

TITLE:
Thermal standardization on semiconductor packages - Part 3: Thermal circuit simulation
models of discrete semiconductor packages for transient analysis

PROPOSED STABILITY DATE: 2029
NOTE FROM TC/SC OFFICERS:
download this electronic file, to make a copy and to print out the content for the sole purpose of preparing National
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IEC CDV 63378-3 © IEC 2024 – 2 – 47D/967/CDV
1 CONTENTS
3 FOREWORD . 3
4 1 Scope . 5
5 2 Normative references . 5
6 3 Terms and definitions . 5
7 4 Procedure of thermal circuit network model . 6
8 4.1 General . 6
9 4.2 Detailed model analysis . 6
10 4.3 Delphi model preparation . 8
11 4.4 Thermal circuit model topology . 8
12 4.5 Determination of thermal capacitance values . 9
13 Annex A (normative) Validation for TO-252 case . 12
14 A.1 General . 12
15 A.2 Simulation parameters . 12
16 A.3 Comparison of detailed thermal model vs D2elphi model . 12
17 Bibliography . 14
19 Figure 3.1 – Two resistor model . 5
20 Figure 3.2 – Delphi model . 6
21 Figure 4.1 - Detailed model (Example) . 6
22 Figure 4.2 - PCB model . 7
23 Figure 4.3 – Simulation volume . 8
24 Figure A.1 – Heatsink model . 12
26 Table 4.1 – Dimensions and material properties of detailed model (Example) . 7
27 Table 4.2 – Dimensions and material properties of PCB model . 7
28 Table 4.3 – Thermal capacitance of the portions (Example) . 10
29 Table 4.4 – Thermal capacitance assignment . 10
30 Table 4.5 – The combination of , ,  (Example) . 10
31 Table A.1 – Comparison with detailed thermal model and D2elphi model . 13
IEC CDV 63378-3 © IEC 2024 – 3 – 47D/967/CDV
35 INTERNATIONAL ELECTROTECHNICAL COMMISSION
36 ____________
38 THERMAL STANDARDIZATION ON SEMICONDUCTOR PACKAGES –
40 Part 3: Thermal circuit simulation models of discrete semiconductor
41 packages for transient analysis
44 FOREWORD
45 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
46 all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
47 co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and
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53 Standardization (ISO) in accordance with conditions determined by agreement between the two organizations.
54 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
55 consensus of opinion on the relevant subjects since each technical committee has representation from all
56 interested IEC National Committees.
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60 misinterpretation by any end user.
61 4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
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67 6) All users should ensure that they have the latest edition of this publication.
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69 members of its technical committees and IEC National Committees for any personal injury, property damage or
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71 expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
72 Publications.
73 8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
74 indispensable for the correct application of this publication.
75 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent
76 rights. IEC shall not be held responsible for identifying any or all such patent rights.
77 IEC 63378-3 has been prepared by subcommittee 47D: Semiconductor devices packaging, of
78 IEC technical committee 47: Semiconductor devices. It is an International Standard.
79 The text of this International Standard is based on the following documents:
Draft Report on voting
XX/XX/FDIS XX/XX/RVD
81 Full information on the voting for its approval can be found in the report on voting indicated in
82 the above table.
83 The language used for the development of this International Standard is English.
84 This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
85 accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available

IEC CDV 63378-3 © IEC 2024 – 4 – 47D/967/CDV
86 at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
87 described in greater detail at www.iec.ch/standardsdev/publications.
88 The committee has decided that the contents of this document will remain unchanged until the
89 stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
90 the specific document. At this date, the document will be
91 • reconfirmed,
92 • withdrawn,
93 • replaced by a revised edition, or
94 • amended.
IEC CDV 63378-3 © IEC 2024 – 5 – 47D/967/CDV
97 THERMAL STANDARDIZATION ON SEMICONDUCTOR PACKAGES –
99 Part 3: Thermal circuit simulation models of discrete semiconductor
100 packages for transient analysis
104 1 Scope
105 This part of IEC 63378 specifies the thermal circuit network model of discrete (TO-243, TO-252
106 and TO-263) packages, which is used in the transient analysis of electronic devices to estimate
107 precise junction temperatures without experimental verification.
108 This model is assumed to be made and provided by semiconductor suppliers and to be used by
109 assembly makers of electronic devices.
110 2 Normative references
111 The following documents are referred to in the text in such a way that some or all of their content
112 constitutes requirements of this document. For dated references, only the edition cited applies.
113 For undated references, the latest edition of the referenced document (including any
114 amendments) applies.
115 IEC 60191-2:2012 DB, Mechanical standardization of semiconductor devices - Part 2:
116 Dimensions
117 3 Terms and definitions
118 3.1
119 detailed model
120 semiconductor package model which has both the geometrical dimensions of each portion, such
121 as die or molding or lead, and the material properties, for thermal analysis
122 Note 1 to entry: This model is often simplified to some extent.
123 3.2
124 thermal circuit network model
125 RC network model
126 thermal model of semiconductor packages which comprises multiple nodes, thermal resistances
127 between nodes and thermal capacitances for each node
128 3.3
129 thermal resistance model
130 thermal circuit network model which is composed of multiple nodes and resistances between
131 nodes for steady-state analysis
132 3.4
133 two resistor model
134 thermal resistance model which has three nodes and two resistances
135 Note 1 to entry: Figure 3.1 shows this model.
137 Figure 3.1 – Two resistor model

IEC CDV 63378-3 © IEC 2024 – 6 – 47D/967/CDV
139 3.5
140 Delphi model
141 thermal resistance model in which multiple resistors are connected in two dimensions
142 Note 1 to entry: Figure 3.2 shows the basic type of this model which contains six nodes and nine resistances.
144 Figure 3.2 – Delphi model
146 4 Procedure of thermal circuit network model
147 4.1 General
148 This clause describes how a conventional Delphi model is transformed into a proposed transient
149 model. The procedure is described using a specific package as an “example”.
151 4.2 Detailed model analysis
152 At first, the thermal analysis using detailed model shall be done in order to obtain the profile of
153 semiconductor temperature vs time. The power (heat quantity) shall be constant.
154 The detailed example model is shown in Figure 5.1. This model is composed of a molding, a
155 semiconductor die, a die attach, a heat spreader and leads.
158 Figure 4.1 - Detailed model (Example)
160 The
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