IEC 62271-101:2012

IEC 62271-101 ®
Edition 2.0 2012-10
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
High-voltage switchgear and controlgear –
Part 101: Synthetic testing
Appareillage à haute tension –
Partie 101: Essais synthétiques

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IEC 62271-101 ®
Edition 2.0 2012-10
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
High-voltage switchgear and controlgear –

Part 101: Synthetic testing
Appareillage à haute tension –

Partie 101: Essais synthétiques

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX XH
ICS 29.130.10 ISBN 978-2-83220-421-4

– 2 – 62271-101 © IEC:2012
CONTENTS
FOREWORD . 7
1 Scope . 9
2 Normative references . 9
3 Terms and definitions . 9
4 Synthetic testing techniques and methods for short-circuit breaking tests . 11
4.1 Basic principles and general requirements for synthetic breaking test
methods . 11
4.1.1 General . 11
4.1.2 High-current interval . 12
4.1.3 Interaction interval . 12
4.1.4 High-voltage interval . 13
4.2 Synthetic test circuits and related specific requirements for breaking tests . 14
4.2.1 Current injection methods . 14
4.2.2 Voltage injection method . 15
4.2.3 Duplicate circuit method (transformer or Skeats circuit) . 15
4.2.4 Other synthetic test methods . 16
4.3 Three-phase synthetic test methods . 16
5 Synthetic testing techniques and methods for short-circuit making tests . 19
5.1 Basic principles and general requirements for synthetic making test methods . 19
5.1.1 General . 19
5.1.2 High-voltage interval . 19
5.1.3 Pre-arcing interval . 19
5.1.4 Latching interval and fully closed position . 20
5.2 Synthetic test circuit and related specific requirements for making tests . 20
5.2.1 General . 20
5.2.2 Test circuit . 20
5.2.3 Specific requirements . 20
6 Specific requirements for synthetic tests for making and breaking performance
related to the requirements of 6.102 through 6.111 of IEC 62271-100:2008 . 21
Annex A (informative) Current distortion . 42
Annex B (informative) Current injection methods. 58
Annex C (informative) Voltage injection methods . 62
Annex D (informative) Skeats or duplicate transformer circuit . 65
Annex E (normative) Information to be given and results to be recorded for synthetic
tests . 68
Annex F (normative) Synthetic test methods for circuit-breakers with opening resistors . 69
Annex G (informative) Synthetic methods for capacitive-current switching . 76
Annex H (informative) Re-ignition methods to prolong arcing . 88
Annex I (normative) Reduction in di/dt and TRV for test duty T100a . 91
Annex J (informative) Three-phase synthetic test circuits . 100
Annex K (normative) Test procedure using a three-phase current circuit and one
voltage circuit . 107
Annex L (normative) Splitting of test duties in test series taking into account the
associated TRV for each pole-to-clear . 127
Annex M (normative) Tolerances on test quantities for type tests . 147

62271-101 © IEC:2012 – 3 –
Annex N (informative) Typical test circuits for metal-enclosed and dead tank circuit-
breakers . 150
Annex O (informative) Combination of current injection and voltage injection methods . 160
Bibliography . 163

Figure 1 – Interrupting process – Basic time intervals . 33
Figure 2 – Examples of evaluation of recovery voltage . 34
Figure 3 – Equivalent surge impedance of the voltage circuit for the current injection
method . 35
Figure 4 – Making process – Basic time intervals . 36
Figure 5 – Typical synthetic making circuit for single-phase tests. 37
Figure 6 – Typical synthetic making circuit for out-of-phase . 38
Figure 7 – Typical synthetic make circuit for three-phase tests (k = 1,5) . 39
pp
Figure 8 – Comparison of arcing time settings during three-phase direct tests (left)
and three-phase synthetic (right) for T100s with k = 1,5 . 40
pp
Figure 9 – Comparison of arcing time settings during three-phase direct tests (left)
and three-phase synthetic (right) for T100a with k = 1,5 . 41
pp
Figure A.1 – Direct circuit, simplified diagram . 49
Figure A.2 – Prospective short-circuit current . 49
Figure A.3 – Distortion current . 49
Figure A.4 – Distortion current . 50
Figure A.5 – Simplified circuit diagram . 51
Figure A.6 – Current and arc voltage characteristics for symmetrical current . 52
Figure A.7 – Current and arc voltage characteristics for asymmetrical current . 53
Figure A.8 – Reduction of amplitude and duration of final current loop of arcing . 54
Figure A.9 – Reduction of amplitude and duration of final current loop of arcing . 55
Figure A.10 – Reduction of amplitude and duration of final current loop of arcing . 56
Figure A.11 – Reduction of amplitude and duration of final current loop of arcing . 57
Figure B.1 – Typical current injection circuit with voltage circuit in parallel with the test
circuit-breaker . 59
Figure B.2 – Injection timing for current injection scheme with circuit B.1 . 60
Figure B.3 – Examples of the determination of the interval of significant change of arc
voltage from the oscillograms . 61
Figure C.1 – Typical voltage injection circuit diagram with voltage circuit in parallel
with the auxiliary circuit-breaker (simplified diagram) . 63
Figure C.2 – TRV waveshapes in a voltage injection circuit with the voltage circuit in
parallel with the auxiliary circuit-breaker . 64
Figure D.1 – Transformer or Skeats circuit . 66
Figure D.2 – Triggered transformer or Skeats circuit . 67
Figure F.1 – Test circuit to verify thermal re-ignition behaviour of the main interrupter . 73
Figure F.2 – Test circuit to verify dielectric re-ignition behaviour of the main interrupter . 73
Figure F.3 – Test circuit on the resistor interrupter . 74
Figure F.4 – Example of test circuit for capacitive current switching tests on the main
interrupter . 75

– 4 – 62271-101 © IEC:2012
Figure F.5 – Example of test circuit for capacitive current switching tests on the
resistor interrupter . 75
Figure G.1 – Capacitive current circuits (parallel mode) . 79
Figure G.2 – Current injection circuit . 80
Figure G.3 – LC oscillating circuit . 81
Figure G.4 – Inductive current circuit in parallel with LC oscillating circuit . 82
Figure G.5 – Current injection circuit, normal recovery voltage applied to both
terminals of the circuit-breaker . 83
Figure G.6 – Synthetic test circuit (series circuit), normal recovery voltage applied to
both sides of the test circuit breaker . 84
Figure G.7 – Current injection circuit, recovery voltage applied to both sides of the
circuit-breaker . 85
Figure G.8 – Making test circuit . 86
Figure G.9 – Inrush making current test circuit . 87
Figure H.1 – Typical re-ignition circuit diagram for prolonging arc-duration . 89
Figure H.2 – Combined Skeats and current injection circuits . 89
Figure H.3 – Typical waveforms obtained during an asymmetrical test using the circuit
in Figure H.2 . 90
Figure J.1 – Three-phase synthetic combined circuit . 102
Figure J.2 – Waveshapes of currents, phase-to-ground and phase-to phase voltages
during a three-phase synthetic test (T100s; k = 1,5 ) performed according to the
pp
three-phase synthetic combined circuit . 103
Figure J.3 – Three-phase synthetic circuit with injection in all phases for k = 1,5. 104
pp
Figure J.4 – Waveshapes of currents and phase-to-ground voltages during a three-
phase synthetic test (T100s; k =1,5) performed according to the three-phase
pp
synthetic circuit with injection in all phases . 104
Figure J.5 – Three-phase synthetic circuit for terminal fault tests with k = 1,3
pp
(current injection method) . 105
Figure J.6 – Waveshapes of currents, phase-to-ground and phase-to-phase voltages
during a three-phase synthetic test (T100s; k =1,3 ) performed according to the
pp
three-phase synthetic circuit shown in Figure J.5 . 105
Figure J.7 – TRV voltages waveshapes of the test circuit described in Figure J.5 . 106
Figure K.1 – Example of a three-phase current circuit with single-phase synthetic
injection . 118
Figure K.2 – Representation of the testing conditions of Table K.1 . 119
Figure K.3 – Representation of the testing conditions of Table K.2 . 120
Figure K.4 – Representation of the testing conditions of Table K.3 . 121
Figure K.5 – Representation of the testing conditions of Table K.4 . 122
Figure K.6 – Representation of the testing conditions of Table K.5 . 123
Figure K.7 – Representation of the testing conditions of Table K.6 . 124
Figure K.8 – Representation of the testing conditions of Table K.7 . 125
Figure K.9 – Representation of the testing conditions of Table K.8 . 126
Figure L.1 – Graphical representation of the test shown in Table L.6 . 137
Figure L.2 – Graphical representation of the test shown in Table L.7 . 138
Figure N.1 – Test circuit for unit testing (circuit-breaker with interaction due to gas
circulation) . 151

62271-101 © IEC:2012 – 5 –
Figure N.2 – Half-pole testing of a circuit-breaker in test circuit given by Figure N.1 –
Example of the required TRVs to be applied between the terminals of the unit(s) under
test and between the live parts and the insulated enclosure . 152
Figure N.3 – Synthetic test circuit for unit testing (if unit testing is allowed as per
6.102.4.2 of IEC 62271-100:2008) . 153
Figure N.4 – Half-pole testing of a circuit-breaker in the test circuit of Figure N.3 –
Example of the required TRVs to be applied between the terminals of the unit(s) under
test and between the live parts and the insulated enclosure . 154
Figure N.5 – Capacitive current injection circuit with enclosure of the circuit-breaker
energized . 155
Figure N.6 – Capacitive synthetic circuit using two power-frequency sources and with
the enclosure of the circuit-breaker energized . 156
Figure N.7 – Capacitive synthetic current injection circuit – Example of unit testing on
half a pole of a circuit-breaker with two units per pole – Enclosure energized with d.c.
voltage source . 157
Figure N.8 – Symmetrical synthetic test circuit for out-of-phase switching tests on a
complete pole of a circuit-breaker . 158
Figure N.9 – Full pole test with voltage applied to both terminals and the metal
enclosure . 159
Figure O.1 – Example of combined current and voltage injection circuit with application
of full test voltage to earth . 161
Figure O.2 – Example of combined current and voltage injection circuit with separated
application of test voltage . 162

Table 1 – Test circuits for test duties T100s and T100a . 17
Table 2 – Test parameters during three-phase interruption for test-duties T10, T30,
T60 and T100s, k = 1,5 . 17
pp
Table 3 – Test parameters during three-phase interruption for test-duties T10, T30,

T60 and T100s, k = 1,3 . 18
pp
Table 4 – Test parameters during three phase interruption for test-duties T10, T30,
T60 and T100s, k = 1,2 . 18
pp
Table 5 – Synthetic test methods for test duties T10, T30, T60, T100s, T100a, SP,
DEF, OP and SLF . 31
Table I.1 – Last loop di/dt reduction for 50 Hz for k = 1,3 and 1,5 . 91
pp
Table I.2 – Last loop di/dt reduction for 50 Hz for k = 1,2 . 92
pp
Table I.3 – Last loop di/dt reduction for 60 Hz for k = 1,3 and 1,5 . 93
pp
Table I.4 – Last loop di/dt reduction for 60 Hz for k = 1,2 . 94
pp
Table I.5 – Corrected TRV values for the first pole-to-clear for k = 1,3 and f = 50 Hz . 95
pp r
Table I.6 – Corrected TRV values for the first pole-to-clear for k = 1,3 and f = 60 Hz . 96
pp r
Table I.7 – Corrected TRV values for the first pole-to-clear for k = 1,5 and f = 50 Hz . 97
pp r
Table I.8 – Corrected TRV values for the first pole-to-clear for k = 1,5 and f = 60 Hz . 98
pp r
Table I.9 – Corrected TRV values for the first pole-to-clear for k = 1,2 and f = 50 Hz . 98
pp r
Table I.10 – Corrected TRV values for the first pole-to-clear for k = 1,2 and f =
pp r
60 Hz . 99
Table K.1 – Demonstration of arcing times for k = 1,5 . 108
pp
Table K.2 – Alternative demonstration of arcing times for k = 1,5 . 109
pp
Table K.3 – Demonstration of arcing times for k = 1,3 . 110
pp
Table K.4 – Alternative demonstration of arcing times for k = 1,3 . 111
pp
– 6 – 62271-101 © IEC:2012
Table K.5 – Demonstration of arcing times for k = 1,5 . 112
pp
Table K.6 – Alternative demonstration of arcing times for k = 1,5 . 113
pp
Table K.7 – Demonstration of arcing times for k = 1,3 . 114
pp
Table K.8 – Alternative demonstration of arcing times for k = 1,3 . 115
pp
Table K.9 – Procedure for combining k = 1,5 and 1,3 during test-duties T10, T30,
pp
T60 and T100s(b) . 116
Table K.10 – Procedure for combining k = 1,5 and 1,3 during test-duty T100a . 117
pp
Table L.1 – Test procedure for k = 1,5. 129
pp
Table L.2 – Test procedure for k = 1,3. 130
pp
Table L.3 – Simplified test procedure for k = 1,3 . 131
pp
Table L.4 – Test procedure for k = 1,2. 132
pp
Table L.5 – Simplified test procedure for k = 1,2 . 133
pp
Table L.6 – Test procedure for asymmetrical currents in the case of k = 1,5 . 134
pp
Table L.7 – Test procedure for asymmetrical currents in the case of k = 1,3 . 135
pp
Table L.8 – Test procedure for asymmetrical currents in the case of k = 1,2 . 136
pp
Table L.9 – Required test parameters for different asymmetrical conditions in the case
of k = 1,5 , f = 50 Hz . 139
pp r
Table L.10 – Required test parameters for different asymmetrical conditions in the
case of a k = 1,3 , f = 50 Hz . 140
pp r
Table L.11 – Required test parameters for different asymmetrical conditions in the
case of k = 1,2 , f = 50 Hz . 141
pp r
Table L.12 – Required test parameters for different asymmetrical conditions in the
case of k = 1,5 , f = 60 Hz . 142
pp r
Table L.13 – Required test parameters for different asymmetrical conditions in the
case of k = 1,3 , f = 60 Hz . 143
pp r
Table L.14 – Required test parameters for different asymmetrical conditions in the
case of k = 1,2, f = 60 Hz . 144
pp r
Table L.15 – Procedure for combining k = 1,5 and 1,3 during test-duties T10, T30,
pp
T60 and T100s(b) . 145
Table L.16 – Procedure for combining k = 1,5 and 1,3 during test-duty T100a . 146
pp
Table M.1 – Tolerances on test quantities for type tests (1of 2) . 148

62271-101 © IEC:2012 – 7 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
___________
HIGH-VOLTAGE SWITCHGEAR AND CONTROLGEAR –

Part 101: Synthetic testing
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
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Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
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with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with an IEC Publication.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 62271-101 has been prepared by subcommittee 17A: High-voltage
switchgear and controlgear, of IEC technical committee 17: Switchgear and controlgear.
This second edition cancels and replaces the first edition published in 2006 and its
Amendment 1 published in 2010. It constitutes a technical revision.
This edition includes the following significant technical changes with respect to the first
edition:
– addition of the new rated voltages of 1 100 kV and 1 200 kV;
– revision of Annex F regarding circuit-breakers with opening resistors;
– alignment with the second edition of IEC 62271-100:2008 and its Amendment 1 (2012).

– 8 – 62271-101 © IEC:2012
The text of this standard is based on the first edition of IEC 62271-101 and the following
documents:
FDIS Report on voting
17A/1015/FDIS 17A/1024/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
This publication shall be read in conjunction with IEC 62271-100, published in 2008, to which
it refers. The numbering of the subclauses of Clause 6 is the same as in IEC 62271-100.
However, not all subclauses of IEC 62271-100 are addressed; merely those where synthetic
testing has introduced changes.
A list of all the parts in the IEC 62271 series, under the general title High-voltage switchgear
and controlgear, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
for the correct
that it contains colours which are considered to be useful
understanding of its contents. Users should therefore print this document using a
colour printer.
62271-101 © IEC:2012 – 9 –
HIGH-VOLTAGE SWITCHGEAR AND CONTROLGEAR –

Part 101: Synthetic testing
1 Scope
This part of IEC 62271 mainly applies to a.c. circuit-breakers within the scope of IEC 62271-
100. It provides the general rules for testing a.c. circuit-breakers, for making and breaking
capacities over the range of test duties described in 6.102 to 6.111 of IEC 62271-100:2008,
by synthetic methods.
It has been proven that synthetic testing is an economical and technically correct way to test
high-voltage a.c. circuit-breakers according to the requirements of IEC 62271-100 and that it
is equivalent to direct testing.
The methods and techniques described are those in general use. The purpose of this
standard is to establish criteria for synthetic testing and for the proper evaluation of results.
Such criteria will establish the validity of the test method without imposing restraints on
innovation of test circuitry.
2 Normative references
The following documents, in whole or in part, are normatively referenced in this document and
are indispensable for its application. For dated references, only the edition cited applies. For
undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 62271-100:2008, High-voltage switchgear and controlgear – Part 100: Alternating current
circuit-breakers
Amendment 1:2012
3 Terms and definitions
For the purposes of this document, the terms and definitions given in IEC 62271-100, as well
as the following, apply.
3.1
direct test
test in which the applied voltage, the current and the transient and power-frequency recovery
voltages are all obtained from a circuit having a single-power source, which may be a power
system or special alternators as used in short-circuit testing stations or a combination of both
3.2
synthetic test
test in which all of the current, or a major portion of it, is obtained from one source (current
circuit), and in which the applied voltage and/or the recovery voltages (transient and power
frequency) are obtained wholly or in part from one or more separate sources (voltage circuits)
3.3
test circuit-breaker
circuit-breaker under test
SEE: 6.102.3 of IEC 62271-100:2008.

– 10 – 62271-101 © IEC:2012
3.4
auxiliary circuit-breaker
circuit-breaker forming part of a synthetic test circuit used to put the test circuit-breaker into
the required relation with various circuits
3.5
current circuit
that part of the synthetic test circuit from which all or the major part of the power-frequency
current is obtained
3.6
voltage circuit
that part of the synthetic test circuit from which all or the major part of the applied voltage
and/or recovery voltage is obtained
3.7
prospective current (of a circuit and with respect to a circuit-breaker)
current that would flow in the circuit if each pole of the test and auxiliary circuit-breakers were
replaced by a conductor of negligible impedance
[SOURCE: IEC 60050-441:1984, 441-17-01, modified]
3.8
actual current
current through the test circuit-breaker (prospective current modified by the arc voltage of the
test and auxiliary circuit-breakers)
3.9
distortion current
calculated current equal to the difference between the prospective current and the actual
current
3.10
post-arc current
current which flows through the arc gap of a circuit-breaker when the current and arc voltage
have fallen to zero and the transient recovery voltage has begun to rise
3.11
current-injection method
synthetic test method in which the voltage circuit is applied to the test circuit-breaker before
power-frequency current zero
3.12
initial transient making current
ITMC
transient current which flows through the circuit-breaker at the moment of voltage breakdown
prior to the initiation of current from the current circuit during making
3.13
injected current
current supplied by the voltage circuit of a current injection circuit when it is connected to the
circuit-breaker under test
3.14
voltage-injection method
synthetic test method in which the voltage circuit is applied to the test circuit-breaker after
power frequency current zero
62271-101 © IEC:2012 – 11 –
3.15
reference system conditions
conditions of an electrical system having the parameters from which the rated and test values
of IEC 62271-100 are derived
3.16
time delay of making device
t
m
time interval, during synthetic making test, between the instant of breakdown of the applied
voltage and the initiation of current from the current circuit
3.17
minimum clearing time
sum of the minimum opening time, minimum relay time (0,5 cycle), and the minimum arcing
time at current interruption after the minor loop of the first-pole-to-clear, during test duty
T100a only, as declared by the manufacturer
NOTE This definition should be used only for the determination of the test parameters during short-circuit breaking
tests according to test duty T100a.
[SOURCE: 3.7.159 of IEC 62271-100:2008]
3.18
pre-strike
voltage breakdown between the contacts during a making operation which initiates current
flow
4 Synthetic testing techniques and methods for short-circuit breaking tests
4.1 Basic principles and general requirements for synthetic breaking test methods
4.1.1 General
Any particular synthetic method chosen for testing shall adequately stress the test circuit-
breaker. Generally, the adequacy is established when the test method meets the
requirements set forth in the following subclauses.
A circuit-breaker has two basic positions: closed and open. In the closed position a circuit-
breaker conducts full current with negligible voltage drop across its contacts. In the open
position it conducts negligible current but with full voltage across the contacts. This defines
the two main stresses, the current stress and the voltage stress, which are separated in time.
If closer attention is paid to the voltage and current stresses during the interrupting process
(Figure 1), three main intervals can be recognized:
– High-current interval
The high-current interval is the time from contact separation to the start of the significant
change in arc voltage. The high-current interval precedes the interaction and high-voltage
intervals.
– Interaction interval
The interaction interval is the time from the start of the significant change in arc voltage
prior to current zero to the time when the current including the post-arc current, if any,
ceases to flow through the test circuit-breaker (see also Clause B.2).
– High-voltage interval
The high-voltage interval is the time from the moment when the current including the post-
arc current, if any, ceases to flow through the test circuit-breaker to the end of the test.

– 12 – 62271-101 © IEC:2012
4.1.2 High-current interval
During the high-current interval the test circuit-breaker shall be stressed by the test circuit in
such a way that the starting conditions for the interaction interval, within tolerances to be
specified, are the same as under reference system conditions.
In synthetic test circuits the ratio of the power-frequency voltage of the current circuit to the
arc voltage is low in comparison with tests at reference system conditions due to:
– the voltage of the current circuit being a fraction of the system voltage;
– the fact that the arc voltages of the test circuit-breaker and of the auxiliary circuit-breaker
are added.
As a result the duration of the current loop and the peak value of the current will be reduced.
This distortion of the current is outlined in Annex A.
Considerations with respect to the arc energy released in the test circuit-breaker lead to a
maximum permissible influence in terms of tolerances on two characteristic values of the
shape of the current, i.e. current-peak value and current-loop duration (see Annex A).
The tolerance on the amplitude and the power frequency of the prospective breaking current
is given in 6.103.2 and 6.104.3 of IEC 62271-100:2008. Therefore, the following conditions
concerning the actual current through the test circuit-breaker shall be met:
– for symmetrical testing the current amplitude and final loop duration shall not be less than
90 % of the required values based on rated current;
– for asymmetrical testing, the current amplitude and final loop duration shall be between
90 % and 110 % of the required values, based on rated current and time constant (see
Tables 15 to 22 of IEC 62271-100:2008).
Adjustment measures:
The amplitude and duration of the last current loop may be adjusted by several means,
such as
– increasing or decreasing of the r.m.s. value of the short-circuit test current,
– changing of the frequency of the test current,
– using pre-tripping or delayed tripping,
– changing the instant of current initiation (initial d.c. component).
4.1.3 Interaction interval
During the interaction interval, the short-circuit current stress changes into high-voltage stress
and the circuit-breaker performance can significantly influence the current and voltages in the
circuit. As the current decreases to zero, the arc voltage may rise to charge parallel
capacitance and distort current passing through the arc. After the current zero the post-arc
conductivity may result in additional damping of the transient recovery voltage and thus
influence the voltage across the circuit-breaker and the energy supplied to the ionized contact
gap. The interaction between the circuit and the circuit-breaker immediately before and after
current zero (i.e. during the interaction interval) is of extreme importance to the interrupting
process.
During the interaction interval, the current and voltage waveforms shall be the same fo
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