IEC 62271-101:2021

IEC 62271-101 ®
Edition 3.0 2021-07
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
High-voltage switchgear and controlgear –
Part 101: Synthetic testing
Appareillage à haute tension –
Partie 101: Essais synthétiques

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IEC 62271-101 ®
Edition 3.0 2021-07
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
High-voltage switchgear and controlgear –

Part 101: Synthetic testing
Appareillage à haute tension –

Partie 101: Essais synthétiques

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 29.130.10 ISBN 978-2-8322-1004-6

– 2 – IEC 62271-101:2021 © IEC 2021
CONTENTS
FOREWORD . 9
1 Scope . 11
2 Normative references. 11
3 Terms and definitions . 11
4 Synthetic testing techniques and methods for short-circuit breaking tests . 13
4.1 Basic principles and general requirements for synthetic breaking test
methods . 13
4.1.1 General . 13
4.1.2 High-current interval . 14
4.1.3 Interaction interval . 15
4.1.4 High-voltage interval . 15
4.2 Synthetic test circuits and related specific requirements for breaking tests . 18
4.2.1 Current injection methods . 18
4.2.2 Voltage injection method . 19
4.2.3 Duplicate circuit method (transformer or Skeats circuit) . 20
4.2.4 Other synthetic test methods . 20
4.3 Three-phase synthetic test methods . 20
5 Synthetic testing techniques and methods for short-circuit making tests . 24
5.1 Basic principles and general requirements for synthetic making test methods . 24
5.1.1 General . 24
5.1.2 High-voltage interval . 27
5.1.3 Pre-arcing interval . 27
5.1.4 Latching interval and fully closed position . 27
5.2 Synthetic test circuit and related specific requirements for making tests . 27
5.2.1 General . 27
5.2.2 Test circuit and test requirements . 27
5.2.3 Alternative test method with reduced voltage . 32
7 Type tests . 33
7.102 General . 33
7.104 Demonstration of arcing times . 34
7.107 Terminal fault tests . 45
7.109 Short-line fault tests . 49
7.110 Out-of-phase making and breaking tests . 50
7.111 Capacitive current tests . 50
Annex A (normative) Correction of di/dt and TRV for test duty T100a . 53
A.1 General . 53
A.2 Reduction in di/dt . 53
A.3 Corrected TRV for the first-pole-to-clear with required asymmetry . 53
A.4 Correction of the di/dt and TRV of the first-pole-to-clear for tests with
intermediate asymmetry . 60
A.5 Correction of the di/dt and TRV of the second- or last-pole-to-clear with
major extended loop with required asymmetry during three-phase tests . 61
A.6 Correction of the di/dt and TRV during tests with a subsequent minor loop . 61
A.7 Calculation of the di/dt and TRV of the first-pole-to-clear . 61
A.7.1 General . 61
A.7.2 Calculation of di/dt . 61

A.7.3 Calculation of TRV . 62
A.7.4 Examples of calculation of di/dt and TRV . 64
Annex B (normative) Tolerances on test quantities for type tests . 66
Annex C (normative) Information to be given and results to be recorded for synthetic
tests . 69
C.1 General . 69
C.2 Auxiliary circuit-breaker . 69
C.3 Test conditions . 69
C.4 Quantities to be recorded . 69
C.4.1 General . 69
C.4.2 Voltages . 69
C.4.3 Currents . 69
Annex D (normative) Test procedure using a three-phase current circuit and one
voltage circuit . 70
D.1 Test circuit . 70
D.2 Test method . 71
D.2.1 General . 71
D.2.2 Test duty T100s(b) . 71
D.2.3 Test duty T100a . 80
D.2.4 Combination of first-pole-to-clear factors 1,3 and 1,5 . 89
Annex E (normative) Splitting of test duties in test series taking into account the
associated TRV for each pole-to-clear . 92
E.1 General . 92
E.2 Test-duties T10, T30, T60, T100s(b), OP1 and OP2(b). 92
E.2.1 Test procedure for first-pole-to-clear factors 1,5 and 2,5 . 92
E.2.2 Test procedure for first-pole-to-clear factors 1,3 and 2,0 . 93
E.2.3 Test procedure for first-pole-to-clear factor 1,2 . 94
E.3 Test duty T100a . 95
E.3.1 General . 95
E.3.2 Test procedure for first-pole-to-clear factor 1,5 . 96
E.3.3 Test procedure for first-pole-to-clear factor 1,3 . 97
E.3.4 Test procedure for first-pole-to-clear factor 1,2 . 99
E.4 Combination of first-pole-to-clear factors . 100
E.4.1 General . 100
E.4.2 Combination of first-pole-to-clear factors 1,3 and 1,5 for test duties T10,
T30, T60 and T100s(b) . 100
E.4.3 Combination of first-pole-to-clear factors 2,0 and 2,5 for test duties OP1
and OP2(b) . 101
E.4.4 Combination of first-pole-to-clear factors 1,3 and 1,5 for test duty T100a . 102
Annex F (informative) Three-phase synthetic test circuits . 114
F.1 General . 114
F.2 Three-phase synthetic combined circuit . 114
F.3 Three-phase synthetic circuit with injection in all phases . 117
F.4 Three-phase synthetic circuit with injection in two phases . 118
Annex G (informative) Examples of test circuits for metal-enclosed and dead tank
circuit-breakers . 122
Annex H (informative) Step-by-step method to prolong arcing . 133
Annex I (informative) Synthetic methods for capacitive current tests . 135
I.1 General . 135

– 4 – IEC 62271-101:2021 © IEC 2021
I.2 Recovery voltage . 135
I.3 Combined current and voltage circuits . 135
I.4 Making tests . 136
I.5 Current chopping . 136
I.6 Examples test circuits . 136
Annex J (normative) Synthetic test methods for circuit-breakers with opening resistors . 145
J.1 General . 145
J.2 Conditions. 145
J.2.1 General . 145
J.2.2 Transient recovery voltage interval . 145
J.2.3 Power-frequency recovery voltage interval . 145
J.3 Multiple step test procedure . 145
J.3.1 General . 145
J.3.2 Test to verify the re-ignition behaviour of the making and breaking unit . 146
J.3.3 Test to verify the re-ignition behaviour of the making and breaking unit
during short circuit test duties with any test method . 147
J.3.4 Tests on resistor switch(s) . 148
J.4 Test requirements . 149
J.4.1 General . 149
J.4.2 Testing of the making and breaking unit . 150
J.4.3 Testing of the resistor switch . 151
J.4.4 Test of the resistor stack . 151
Annex K (informative) Combination of current injection and voltage injection methods . 152
K.1 Current injection methods . 152
K.2 Voltage injection methods . 152
K.3 Combined current and voltage injection circuits. 152
K.3.1 General . 152
K.3.2 Combined current and voltage injection circuit with application of full
test voltage to earth . 152
K.3.3 Combined current and voltage injection circuit with separated
application of test voltage . 152
Bibliography . 155

Figure 1 – Interrupting process – Basic time intervals . 14
Figure 2 – Examples of evaluation of initial recovery voltage . 17
Figure 3 – Equivalent surge impedance of the voltage circuit for the current injection
method . 19
Figure 4 – Reference lines of TRV with four-parameter for k = 1,5 . 22
pp
Figure 5 – Reference lines of TRV with four-parameter for k = 1,3 . 23
pp
Figure 6 – Reference lines of TRV with four-parameter for k = 1,2 . 24
pp
Figure 7 – Making process – Basic time intervals . 26
Figure 8 – Example of synthetic making circuit for single-phase tests . 29
Figure 9 – Example of synthetic making circuit for out-of-phase tests . 30
Figure 10 – Example of synthetic making circuit for three-phase tests (k = 1,5) . 31
pp
Figure 11 – Comparison of arcing time settings during three-phase direct tests (left)
and three-phase synthetic (right) for T100s with k = 1,5 . 37
pp
Figure 12 – Comparison of arcing time settings during three-phase direct tests (left)
and three-phase synthetic (right) for T100s with k = 1,3 . 38
pp
Figure 13 – Comparison of arcing time settings during three-phase direct tests (left)
and three-phase synthetic tests (right) for T100a with k = 1,5 . 41
pp
Figure 14 – Comparison of arcing time settings during three-phase direct tests (left)
and three-phase synthetic tests (right) for T100a with k = 1,3 . 42
pp
Figure 15 – Evaluation of recovery voltage during synthetic capacitive current
switching testing . 52
Figure D.1 – Example of a three-phase current circuit with single-phase synthetic
injection . 71
Figure D.2 – Representation of the testing conditions of Table D.1. 73
Figure D.3 – Representation of the testing conditions of Table D.2. 75
Figure D.4 – Representation of the testing conditions of Table D.3. 77
Figure D.5 – Representation of the testing conditions of Table D.4. 79
Figure D.6 – Representation of the testing conditions of Table D.5. 82
Figure D.7 – Representation of the testing conditions of Table D.6. 84
Figure D.8 – Representation of the testing conditions of Table D.7. 86
Figure D.9 – Representation of the testing conditions of Table D.8. 88
Figure E.1 – Example of graphical representation of the tests shown in Table E.6 . 97
Figure E.2 – Example of graphical representation of the tests shown in Table E.7 and
Table E.8 . 99
Figure F.1 – Three-phase synthetic combined circuit . 115
Figure F.2 – Waveshapes of currents, phase-to-ground and phase-to phase voltages
during a three-phase synthetic test (T100s; k = 1,5) performed according to the
pp
three-phase synthetic combined circuit . 116
Figure F.3 – Three-phase synthetic circuit with injection in all phases for k = 1,5 . 117
pp
Figure F.4 – Waveshapes of currents and phase-to-ground voltages during a three-
phase synthetic test (T100s; k = 1,5) performed according to the three-phase
pp
synthetic circuit with injection in all phases . 118
Figure F.5 – Three-phase synthetic circuit for terminal fault tests with k = 1,3
pp
(current injection method) . 119
Figure F.6 – Waveshapes of currents and phase-to-ground voltages during a
three-phase synthetic test (T100s; k = 1,3 ) performed according to the three-phase
pp
synthetic circuit shown in Figure F.5 . 120
Figure F.7 – TRV voltages waveshapes of the test circuit described in Figure F.5 . 121
Figure G.1 – Example of a test circuit for unit testing (circuit-breaker with interaction
due to gas circulation) . 123
Figure G.2 – Oscillogram corresponding to Figure G.1 – Example of the required TRVs
to be applied between the terminals of the unit(s) under test and between the live parts
and the insulated enclosure . 124
Figure G.3 – Example of test circuit using two voltage circuits for breaking tests . 125
Figure G.4 – Example of test circuit using two voltage circuits for breaking tests . 126
Figure G.5 – Example of a synthetic test circuit for unit testing (if unit testing is allowed

as per 7.102.4.2 of IEC 62271-100:2021) . 127
Figure G.6 – Oscillogram corresponding to Figure G.3 – Example of the required TRVs
to be applied between the terminals of the unit(s) under test and between the live parts
and the insulated enclosure . 128

– 6 – IEC 62271-101:2021 © IEC 2021
Figure G.7 – Example of a capacitive current injection circuit with enclosure of the
circuit-breaker energized . 129
Figure G.8 – Example of a capacitive synthetic circuit using two power-frequency
circuits and with the enclosure of the circuit-breaker energized . 130
Figure G.9 – Example of a capacitive synthetic current injection circuit – Unit testing on
half a pole of a circuit-breaker with two units per pole – Enclosure energized with DC
voltage . 131
Figure G.10 – Example of a synthetic making circuit for out-of-phase tests . 132
Figure H.1 – Example of a re-ignition circuit diagram for prolonging arc-duration . 133
Figure H.2 – Example of waveforms obtained during a symmetrical test using the
circuit in Figure H.1. 134
Figure I.1 – Power-frequency circuits in parallel. 138
Figure I.2 – Current injection circuit . 139
Figure I.3 – Power-frequency current injection circuit . 140
Figure I.4 – Current injection circuit, recovery voltage applied to both terminals of the
circuit-breaker . 141
Figure I.5 – Current injection circuit with decay compensation. 142
Figure I.6 – LC oscillating circuit . 143
Figure I.7 – Inrush making current test circuit . 144
Figure J.1 – Test circuit to verify re-ignition behaviour of the making and breaking unit
using current injection method. 147
Figure J.2 – Test circuit to verify re-ignition behaviour of the making and breaking unit . 148
Figure J.3 – Test circuit on the resistor switch . 149
Figure J.4 – Example of test circuit for capacitive current switching tests on the making
and breaking unit . 150
Figure J.5 – Example of test circuit for capacitive current switching tests on the resistor
switch . 151
Figure K.1 – Example of combined current and voltage injection circuit with application
of full test voltage to earth . 153
Figure K.2 – Example of combined current and voltage injection circuit with separated
application of test voltage . 154

Table 1 – Tolerances and limits required during the high-current interval . 15
Table 2 – Test circuits for test duties T100s and T100a . 21
Table 3 – Test parameters during three-phase interruption for test-duties T10, T30,
T60 and T100s, k = 1,5 . 21
pp
Table 4 – Test parameters during three-phase interruption for test-duties T10, T30,
T60 and T100s, k = 1,3 . 22
pp
Table 5 – Test parameters during three phase interruption for test-duties T10, T30,

T60 and T100s, k = 1,2 . 23
pp
Table 6 – Symbols and abbreviated terms used for operation during synthetic tests . 33
Table 7 – Synthetic test methods for test duties T10, T30, T60, T100s, T100a, SP,
DEF, OP and SLF . 46
Table A.1 – Corrected TRV values for the first-pole-to-clear for k = 1,3 and
pp
f = 50 Hz . 54
r
Table A.2 – Corrected TRV values for the first-pole-to-clear for k = 1,3 and
pp
f = 60 Hz . 55
r
Table A.3 – Corrected TRV values for the first-pole-to-clear for k = 1,5 and
pp
f = 50 Hz . 57
r
Table A.4 – Corrected TRV values for the first-pole-to-clear for k = 1,5 and
pp
f = 60 Hz . 58
r
Table A.5 – Corrected TRV values for the first-pole-to-clear for k = 1,2 and
pp
f = 50 Hz . 58
r
Table A.6 – Corrected TRV values for the first-pole-to-clear for k = 1,2 and
pp
f = 60 Hz . 59
r
Table A.7 – Percentage of DC component and di/dt at current zero for first-pole-to-
clear for f = 50 Hz . 59
r
Table A.8 – Percentage of DC component and di/dt at current zero for first-pole-to-
clear for f = 60 Hz . 60
r
Table B.1 – Tolerances on test quantities for type tests . 67
Table D.1 – Demonstration of arcing times for k = 1,5 . 72
pp
Table D.2 – Alternative demonstration of arcing times for k = 1,5 . 74
pp
Table D.3 – Demonstration of arcing times for k = 1,3 . 76
pp
Table D.4 – Alternative demonstration of arcing times for k = 1,3 . 78
pp
Table D.5 – Demonstration of arcing times for k = 1,5 . 81
pp
Table D.6 – Alternative demonstration of arcing times for k = 1,5 . 83
pp
Table D.7 – Demonstration of arcing times for k = 1,3 . 85
pp
Table D.8 – Alternative demonstration of arcing times for k = 1,3 . 87
pp
Table D.9 – Procedure for combining k = 1,5 and 1,3 during test-duties T10, T30,
pp
T60 and T100s(b) . 89
Table D.10 – Procedure for combining k = 1,5 and 1,3 during test-duty T100a . 90
pp
Table E.1 – Test procedure for k = 1,5 and 2,5 . 92
pp
Table E.2 – Test procedure for k = 1,3 and 2,0 . 93
pp
Table E.3 – Simplified test procedure for k = 1,3 and 2,0 . 94
pp
Table E.4 – Test procedure for k = 1,2 . 95
pp
Table E.5 – Simplified test procedure for k = 1,2 . 95
pp
Table E.6 – Test procedure for asymmetrical currents for k = 1,5 . 96
pp
Table E.7 – Test procedure for asymmetrical currents for k = 1,3 . 98
pp
Table E.8 – Test procedure for asymmetrical currents for k = 1,2 . 100
pp
Table E.9 – Procedure for combining k = 1,3 and 1,5 for test-duties T10, T30, T60
pp
and T100s(b) . 101
Table E.10 – Procedure for combining k = 2,0 and 2,5 for test-duties OP1 and
pp
OP2(b) . 102
Table E.11 – Procedure for combining k = 1,5 and 1,3 for test-duty T100a . 103
pp
Table E.12 – Required test parameters for different asymmetrical conditions in the
case of k = 1,5, f = 50 Hz . 104
pp r
– 8 – IEC 62271-101:2021 © IEC 2021
Table E.13 – Required test parameters for different asymmetrical conditions in the
case of a k = 1,3, f = 50 Hz . 106
pp r
Table E.14 – Required test parameters for different asymmetrical conditions in the
case of k = 1,2, f = 50 Hz . 108
pp r
Table E.15 – Required test parameters for different asymmetrical conditions in the
case of k = 1,5, f = 60 Hz . 109
pp r
Table E.16 – Required test parameters for different asymmetrical conditions in the
case of k = 1,3, f = 60 Hz . 111
pp r
Table E.17 – Required test parameters for different asymmetrical conditions in the
case of k = 1,2, f = 60 Hz . 113
pp r
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
HIGH-VOLTAGE SWITCHGEAR AND CONTROLGEAR –

Part 101: Synthetic testing
FOREWORD
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent
rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 62271-101 has been prepared by subcommittee 17A: Switching
devices, of IEC technical committee 17: High-voltage switchgear and controlgear.
This third edition cancels and replaces the second edition published in 2012 and
Amendment 1:2017. This edition constitutes a technical revision.
This edition includes the following significant technical changes with respect to the second
edition:
a) alignment with the third edition of IEC 62271-100:2021;
b) update this document with the last methods and techniques used for synthetic tests;

– 10 – IEC 62271-101:2021 © IEC 2021
The text of this document is based on the following documents:
FDIS Report on voting
17A/1312/FDIS 17A/1315/RVD
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/standardsdev/publications.
This publication shall be read in conjunction with IEC 62271-100:2021, to which it refers. The
numbering of the subclauses of Clause 7 is the same as in IEC 62271‑100. However, not all
subclauses of IEC 62271-100 are addressed; merely those where synthetic testing has
introduced changes.
A list of all the parts in the IEC 62271 series, under the general title High-voltage switchgear
and controlgear, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
The contents of the corrigendum of October 2021 have been included in this copy.

IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates that it
contains colours which are considered to be useful for the correct understanding of its
contents. Users should therefore print this document using a colour printer.

HIGH-VOLTAGE SWITCHGEAR AND CONTROLGEAR –

Part 101: Synthetic testing
1 Scope
This part of IEC 62271 mainly applies to AC circuit-breakers within the scope of IEC 62271-100.
It provides the general rules for testing AC circuit-breakers, for making and breaking capacities
over the range of test duties described in 7.102 to 7.111 of IEC 62271-100:2021, by synthetic
methods.
It has been proven that synthetic testing is an economical and technically correct way to test
high-voltage AC circuit-breakers according to the requirements of IEC 62271-100 and that it is
equivalent to direct testing.
The methods and techniques described are those in general use. The purpose of this document
is to establish criteria for synthetic testing and for the proper evaluation of results. Such criteria
will establish the validity of the test method without imposing restraints on innovation of test
circuitry.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies.
For undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 62271-100:2021, High-voltage switchgear and controlgear – Part 100: Alternating-current
circuit-breakers
3 Terms and definit
...