IEC TR 61643-03:2024

IEC TR 61643-03 ®
Edition 1.0 2024-07
TECHNICAL
REPORT
Low-voltage surge protective devices –
Part 03: SPD testing guide
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IEC TR 61643-03 ®
Edition 1.0 2024-07
TECHNICAL
REPORT
Low-voltage surge protective devices –

Part 03: SPD testing guide
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 29.240.01; 29.240.10 ISBN 978-2-8322-7999-1

– 2 – IEC TR 61643-03:2024 © IEC 2024
CONTENTS
FOREWORD . 5
INTRODUCTION . 7
1 Scope . 8
2 Normative references . 8
3 Terms and definitions . 9
4 Correspondence between this document and the tests in IEC 61643-x1 . 9
5 Probe application – residual voltage measurements . 9
5.1 Overview. 9
5.2 General . 9
5.3 Guidance for the test arrangement . 14
5.3.1 General . 14
5.3.2 Method 1: Voltage probe placed at a certain distance . 14
5.3.3 Method 2: Minimized loop of measurement lines . 16
5.3.4 Combination of method 1 and method 2 for pigtail connections . 17
6 Insulation resistance and dielectric withstand . 19
6.1 General . 19
6.2 Surfaces which are touchable after installation as for normal use are as
follows: . 19
6.3 Surfaces on which the SPD can be mounted or it can be in contact with
metal surfaces: . 20
6.4 Conclusions: . 21
6.5 Example of a test-set-up to measure the Insulation Resistance according to
9.3.7 and the Dielectric Withstand according to 9.3.8 of IEC 61643-01:— . 22
7 TOV testing . 23
7.1 TOV testing of SPDs for AC power systems . 23
7.2 TOV testing of SPDs for DC power systems . 26
8 Test application to SPDs with multiple components . 27
8.1 General . 27
8.2 Example of a multiple series spark gap with resistive/capacitive trigger
control . 28
8.3 Example of a series spark gap with resistive/capacitive trigger control and
with a parallel connected series connection of GDT + MOV(s) . 28
8.4 Example of a 3-electrode GDT with parallel MOV bypass/trigger control . 29
8.5 Example of a 4-electrode spark gap with GDT + MOV trigger control . 30
8.6 Example of a GDT with parallel connected series connection of GDT + MOV . 30
8.7 Example of a 3-electrode spark gap with trigger transformer . 31
9 SPD coordination testing . 32
9.1 Energy coordination . 32
9.2 Let-through energy (LTE) method . 32
9.2.1 General . 32
9.2.2 Method . 34
9.3 Energy and voltage protection coordination method . 35
9.3.1 General . 35
9.3.2 Coordination criteria . 35
9.3.3 Coordination techniques . 36
9.3.4 Coordination test . 36
10 System level immunity testing . 40

10.1 General . 40
10.2 SPD discharge current test under normal service conditions: . 40
10.3 Induction test due to lightning currents: . 40
10.4 Recommended test classification of system level immunity (following
IEC 61000-4-5): . 40
Annex A (informative) Critical investigation on the impulse current specification for T1
SPDs when testing Metal Oxide Varistors . 42
A.1 History and background . 42
A.2 General information . 42
A.3 Test program and instructions . 43
A.3.1 Detailed instructions . 43
A.4 Details and results of interlaboratory comparison tests . 44
A.4.1 Single disc results . 45
A.4.2 Double block results . 46
A.5 Conclusions from interlaboratory test results . 47
A.6 Further investigations and comparison tests in CTI . 47
A.6.1 Examples. 48
A.6.2 Overview single disc results. 49
A.6.3 Overview double block results . 49
A.7 Final conclusions . 49
Annex B (informative) Illustration of the terms mode of protection, current path and

current branch . 51
B.1 Examples of SPDs with one single mode of protection . 51
B.2 Examples of multimode SPDs . 52
Bibliography . 55

Figure 1 – 8/20 current impulse and induced voltage . 10
Figure 2 – Test arrangement A . 11
Figure 3 – Test arrangement B . 12
Figure 4 – Test arrangement C . 13
Figure 5 – Measured voltages of test arrangements A, B and C during 8/20 current

application . 13
Figure 6 – Routing of the measurement lines of an SPD having a single mode of
protection . 15
Figure 7 – Wrong routings of the measurement lines . 15
Figure 8 – Routing of the measurement lines of a multimode SPD, example 1 . 16
Figure 9 – Routing of the measurement lines of a multimode SPD, example 2 . 16
Figure 10 – Example for the application of method 2 at an SPD having a single mode
of protection. 17
Figure 11 – Example for the application of method 1 and method 2 where the SPD is
provided with pigtail connections . 18
Figure 12 – Wrong routings of the pigtails together with the measurement lines where
the SPD is provided with pigtail connections . 18
Figure 13 – Examples of a three-phase and single-phase test setup for use in testing
SPDs for application in TT systems under TOVs caused by faults in the high (medium)

voltage system . 24
Figure 14 – Example of a three-phase test setup for use in testing SPDs for use in IT
systems under TOVs caused by faults in the high (medium) voltage system . 25
Figure 15 – Vector diagram for the voltages in the test setup in Figure 14 . 26

– 4 – IEC TR 61643-03:2024 © IEC 2024
Figure 16 – Example of a test setup for use in testing SPDs intended to be connected
to a DC system, which is derived from an AC TT system without separation, under
TOVs caused by faults in the high (medium) voltage system . 27
Figure 17 – Example of a test setup for use in testing SPDs intended to be connected
to a DC TT system, which is derived from another earthed DC system, under TOVs
caused by faults in the high (medium) voltage system . 27
Figure 18 – multiple series spark gap with resistive /capacitive trigger control . 28
Figure 19 – series spark gap with capacitive trigger control . 29
Figure 20 – 3-electrode GDT with parallel MOV bypass/trigger control . 29
Figure 21 – 4-electrode spark gap with GDT + MOV trigger control . 30
Figure 22 – GDT with parallel connected series connection of GDT + MOV . 31
Figure 23 – 3-electrode spark gap with trigger transformer . 31
Figure 24 – LTE – Coordination method with standard pulse parameters . 33
Figure 25 – SPDs arrangement for the coordination test . 38
Figure 26 – Example of a circuit used to perform discharge current tests under normal

service conditions . 41
Figure 27 – Example circuit of an induction test due to lightning currents . 41
Figure B.1 – SPD with one mode of protection comprising one current path and
consisting of one current branch . 51
Figure B.2 – SPD with one mode of protection comprising three current paths (blue,
green, yellow arrows), but consisting of only one current branch . 52
Figure B.3 – SPD with three modes of protection (L-N, N-PE and L-PE) whereby the
mode L-PE is composed of a series connection of the modes L-N and N-PE, the modes
of protection L-N and N-PE comprise one current path and consist of one current
branch each, the mode of protection L-PE comprises one current path but consists of

two current branches (L-N and N-PE) . 52
Figure B.4 – SPD with two modes of protection (L-N, N-PE) or three modes of
protection (L-N, N-PE, L-PE) as declared by the manufacturer, each mode of
protection comprises one current path (blue, green, yellow arrows), but each mode of
protection or current path consists of two current branches (e.g. L to common
connection point and N to common connection point) . 53
Figure B.5 – SPD with two modes of protection (L-N, N-PE) or three modes of
protection (L-N, N-PE, L-PE) as declared by the manufacturer, each mode of

protection comprises two current paths (blue, green, orange arrows) . 54
Figure B.6 – SPD with two modes of protection (L-N, N-PE) or three modes of
protection (L-N, N-PE, L-PE) as declared by the manufacturer and containing three
current branches (blue, green, yellow arrows) in total, each mode of protection

containing two current branches . 54

Table 1 – Correspondence between this document and the IEC 61643-x1 series . 9
Table 2 – Values to be calculated . 34
Table 3 – Normalised division factors for a CWG . 34
Table 4 – Resulting calculation from Table 2 and Table 3 . 35
Table 5 – Test procedure for coordination . 39

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
LOW-VOLTAGE SURGE PROTECTIVE DEVICES –

Part 03: SPD Testing Guide
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
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9) IEC draws attention to the possibility that the implementation of this document may involve the use of (a)
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IEC TR 61643-03 has been prepared by subcommittee 37A: Low-voltage Surge Protective
Devices, of IEC technical committee 37: Surge Arrestors. It is a Technical Report.
The text of this Technical Report is based on the following documents:
Draft Report on voting
37A/XX/DTR 37A/XX/RVDTR
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this Technical Report is English.

– 6 – IEC TR 61643-03:2024 © IEC 2024
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/publications.
A list of all parts in the IEC 61643, published under the general title Low-voltage surge
protective devices, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The "colour inside" logo on the cover page of this document indicates
that it contains colours which are considered to be useful for the correct understanding
of its contents. Users should therefore print this document using a colour printer.

INTRODUCTION
It has been assumed in the preparation of this document that the execution of its provisions is
entrusted to appropriately qualified and experienced persons.
Throughout this document, when the “IEC 61643-x1 series” is mentioned, it refers to all parts
of the IEC 61643 series of standards that deal with testing of SPDs, e.g. IEC 61643-01,
IEC 61643-11.
This part of the IEC 61643 series addresses correct test execution and accurate interpretation
of measurement results and is also intended to further enhance repeatability and comparability
throughout different test laboratories and to establish an acceptable accuracy level for the test
results obtained.
The new SPD classification T1 SPD, T2 SPD and T3 SPD is relating to the former test class
oriented classification Class I tests, Class II tests and Class III tests.

– 8 – IEC TR 61643-03:2024 © IEC 2024
LOW-VOLTAGE SURGE PROTECTIVE DEVICES –

Part 03: SPD Testing Guide
1 Scope
This part of IEC 61643, which is a Technical Report, applies to SPD testing in accordance with
the IEC 61643-x1 series and for SPD coordination and system level immunity purposes.
It aims to provide guidance and helpful information for correct test execution and accurate
interpretation of measurement results. It is also intended to further enhance repeatability and
comparability throughout different test laboratories and to establish an acceptable accuracy
level for the test results obtained.
The main subjects are:
– Test application
– Test arrangement/setup
– Probe application
– SPD coordination testing
– System level immunity testing
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies.
For undated references, the latest edition of the referenced document (including any
amendments) applies.
For the purposes of this document the normative references given in IEC 61643-01:— and the
following apply.
IEC 61643-01:—, Low-voltage surge protective devices – Part 01: General requirements and
test methods
, Low-voltage surge protective devices – Part 11: Surge protective devices
IEC 61643-11:—
connected to low-voltage power systems – Requirements and test methods
IEC 61643-12:2020, Low-voltage surge protective devices – Part 12: Surge protective devices
connected to low-voltage power systems – Selection and application principles
IEC 61643-41:— , Low-voltage surge protective devices – Part 41: Surge protective devices
connected to DC low-voltage power systems – Requirements and test methods
___________
Under preparation. Stage at the time of publication: IEC/ACDV 61643-01:2023.
Under preparation. Stage at the time of publication: IEC/ACDV 61643-11:2023.
Under preparation. Stage at the time of publication: IEC/ACDV 61643-41:2023.

3 Terms and definitions
For the purposes of this document, the terms and definitions given in IEC 61543-01:— apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
4 Correspondence between this document and the tests in IEC 61643-x1
Table 1 provides information on which clauses of this document should apply to certain tests
from the IEC 61643-x1 series.
Table 1 – Correspondence between this document and the IEC 61643-x1 series
IEC 61643-03 clause reference Relevance for test clauses in the IEC 61643-x1
series
5 Probe application – residual voltage measurements 9.1.1, Table 3, pass criterion D
9.3.4 measured limiting voltage,
9.3.5 operating duty test,
9.6.5.3 Measurement of voltage rate of rise du/dt
6 Insulation resistance and dielectric withstand 9.3.7 Insulation resistance
9.3.8 Dielectric withstand
7 TOV testing 9.3.9 Behaviour under temporary overvoltages (TOVs)
7.1 TOV testing of SPDs for AC power systems IEC 61643-11:—, 9.3.9.101 TOVs caused by faults in
the high (medium) voltage system
7.2 TOV testing of SPDs for DC power systems IEC 61643-41:—, 9.3.9 Behaviour under temporary
overvoltages (TOVs)
8 Test application to SPDs with multiple components General
Annex A Critical investigation on the impulse current 9.1.2 Impulse discharge current
specification for T1 SPDs when testing
Metal Oxide Varistors
5 Probe application – residual voltage measurements
5.1 Overview
Residual voltages measurements are very sensitive measurements due to the fact that they are
carried out at high frequencies in presence of magnetic fields which may strongly interfere with
the results of these measurements to such an extent that different measurements from one
measurement to another one, or between different testing entities may not be comparable.
This clause intends to provide guidelines on testing techniques for making correct residual
voltages measurements to limit these deviations and discrepancies.
5.2 General
According to the induction law, an alternating magnetic field induces a voltage into a conductor
loop. The induced voltage depends on the loop size and the frequency and the amount of
magnetic field. The intensity of a magnetic field decreases with increasing distance to its
source.
– 10 – IEC TR 61643-03:2024 © IEC 2024
The residual voltage is measured with 8/20 current impulses. The magnetic field generated by
this 8/20 current impulse induces a voltage into the loop build up by the voltage measurement
lines that are connected to the device under test. This voltage is added to the voltage drop
between the two points where the measurement lines are connected to. This induced voltage
depends on and is directly proportional to the size of the loop build by the voltage measurement
lines and to the peak value of the 8/20 current impulse and may have values of several 10 V up
to some kV. The wave shape of the induced voltage follows the derivative di/dt of the 8/20
current impulse and reaches its maximum at the beginning of the 8/20 current impulse. A zero
crossing and therefore 0 V occurs at the crest value of the 8/20 current impulse. A typical
waveshape of the induced voltage is shown in Figure 1.

Figure 1 – 8/20 current impulse and induced voltage
In general, the test procedure to measure the residual voltage with 8/20 current impulses
requires the connection of the voltage measuring system as close as possible to the SPD. This
is caused by the fact that a voltage drop occurs along the length of a conductor when a current
flows through. This voltage drop also influences the measured voltage between the two points
to which the measurement lines are connected.
To show the influence of the loop size of the voltage measurement lines and the voltage drop
of the conductors to the test sample when the 8/20 current impulse flows, three test
arrangements are assumed.
Test arrangement A is given in Figure 2 and shows a large loop size of the voltage measurement
lines that are connected far from the test sample.
Test arrangement B is given in Figure 3 and shows a smaller loop size of the voltage
measurement lines that are connected directly to the test sample.
Test arrangement C is given in Figure 4 and shows a loop size as small as possible of the
voltage measurement lines that are twisted and connected directly to the test sample.
Figure 5 shows the measured voltage time behaviour of the test arrangements A, B and C during
8/20 current application when the device under test is a voltage limiting SPD.

Key
1 HV output connection of impulse current generator
2 Ground connection of impulse current generator
3 Device under test (SPD)
4 Conductor to connect the SPD to the impulse current generator
5 Voltage probe
6 Loop area created by the voltage measurement lines (hash shaded area)
Figure 2 – Test arrangement A
– 12 – IEC TR 61643-03:2024 © IEC 2024

Key
1 HV output connection of impulse current generator
2 Ground connection of impulse current generator
3 Device under test (SPD)
4 Conductor to connect the SPD to the impulse current generator
5 Voltage probe
6 Loop area created by the voltage measurement lines (hash shaded area)
Figure 3 – Test arrangement B
Key
1 HV output connection of impulse current generator
2 Ground connection of impulse current generator
3 Device under test (SPD)
4 Conductor to connect the SPD to the impulse current generator
5 Voltage probe
6 Loop area created by the voltage measurement lines (hash shaded area)
Figure 4 – Test arrangement C
Figure 5 – Measured voltages of test arrangements A, B
and C during 8/20 current application

– 14 – IEC TR 61643-03:2024 © IEC 2024
5.3 Guidance for the test arrangement
5.3.1 General
The guidance for test arrangements to measure the residual voltage with 8/20 current impulses
given in 5.3.2 and 5.3.3 may be applied if:
• it is unknown or it is assumed, that the influence of the magnetic field of the 8/20 current
or the loop size of the measurement lines is too big, or
• the measured residual voltage exceeds the voltage protection level Up of an SPD
defined by the manufacturer, or
• agreed or required by the manufacturer of the SPD.
The following two alternate test arrangements are proposed. Depending on the equipment
available and as required by the manufacturer of the SPD one of these methods could be
chosen.
In addition, the use of differential probes and/or a scope with isolated inputs should be
considered.
5.3.2 Method 1: Voltage probe placed at a certain distance
If the design of the SPD and/or the size of the voltage probe does not allow to connect the
voltage probes very close to the device under test (DUT) without creating a large loop area, the
following test setup may be appropriate to minimize the loop build up by the measurement lines
and the SPD itself.
The measurement lines connecting the voltage probe to the DUT should be as small as possible.
Their insulation should be as small as possible but thick enough to withstand, when twisted
together, the expected residual voltage. The measuring lines should be routed along the
shortest distance between the connections of the DUT along the housing of the DUT. From the
midpoint of the shortest distance between the connections of DUT, the measurement lines
should be twisted with a twist rate of at least 30 twists per meter and routed at around 90° ±10°
away from the axis created by the DUT and its conductors to the impulse current generator.
The shortest distance between the connections of DUT onto its housing may vary depending
on the mode of protection under test. A typical example of an SPD having a single mode of
protection is given in Figure 6. Two typical examples of a multimode SPD are given in Figure 8
and Figure 9.
Figure 7 shows a wrong routing of the measurement lines, where the loop between the
measurement lines and the DUT is too large.
The voltage probe should be placed in a distance of 200 mm minimum up to 500 mm maximum
away from the DUT.
Figure 6 – Routing of the measurement lines of an SPD having
a single mode of protection
Loop area created by the pigtails together with the voltage measurement lines (hash shaded
area)
Figure 7 – Wrong routings of the measurement lines

– 16 – IEC TR 61643-03:2024 © IEC 2024

Figure 8 – Routing of the measurement lines of a multimode SPD, example 1

Figure 9 – Routing of the measurement lines of a multimode SPD, example 2
5.3.3 Method 2: Minimized loop of measurement lines
If the design of the SPD and the size of the voltage probe allows to connect the voltage probe
directly or via short measurement lines placed close to the DUT the following test setup may be
appropriate to minimize the loop build by the measurement lines and the SPD itself.

The voltage probe (with reduced dimensions) is placed as close as possible to the SPD. The
voltage probe is either connected directly to the DUT or via a separate connecting wire which
is as straight and as short as possible. It should be considered that the connecting wire itself is
not part of the test circuit for the impulse current and no impulse flows through it.
To minimize the loop size even further, the ground connection wire 5 (connected to 4 on the
ground side) should be twisted around the body of the voltage probe.
If possible, the voltage probe should be positioned in parallel to the impulse current flow through
the SPD. Therefore the design of the SPD (single mode/ multimode) and the corresponding flow
of surge current should to be considered.
Figure 10 shows an example for the application of method 2 to an SPD having a single mode
of protection.
Key
1 HV output connection of impulse current generator
2 Ground connection of impulse current generator
3 Device under test (SPD)
4 Conductor to connect the SPD to the impulse current generator
5 Conductor to connect the SPD to the voltage probe
6 Voltage probe
7 Loop area created by the voltage measurement lines (hash shaded area)
Figure 10 – Example for the application of method 2 at
an SPD having a single mode of protection
5.3.4 Combination of method 1 and method 2 for pigtail connections
Figure 11 describes the probe voltage connection for products with pigtail connections.

– 18 – IEC TR 61643-03:2024 © IEC 2024
Figure 12 shows a wrong routing of the SPD pigtails together with the measurement lines, where the
loop created by the SPD pigtails and the measurement lines is too large.

Figure 11 – Example for the application of method 1 and method 2
where the SPD is provided with pigtail connections

Loop area created by the pigtails together with the voltage measurement lines (hash shaded area)
Figure 12 – Wrong routings of the pigtails together with the measurement lines
where the SPD is provided with pigtail connections

6 Insulation resistance and dielectric withstand
6.1 General
In this clause guidance is given on how to correctly perform the testing of the insulation
resistance and the dielectric withstand of SPDs:
– between live parts and the SPD’s body,
– between electrically separated circuits,
– between live parts of the SPD´s main circuits and live parts of any electrically separated
circuit(s)
– between live parts of different electrically separated circuit(s)
6.2 Surfaces which are touchable after installation as for normal use are as follows:
Normal use means:
Built in an enclosure including a cover.
– only the yellow marked surfaces are
touchable
– 20 – IEC TR 61643-03:2024 © IEC 2024
6.3 Surfaces on which the SPD can be mounted or it can be in contact with metal
surfaces:
The SPD can be installed in a metallic
cabinet or casing
– red marked surfaces can be of
metal or conductive material
The cover could also be metallic or
conductive
– red marked surfaces of the SPD can
be in contact with metallic or
conductive parts
6.4 Conclusions:
“Body” includes the red + yellow marked
surfaces and the mounting surface.
The red + yellow marked surfaces are
covered with metal foil for testing.
The metal foil also covers screw holes,
but the foil is not pushed into the holes
during the application of the test finger

Sufficient distance is kept between the
metal foil and the live terminal
entrance(s) to ensure that no flashover
occurs during testing.
The mounting surface including any
recessed surface for mounting rails, or
similar, are also covered with foil.
The PE terminal is connected to the metal
foil.
– 22 – IEC TR 61643-03:2024 © IEC 2024
6.5 Example of a test-set-up to measure the Insulation Resistance according to 9.3.7
and the Dielectric Withstand according to 9.3.8 of IEC 61643-01:—
Test according to 9.3.7.2, item a) of
IEC 61643-01:—
Between all interconnected live parts of
the SPD’s main circuit(s) (all terminals
being connected together, but excluding
the PE, PEN or PEM
terminals/connections) and the SPD’s
body.
Test according to 9.3.7.2, item b) of
IEC 61643-01:—
Between all interconnected live parts
from each electrically separated circuit,
if there is any, and the SPDs body.

Test according to 9.3.7.2, item c) of
IEC 61643-01:—
between all interconnected live parts of
the SPD’s main circuit(s) (all terminals
being connected together, but excluding
the PE, PEN or PEM
terminals/connections) and all
interconnected live parts of each
electrically separated circuit, if there are
any.
Test according to 9.3.7.2, item d) of
IEC 61643-01:—
between all interconnected live parts of
any electrically separated circuit and all
interconnected live parts of all other
electrically separated circuits, if there is
more than one.
NOTE R /U insulation resistance test equipment
iso ac
7 TOV testing
7.1 TOV testing of SPDs for AC power systems
Figure 13 provides additional examples of test setups to IEC 61643-11 for use in testing SPDs
for application in TT systems and for testing TOVs caused by faults in the high (medium) voltage
system.
– 24 – IEC TR 61643-03:2024 © IEC 2024

Figure 13 – Examples of a three-phase and single-phase test setup for use in testing
SPDs for application in TT systems under TOVs caused by faults in the high (medium)
voltage system
Figure 14 provides an additional example of a test setup to IEC 61643-11 for use in testing
SPDs for application in IT systems and for testing TOVs caused by faults in the high (medium)
voltage system. Figure 15 provides the corresponding vector diagram for the voltages in this
test setup.
Figure 14 – Example of a three-phase test setup for use in testing SPDs for use in IT
systems under TOVs caused by faults in the high (medium) voltage system
The earthing point for the example test setup is choosen to be located in phase L2 for
measurement reference purposes and for protection considerations, to ensure that no point of
the test setup exceeds 1 200 V RMS to earth. This earthing point may in principle be choosen
anywhere depending on laboratory system configuration, but may have an influence on
measurement setup.
This earthing point for the test setup has no relation to the earth fault simulation provided by
the test setup.
– 26 – IEC TR 61643-03:2024 © IEC 2024

Figure 15 – Vector diagram for the voltages in the test setup in Figure 14
7.2 TOV testing of SPDs for DC power systems
Figure 16 provides an example of a test setup to IEC 61643-41:— for use in testing SPDs
intended to be connected to a DC system, which is derived from an AC TT system without
separation, under TOVs caused by faults in the high (medium) voltage system.

Figure 16 – Example of a test setup for use in testing SPDs intended to be connected to
a DC system, which is derived from an AC TT system without separation, under TOVs
caused by faults in the high (medium) voltage system
Figure 17 provides an example of a test setup to IEC 61643-41:— for use in testing SPDs
intended to be connected to a DC TT system, which is derived from another earthed DC system,
under TOVs caused by faults in the high (medium) voltage system.

Figure 17 – Example of a test setup for use in testing SPDs intended to be connected to
a
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