iTeh Standards logo
EURUSD
Your shopping cart is empty.
CLC

IEC/TC 93 - IEC_TC_93

Standardization to enable the integration and automation of electrotechnical product design, engineering, manufacturing, and logistics support processes, and to facilitate procedures for product operation and maintenance. This standardization should also support the integrated system design of electrotecnical products which encompasses the electrical, electronic, electromechanical and embedded software performance aspects. Such standardization involves comuter-sensible representations of electrotechnical hardware and embedded and control software for use in comuter-aided and auxiliary activities that may directly impact these processes. Representative activities include but are not limited to: - preparing data element descriptions of electrotechnical products, - preparing information models of such products, - preparing design, engineering, manufacturing and logistics support process application protocols, - identifying hardware and software requirements to support the use and validation of the application protocols, - developing methods and enabling technologies for TC 93 and other IEC Technical Committees. This work shall be carried out in collaboration with ISO/TC 184/SC 4 and other relevant technical committees in IEC and ISO

IEC_TC_93

Standardization to enable the integration and automation of electrotechnical product design, engineering, manufacturing, and logistics support processes, and to facilitate procedures for product operation and maintenance. This standardization should also support the integrated system design of electrotecnical products which encompasses the electrical, electronic, electromechanical and embedded software performance aspects. Such standardization involves comuter-sensible representations of electrotechnical hardware and embedded and control software for use in comuter-aided and auxiliary activities that may directly impact these processes. Representative activities include but are not limited to: - preparing data element descriptions of electrotechnical products, - preparing information models of such products, - preparing design, engineering, manufacturing and logistics support process application protocols, - identifying hardware and software requirements to support the use and validation of the application protocols, - developing methods and enabling technologies for TC 93 and other IEC Technical Committees. This work shall be carried out in collaboration with ISO/TC 184/SC 4 and other relevant technical committees in IEC and ISO

General Information

Status
Stagnation
Sector
V30 - DESIGN AUTOMATION
Parent
IEC - CLC IEC TC
Standardization Organization
ICS
Directive
Mandate
50
CLC
EN 61926-1:2000(Main)
Design automation - Part 1: Standard test language for all systems - Common abbreviated test language for all systems (C/ATLAS)
SIST EN 61926-1:2002

Defines a high order language for electronics testing independent of any specific test system. Can be implemented on automatic test equipement (ATE)

  • Standard
    604 pages
    English language
    e-Library read for
    1 day
CLC
EN 61691-1:1997(Main)
Design automation - Part 1: VHDL language reference manual
SIST EN 61691-1:2002

This standard is based on IEEE Std 1076. It describes the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL)

  • Standard
    254 pages
    English language
    e-Library read for
    1 day
CLC
EN 61523-2:2002(Main)
Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries
SIST EN 61523-2:2004

Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.

  • Standard
    41 pages
    English language
    e-Library read for
    1 day
CLC
ES 59011:2001(Main)
Specification for the representation of Quality rules and metrics for Hardware and Software Design Languages
SIST ES 59011:2004

D116/196: TC 217 disbanded * D124/C049: Withdrawn

  • Standardization document
    18 pages
    English language
    e-Library read for
    1 day
CLC
ENV 50247-1:1998(Main)
Pinnacles Component Information Standard 1.2 - The PCIS tag library
SIST ENV 50247-1:2002

Document jointly prepared by the Pinnacles Group and TC 217 * D116/196: TC 217 disbanded * D124/C049: Withdrawn

  • Standardization document
    417 pages
    English language
    e-Library read for
    1 day
CLC
ENV 50247-2:1998(Main)
Pinnacles Component Information Standard 1.2 - The SGML declaration and SGML Document Type Definitions (DTDs)
SIST ENV 50247-2:2004

Document jointly prepared by the Pinnacles Group and TC 217 * D116/196: TC 217 disbanded * D124/C049: Withdrawn

  • Standardization document
    60 pages
    English language
    e-Library read for
    1 day
CLC
ENV 50219:1996(Main)
Description of the reliability test structures of the European mini test chip
SIST ENV 50219:2002

D116/196: TC 217 disbanded * D124/C049: Withdrawn

  • Standardization document
    35 pages
    English language
    e-Library read for
    1 day
CLC
ENV 50218:1996(Main)
Description of a parametrized European mini test chip
SIST ENV 50218:2002

D116/196: TC 217 disbanded * D124/C049: Withdrawn

  • Standardization document
    19 pages
    English language
    e-Library read for
    1 day
CLC
R217-020:2001(Main)
Electronic system specification languages - VHDL modelling guidelines
SIST-TP CLC/R217-020:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    47 pages
    English language
    e-Library read for
    1 day
CLC
R217-015:1999(Main)
Pinnacles Component Information Standard 1.2 - PCIS Tutorial
SIST-TP CLC/R217-015:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    66 pages
    English language
    e-Library read for
    1 day
CLC
R217-016:1999(Main)
Pinnacles Component Information Standard 1.2 - PCIS Sample Documents
SIST-TP CLC/R217-016:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    84 pages
    English language
    e-Library read for
    1 day
CLC
R217-018:1997(Main)
Report on the Viability of EDIF PCB Version (3 5 0)
SIST-TP CLC/R217-018:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    19 pages
    English language
    e-Library read for
    1 day
CLC
R217-017:1997(Main)
Evaluation techniques of the reliability test structures of the European mini test chip
SIST-TP CLC/R217-017:2004

Based on JESSI document * D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    22 pages
    English language
    e-Library read for
    1 day
CLC
R217-013:1997(Main)
Interchange formats - Evaluation of EDIF Version 3 0 0 level 0
SIST-TP CLC/R217-013:2004

Based on ESIP document * D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    18 pages
    English language
    e-Library read for
    1 day
CLC
R217-012:1996(Main)
Electronic system specification languages - VHDL 93 information core model
SIST-TP CLC/R217-012:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    270 pages
    English language
    e-Library read for
    1 day
CLC
R217-011:1996(Main)
Electronic system specification language - Express information model VHDL 87
SIST-TP CLC/R217-011:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    292 pages
    English language
    e-Library read for
    1 day
CLC
R217-014:1996(Main)
EDA framework - Task and session information model
SIST-TP CLC/R217-014:2004

Previous prENV 50224 * D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    21 pages
    English language
    e-Library read for
    1 day
CLC
R217-010:1996(Main)
Measurement techniques of the reliability test structures of the European mini test chip
SIST-TP CLC/R217-010:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    43 pages
    English language
    e-Library read for
    1 day
CLC
R217-001:1996(Main)
Basic information on submicron CMOS technology assessment flow
SIST-TP CLC/R217-001:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    8 pages
    English language
    e-Library read for
    1 day
CLC
R217-008:1995(Main)
Language requirements for high-level synthesis
SIST-TP CLC/R217-008:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    2 pages
    English language
    e-Library read for
    1 day
CLC
R217-003:1995(Main)
Validation of EXPRESS models
SIST-TP CLC/R217-003:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    2 pages
    English language
    e-Library read for
    1 day
CLC
R217-007:1995(Main)
Recommendations on necessary concepts to model behavioural semantics
SIST-TP CLC/R217-007:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    2 pages
    English language
    e-Library read for
    1 day
CLC
R217-002:1995(Main)
Comparison of different information modelling approaches and styles
SIST-TP CLC/R217-002:2004

Based on ECIP document * D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    2 pages
    English language
    e-Library read for
    1 day
CLC
R217-005:1995(Main)
Measurement techniques for the characterization of the European mini test chip
SIST-TP CLC/R217-005:2004

Based on JESSI document * D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    2 pages
    English language
    e-Library read for
    1 day
CLC
R217-004:1995(Main)
JESSI 0.8µm CMOS transistor model for analogue and digital circuit simulation
SIST-TP CLC/R217-004:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    2 pages
    English language
    e-Library read for
    1 day
CLC
EN 61523-1:2002(Main)
Delay and power calculation standards - Part 1: Integrated circuit delay and power calculation systems
SIST EN 61523-1:2002

The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs.

  • Standard
    425 pages
    English language
    e-Library read for
    1 day
CLC
EN 61691-3-2:2001(Main)
Behavioural languages - Part 3-2: Mathematical operation in VHDL
SIST EN 61691-3-2:2007

This set of packages provides a standard for the declaration of most frequently used real and complex elementary functions required for numerically oriented modeling applications. Use of these packages with their defined data types, constants, and functions is intended to provide a mechanism for writing VHDL models (compliant with IEEE Std 1076-1993) that are portable and interoperable with other VHDL models adhering to this standard. The standard serves a broad class of applications with reasonable ease of use and requires implementations that are of high quality. This standard includes package bodies, as described in annex B, which are available in electronic format either on a diskette affixed to the back cover, or as a downloadable file from the IEC Web Store.

  • Standard
    42 pages
    English language
    e-Library read for
    1 day
CLC
EN 61691-3-3:2001(Main)
Behavioural languages - Part 3-3: Synthesis in VHDL
SIST EN 61691-3-3:2007

This standard supports the synthesis and verification of hardware designs, by defining vector types for representing signed or unsigned integer values and providing standard interpretations of widely used scalar VHDL values. Includes package bodies, as described in annex A, which are available in electronic format either on a diskette affixed to the back cover, or as a downloadable file from the IEC Web Store.

  • Standard
    50 pages
    English language
    e-Library read for
    1 day
CLC
EN 62014-1:2002(Main)
Electronic design automation libraries - Part 1: Input/Output buffer information specifications (IBIS version 3.2)
SIST EN 62014-1:2002

Gives specifications for electronic behavioral of digital integrated circuit input/ output analog characteristics. It specifies a consistent software-parsable format for essential behavioral information. The goal of this standard is to support all simulators of all degrees of sophistication.

  • Standard
    87 pages
    English language
    e-Library read for
    1 day
CLC
ENV 50208-6:1997(Main)
Data Interchange format for Simulated and Measured Data (ISMD)
SIST ENV 50208-6:2002

D116/196: TC 217 disbanded * D124/C049: Withdrawn

  • Standardization document
    20 pages
    English language
    e-Library read for
    1 day
50

Frequently Asked Questions

IEC/TC 93 is a Technical Committee within CLC. It is named "IEC_TC_93" and is responsible for: Standardization to enable the integration and automation of electrotechnical product design, engineering, manufacturing, and logistics support processes, and to facilitate procedures for product operation and maintenance. This standardization should also support the integrated system design of electrotecnical products which encompasses the electrical, electronic, electromechanical and embedded software performance aspects. Such standardization involves comuter-sensible representations of electrotechnical hardware and embedded and control software for use in comuter-aided and auxiliary activities that may directly impact these processes. Representative activities include but are not limited to: - preparing data element descriptions of electrotechnical products, - preparing information models of such products, - preparing design, engineering, manufacturing and logistics support process application protocols, - identifying hardware and software requirements to support the use and validation of the application protocols, - developing methods and enabling technologies for TC 93 and other IEC Technical Committees. This work shall be carried out in collaboration with ISO/TC 184/SC 4 and other relevant technical committees in IEC and ISO This committee has published 30 standards.

IEC/TC 93 develops CLC standards in the area of V30 - DESIGN AUTOMATION. The scope of work includes: Standardization to enable the integration and automation of electrotechnical product design, engineering, manufacturing, and logistics support processes, and to facilitate procedures for product operation and maintenance. This standardization should also support the integrated system design of electrotecnical products which encompasses the electrical, electronic, electromechanical and embedded software performance aspects. Such standardization involves comuter-sensible representations of electrotechnical hardware and embedded and control software for use in comuter-aided and auxiliary activities that may directly impact these processes. Representative activities include but are not limited to: - preparing data element descriptions of electrotechnical products, - preparing information models of such products, - preparing design, engineering, manufacturing and logistics support process application protocols, - identifying hardware and software requirements to support the use and validation of the application protocols, - developing methods and enabling technologies for TC 93 and other IEC Technical Committees. This work shall be carried out in collaboration with ISO/TC 184/SC 4 and other relevant technical committees in IEC and ISO Currently, there are 30 published standards from this technical committee.

CLC is a standardization organization that develops and publishes standards to support industry, commerce, and regulatory requirements.

A Technical Committee (TC) in CLC is a group of experts responsible for developing international standards in a specific technical area. TCs are composed of national member body delegates and work through consensus to create standards that meet global industry needs. Each TC may have subcommittees (SCs) and working groups (WGs) for specialized topics.