IEC/TC 93 - IEC_TC_93

Defines a high order language for electronics testing independent of any specific test system. Can be implemented on automatic test equipement (ATE)

This standard is based on IEEE Std 1076. It describes the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL)

Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.

D116/196: TC 217 disbanded * D124/C049: Withdrawn

Document jointly prepared by the Pinnacles Group and TC 217 * D116/196: TC 217 disbanded * D124/C049: Withdrawn

Document jointly prepared by the Pinnacles Group and TC 217 * D116/196: TC 217 disbanded * D124/C049: Withdrawn

D116/196: TC 217 disbanded * D124/C049: Withdrawn

D116/196: TC 217 disbanded * D124/C049: Withdrawn

D116/196: TC 217 disbanded * D122/065: Withdrawn

D116/196: TC 217 disbanded * D122/065: Withdrawn

D116/196: TC 217 disbanded * D122/065: Withdrawn

D116/196: TC 217 disbanded * D122/065: Withdrawn

Based on JESSI document * D116/196: TC 217 disbanded * D122/065: Withdrawn

Based on ESIP document * D116/196: TC 217 disbanded * D122/065: Withdrawn

D116/196: TC 217 disbanded * D122/065: Withdrawn

D116/196: TC 217 disbanded * D122/065: Withdrawn

Previous prENV 50224 * D116/196: TC 217 disbanded * D122/065: Withdrawn

D116/196: TC 217 disbanded * D122/065: Withdrawn

D116/196: TC 217 disbanded * D122/065: Withdrawn

D116/196: TC 217 disbanded * D122/065: Withdrawn

D116/196: TC 217 disbanded * D122/065: Withdrawn

D116/196: TC 217 disbanded * D122/065: Withdrawn

Based on ECIP document * D116/196: TC 217 disbanded * D122/065: Withdrawn

Based on JESSI document * D116/196: TC 217 disbanded * D122/065: Withdrawn

D116/196: TC 217 disbanded * D122/065: Withdrawn

The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs.

This standard supports the synthesis and verification of hardware designs, by defining vector types for representing signed or unsigned integer values and providing standard interpretations of widely used scalar VHDL values. Includes package bodies, as described in annex A, which are available in electronic format either on a diskette affixed to the back cover, or as a downloadable file from the IEC Web Store.

This set of packages provides a standard for the declaration of most frequently used real and complex elementary functions required for numerically oriented modeling applications. Use of these packages with their defined data types, constants, and functions is intended to provide a mechanism for writing VHDL models (compliant with IEEE Std 1076-1993) that are portable and interoperable with other VHDL models adhering to this standard. The standard serves a broad class of applications with reasonable ease of use and requires implementations that are of high quality. This standard includes package bodies, as described in annex B, which are available in electronic format either on a diskette affixed to the back cover, or as a downloadable file from the IEC Web Store.

Gives specifications for electronic behavioral of digital integrated circuit input/ output analog characteristics. It specifies a consistent software-parsable format for essential behavioral information. The goal of this standard is to support all simulators of all degrees of sophistication.

D116/196: TC 217 disbanded * D124/C049: Withdrawn