SIST ETS 300 276 E1:2003
(Main)Network Aspects (NA); Metropolitan Area Network (MAN); Physical Layer Convergence Procedure (PLCP) for 622,080 Mbit/s CCITT Recommendations G.707, G.708 and G.709 SDH based systems
- Abstract
DE/NA-053033
- Status
- Published
- Publication Date
- 30-Nov-2003
- Current Stage
- 6060 - National Implementation/Publication (Adopted Project)
- Start Date
- 01-Dec-2003
- Due Date
- 01-Dec-2003
- Completion Date
- 01-Dec-2003
SIST ETS 300 276 E1:2003 is the Slovenian standard identical to ETSI ETS 300 276 Edition 1. It specifies the physical layer convergence procedure (PLCP) for Metropolitan Area Network (MAN) subnetwork operation at 622,080 Mbit/s on SDH-based systems. The document is aimed at telecom engineers, equipment suppliers, and operators who need to carry DQDB traffic over Synchronous Digital Hierarchy (SDH) transport.
What does SIST ETS 300 276 E1:2003 specify?
SIST ETS 300 276 E1:2003 defines how Distributed Queue Dual Bus (DQDB) slots are transferred using SDH at a 622,080 Mbit/s physical medium rate. The standard focuses on one use case: a MAN subnetwork using the PLCP described in clause 5.
The document is organized into five main clauses:
- Clause 1 sets the scope.
- Clause 2 lists the normative references.
- Clause 3 points to the source definitions.
- Clause 4 points to the source symbols and abbreviations.
- Clause 5 gives the PLCP mapping, overhead fields, fault handling, receiver and transmitter operation, and timing rules.
Clause 5 is supported by Figures 1 to 6 and Tables 1 to 3, which show the frame mapping, state machines, link status coding, and timing selection.
What are the key requirements of SIST ETS 300 276 E1:2003?
SIST ETS 300 276 E1:2003 is mainly a mapping and control specification. The most important points are how DQDB slots are framed in SDH, how overhead fields are used, and how the PLCP reacts to faults and timing changes.
How DQDB slots are carried in SDH
- Clause 5.1 maps DQDB slots into VC-4-4c virtual containers and uses SDH transport modules to carry them. In practice, this defines the path between the DQDB subnetwork and the SDH network.
- Clause 5.2 states that the PLCP frame format is VC-4-4c, arranged as 9 rows by 1 044 octets with a nominal duration of 125 μs. For implementation, this means the equipment must generate and accept frames on that timing.
- Clause 5.2 also allows a slot to cross a VC-4-4c boundary because the payload size is not an exact multiple of the 53-octet DQDB slot length. Slot boundaries are therefore recovered by the header check sequence (HCS) method, not by simple alignment.
How the overhead fields are used
- Clause 5.3 assigns functions to the path overhead octets. B3 carries Bit Interleaved Parity-8 (BIP-8) error monitoring, C2 identifies the payload construction, G1 carries path status, H4 carries the Link Status Signal (LSS) and slot offset, and M1-M2 carry DQDB layer management information.
- Clause 5.3.2 uses B3 for error monitoring over the previous VC-4-4c. This tells implementers where path error counts are reported and checked.
- Clause 5.3.3 sets C2 to code 14 HEX to identify an IEEE 802.6 payload and overhead structure.
- Clause 5.3.4 uses G1 to report Far End Block Error (FEBE) and Far End Receive Failure (FERF). Clause 5.3.5 uses H4 to signal link status between adjacent PLCP entities and to carry the slot offset indicator.
- Clause 5.3.6 keeps M1 and M2 for DQDB layer management information, and clause 5.3.7 reserves Z4 and Z5 for future standardisation. In practice, this separates operational fields from reserved space.
How slot delineation works
- Clause 5.6.1.1 defines slot delineation by the HCS method. The receiver checks a cyclic redundancy check over the slot header octets to find slot boundaries.
- The HCS slot delineation state machine has Sync, Presync, and Hunt states. This matters because the receiver must move between reliable alignment, searching, and recovery modes as HCS results change.
- Clause 5.6.1.1 also describes the transition logic for finding and losing slot synchronisation. That logic tells an implementer when to trust incoming slot boundaries and when to treat them as lost.
How the PLCP behaves during faults and out-of-service conditions
- Clause 5.4 says faults force the PLCP into Out-Of-Frame or Out-Of-Slot-Delineation states. A 1 ms timer is started, and invalid data indications are sent to the DQDB layer until recovery or timeout.
- If recovery does not arrive in time, the PLCP declares Loss-Of-Frame or Loss-Of-Slot-Delineation and sends DOWN status. This is the trigger for higher-layer protection and reconfiguration.
- Clause 5.5 allows the PLCP to bypass the DQDB layer when the layer is out of service. In that mode, SDH and PLCP overhead processing continues, while DQDB slot octets and management octets are relayed unmodified.
How transmission, link status, and timing are controlled
- Clause 5.6.2 says the transmitter continuously generates VC-4-4c frames and maps received slot data and management octets into them. Invalid data or no data leads to void slots, which are defined as 53 octets of zeroes.
- Clause 5.6.3 gives the Link Status Signal operations table. It links the framing state, incoming LSS, and physical layer connection control to the outgoing LSS and Ph-STATUS. For users, this is the decision logic that keeps the two buses consistent.
- Clause 5.6.4 gives the physical layer frame timing operations table. It selects the 125 μs timing source from the receiver states on Bus A and Bus B together with the DQDB timing request. This matters because the PLCP must keep the frame clock stable even when one bus fails.
What terms does SIST ETS 300 276 E1:2003 define?
SIST ETS 300 276 E1:2003 relies on the definitions in IEEE Standard 802.6 for its core terminology, and the following terms are central to the document:
- Physical Layer Convergence Procedure (PLCP) - The function that maps DQDB traffic into SDH VC-4-4c frames and recovers it at the receiving end.
- Distributed Queue Dual Bus (DQDB) - The MAN access method used by this standard, based on two buses and slot transfer.
- Virtual Container VC-4-4c - The SDH container used as the PLCP frame format for carrying DQDB slots.
- Header Check Sequence (HCS) - The CRC-based method used to find DQDB slot boundaries in the VC-4-4c payload.
- Link Status Signal (LSS) - The H4 coding used to report link state between adjacent PLCP entities.
- Far End Block Error (FEBE) - The G1 status code that reports the count of errored blocks detected by B3.
- Far End Receive Failure (FERF) - The G1 status signal used to indicate a persistent receive failure on the path.
Who uses SIST ETS 300 276 E1:2003?
SIST ETS 300 276 E1:2003 is used by people who design, integrate, or operate DQDB-based MAN equipment over SDH transport. Typical users include:
- telecom hardware engineers implementing PLCP functions
- network architects planning MAN interworking with SDH systems
- equipment vendors building transmit, receive, framing, and timing logic
- maintenance teams diagnosing link status, slot sync, and fault recovery
- interoperability and compliance engineers checking mapping, overhead coding, and state-machine behavior
What changed in SIST ETS 300 276 E1:2003 from the previous edition?
SIST ETS 300 276 E1:2003 corresponds to ETS 300 276 Edition 1. The document history records March 1994 as the first edition and March 1996 as the PDF conversion.
Which standards are used with SIST ETS 300 276 E1:2003?
| Standard | What it contributes |
|---|---|
| CCITT Recommendation G.707 | SDH bit rates |
| CCITT Recommendation G.708 | Network node interface for SDH |
| CCITT Recommendation G.709 | Synchronous multiplexing structure |
| CCITT Recommendation G.783 | SDH multiplexing equipment functional blocks and pointer interpretation states |
| CCITT Recommendation I.432 | ATM physical layer reference used for the HCS/HEC comparison |
| IEEE Standard 802.6 | DQDB definitions, primitives, management behavior, LSS and timing references |
| ETS 300 147 | SDH multiplexing structure and the J1 octet reference |
What does the SIST ETS 300 276 E1:2003 document contain?
SIST ETS 300 276 E1:2003 contains the VC-4-4c frame mapping for DQDB slots, the slot format, and the path overhead field definitions. It also includes the HCS slot delineation state machine and the framing state machine used by the receiver.
The document provides the LSS coding table and the physical layer frame timing operations table, both of which are used to control state exchange and clock selection. Figures 1 to 6 show the mapping and state transitions, while Tables 1 to 3 summarize the codes and timing behavior used during normal operation and fault recovery.
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Frequently Asked Questions
SIST ETS 300 276 E1:2003 is a standard published by the Slovenian Institute for Standardization (SIST). Its full title is "Network Aspects (NA); Metropolitan Area Network (MAN); Physical Layer Convergence Procedure (PLCP) for 622,080 Mbit/s CCITT Recommendations G.707, G.708 and G.709 SDH based systems". This standard covers: DE/NA-053033
DE/NA-053033
SIST ETS 300 276 E1:2003 is classified under the following ICS (International Classification for Standards) categories: 35.110 - Networking. The ICS classification helps identify the subject area and facilitates finding related standards.
SIST ETS 300 276 E1:2003 is available in PDF format for immediate download after purchase. The document can be added to your cart and obtained through the secure checkout process. Digital delivery ensures instant access to the complete standard document.
Standards Content (Sample)
SLOVENSKI STANDARD
01-december-2003
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IL]LþQLSODVWL 3/&3 ]DKLWURVW0ELWV±3ULSRURþLOD&&,77**LQ
* ±1D6'+WHPHOMHþLVLVWHPL
Network Aspects (NA); Metropolitan Area Network (MAN); Physical Layer Convergence
Procedure (PLCP) for 622,080 Mbit/s CCITT Recommendations G.707, G.708 and
G.709 SDH based systems
Ta slovenski standard je istoveten z: ETS 300 276 Edition 1
ICS:
35.110 Omreževanje Networking
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.
EUROPEAN ETS 300 276
TELECOMMUNICATION March 1994
STANDARD
Source: ETSI TC-NA Reference: DE/NA-053033
ICS: 33.080
MAN
Key words:
Network Aspects (NA);
Metropolitan Area Network (MAN)
Physical Layer Convergence Procedure (PLCP) for 622,080 Mbit/s
CCITT Recommendations G.707, G.708 and G.709
SDH based systems
ETSI
European Telecommunications Standards Institute
ETSI Secretariat
F-06921 Sophia Antipolis CEDEX - FRANCE
Postal address:
650 Route des Lucioles - Sophia Antipolis - Valbonne - FRANCE
Office address:
c=fr, a=atlas, p=etsi, s=secretariat - secretariat@etsi.fr
X.400: Internet:
Tel.: +33 92 94 42 00 - Fax: +33 93 65 47 16
Copyright Notification: No part may be reproduced except as authorized by written permission. The copyright and the
foregoing restriction extend to reproduction in all media.
© European Telecommunications Standards Institute 1994. All rights reserved.
New presentation - see History box
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ETS 300 276: March 1994
Whilst every care has been taken in the preparation and publication of this document, errors in content,
typographical or otherwise, may occur. If you have comments concerning its accuracy, please write to
"ETSI Editing and Committee Support Dept." at the address shown on the title page.
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ETS 300 276: March 1994
Contents
Foreword .5
1 Scope .7
2 Normative references.7
3 Definitions.7
4 Symbols and abbreviations .7
5 Physical layer convergence procedure for 622,080 Mbit/s CCITT Recommendations G.707,
G.708 and G.709 SDH based systems .8
5.1 Introduction .8
5.2 The PLCP frame format.8
5.3 PLCP path overhead field definitions.10
5.3.1 Path trace (J1).10
5.3.2 Bit interleaved parity - 8 (B3).10
5.3.3 Signal label (C2).10
5.3.4 Path status (G1) .10
5.3.5 Multiframe indicator (H4).11
5.3.6 DQDB layer management information octets (M1 - M2).11
5.3.7 Growth octets .11
5.4 PLCP behaviour during faults .12
5.5 PLCP behaviour during DQDB layer out of service .12
5.6 PLCP operation.13
5.6.1 Receiver operation .13
5.6.1.1 Slot delineation using the header check sequence
method.13
5.6.1.2 Framing state machine.14
5.6.2 Transmitter operation .17
5.6.3 Link status signal operations table .17
5.6.4 Physical layer frame timing operations table.18
History.20
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ETS 300 276: March 1994
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ETS 300 276: March 1994
Foreword
This European Telecommunication Standard (ETS) has been prepared by the Network Aspects (NA)
Technical Committee of the European Telecommunications Standards Institute (ETSI).
This ETS details the physical layer convergence procedure for a European Metropolitan Area Network
(MAN) based on the Distributed Queue Dual Bus (DQDB) access method as defined in IEEE Standard
802.6 [6] operating at a transmission rate of 622,080 Mbit/s in accordance with CCITT Recommendations
G.707 [1], G.708 [2] and G.709 [3].
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ETS 300 276: March 1994
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ETS 300 276: March 1994
1 Scope
This European Telecommunication Standard (ETS) defines the physical layer convergence procedure at
622,080 Mbit/s for use in the context of a subnetwork of a Metropolitan Area Network (MAN). Use of
methods defined in this ETS for other purposes is outside the scope of this ETS.
Methods of testing will be the subject of separate arrangements.
2 Normative references
This ETS incorporates, by dated or undated reference, provisions from other publications. These
normative references are cited at the appropriate places in the text and the publications are listed below.
For dated references, subsequent amendments to or revisions of these publications apply to this ETS only
when incorporated in it by amendment or revision. For undated references the latest edition of the
publication referred to applies.
[1] CCITT Recommendation G.707 (1991): "Synchronous Digital Hierarchy Bit
Rates".
[2] CCITT Recommendation G.708 (1991): "Network Node Interface for the
Synchronous Digital Hierarchy".
[3] CCITT Recommendation G.709 (1991): "Synchronous Multiplexing Structure".
[4] CCITT Recommendation G.783 (1991): "Characteristics of Synchronous Digital
Hierarchy (SDH) Multiplexing Equipment Functional Blocks".
[5] CCITT Recommendation I.432 (1991): "B-ISDN User-Network Interface -
Physical Layer Specification".
[6] IEEE Standard 802.6 (1990): "Distributed Queue Dual Bus (DQDB) Subnetwork
of a Metropolitan Area Network (MAN)".
[7] ETS 300 147: "Transmission and multiplexing; Synchronous digital hierarchy
multiplexing structure".
3 Definitions
For the purpose of this ETS, the definitions as defined in IEEE Standard 802.6 [6] shall apply.
4 Symbols and abbreviations
For the purpose of this ETS, the symbols and abbreviations as defined in IEEE Standard 802.6 [6] shall
apply.
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ETS 300 276: March 1994
5 Physical layer convergence procedure for 622,080 Mbit/s CCITT
Recommendations G.707, G.708 and G.709 SDH based systems
5.1 Introduction
This ETS defines a convergence procedure for transfer of Distributed Queue Dual Bus (DQDB) slots
using the Synchronous Digital Hierarchy (SDH) at a 622,080 Mbit/s physical medium rate.
The rates, formats, and other attributes of SDH are defined in CCITT Recommendations G.707 [1], G.708
[2] and G.709 [3]. DQDB slots are mapped into VC-4-4c virtual containers, and the VC-4-4c's are
transported using synchronous transport modules. A mapping of Asynchronous Transfer Mode (ATM)
cells into VC-4-4c can be found in CCITT Recommendation I.432 [5]. As ATM cells and DQDB slots are
identical in length (53 octets) and nearly identical in format, the mapping of DQDB slots into VC-4-4c is
identical to the ATM cell mapping into VC-4-4c except for the following:
- the use of the user channel (F2) and growth (Z3) octets for carrying DQDB layer management
information octets (M1 and M2);
- the use of two bit positions in the multiframe indicator (H4) octet for providing the DQDB Link Status
Signal (LSS);
- the use of VC-4-4c for propagating the DQDB layer 125 μs timing along the DQDB buses;
- the Header Check Sequence (HCS) method shall be used for providing slot boundary indication.
The HCS method for slot delineation is identical to the Header Error Control (HEC) method for ATM
cell delineation described in CCITT Recommendation I.432 [5], § 4.5.1.1 except for the fact that the
HCS is calculated over three octets of the DQDB slot header, whereas the ATM HEC is calculated
over four octets of the ATM cell header.
CCITT Recommendations G.707 [1], G.708 [2], and G.709 [3] shall be the primary references for
providing an SDH based physical layer for DQDB with the above modifications. Descriptions of POH field
definitions in this ETS other than M1-M2 and H4 fields are included for clarity and completeness only.
The SDH PLCP makes use of the optional status parameter in Ph-DATA indication and Ph-DATA request
primitives (see section 4.2 of IEEE Standard 802.6 [6]). Hence, the status parameter shall be mandatory
for the service provided by the SDH PLCP.
In this ETS, the terms Bus x, Bus y, Ph-SAP_x, and Ph-SAP_y (x = A or B; y = B or A) are used. Bus x
enters a DQDB node at Ph-SAP_x and exits at Ph-SAP_y, whereas Bus y enters a DQDB node at Ph-
SAP_y and exits at Ph-SAP_x.
5.2 The PLCP frame format
The PLCP frame format is a virtual container VC-4-4c that consists of 9 rows by 1 044 octets. The VC-4-
4c has a nominal duration of 125 μs. The VC-4-4c frame rate shall provide the 125 μs timing information.
The VC-4-4c frames are transported between peer PLCPs by the SDH transmission system.
DQDB slots are mapped into the VC-4-4c as illustrated in figure 1. The VC-4-4c consists of one column
(nine octets) of Path Overhead (POH), three columns of unused octets plus a 9 row by 1 040 column
payload capacity.
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ETS 300 276: March 1994
4 octets 1 040 octets
J1
VC-4-4c
B3
C2
G1
M1
9 rows
H4
M2
Z4
Z5
53 octets
VC-4-4c Path Overhead
DQDB slot
Figure 1: VC-4-4c PLCP mapping for DQDB
The DQDB slots are located horizontally (by row) in the VC-4-4c payload capacity with the slot boundaries
aligned with the VC-4-4c octet boundaries. Because the VC-4-4c payload capacity (9 360 octets) is not an
integer multiple of the DQDB slot length (53 octets), a slot is allowed to cross the VC-4-4c boundary. Slot
boundary indication shall be provided using the HCS method.
5 octet slot header 48 octet slot payload
HCS
3 octets covered
by HCS
Figure 2: DQDB slot format
The slot format is illustrated in figure 2. The slot payload of 48 octets shall be scrambled before VC-4-4c
framing. The scrambler operates for the duration of the 48 octet slot payload. Operation is suspended and
the scrambler state is retained at all other times. A self-synchronous scrambler with generator polynomial
x +1 shall be used. In the reverse operation, following termination of the VC-4-4c signal and slot
delineation, the slot payload shall be descrambled. The descrambler shall operate for the duration of the
assumed slot payload according to the derived slot delineation (see subclause 5.6.1.1). Operation shall be
suspended and the descrambler state shall be retained at all other times.
At the transmitting PLCP, an eight bit pattern shall be added (modulo 2) to the HCS field of the slot
headers. At the receiving PLCP, the same bit pattern shall be subtracted (equal to add modulo 2) from the
HCS field of the assumed slot headers. The bit pattern shall be (01010101).
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ETS 300 276: March 1994
5.3 PLCP path overhead field definitions
The first column of the VC-4-4c contains the path overhead octets. The following subclauses describe
each of the VC-4-4c path overhead octets and their functions. As previously noted, these descriptions are
consistent with CCITT Recommendation G.709 [3] except for the use of the user channel (F2), growth
(Z3), and multiframe indicator (H4) octets. Values of octets are described as bit patterns. The leftmost bit
of each octet is most significant.
The PLCP path is defined between two adjacent peer PLCP entities. All path overhead octets other than
M1 and M2 are related to PLCP operation and are terminated/generated at each PLCP on the
subnetwork. The M1 and M2 octets are provided for the transport of DQDB layer management information
octets and shall not be processed by the PLCP.
5.3.1 Path trace (J1)
For the definition of the J1 octet see ETS 300 147 [7].
5.3.2 Bit interleaved parity - 8 (B3)
The B3 octet is allocated for the PLCP path error monitoring function. This function shall be a Bit
Interleaved Parity 8 (BIP-8) code using even parity. The PLCP path BIP-8 is calculated over all bits of the
previous VC-4-4c. The computed BIP-8 is placed in the B3 octet of the current VC-4-4c. The BIP-8 is
calculated after the PLCP scrambling of the slot payload.
A BIP-8 is an 8 bit code in which the first bit of the BIP-8 code calculates even parity over the first bit of
each octet in the VC-4-4c, the second bit of the BIP-8 code calculates even parity over the second bit of
each octet in the VC-4-4c, etc. Therefore, the BIP-8 code provides for 8 separate even parity codes
covering the corresponding bit of each octet in the VC-4-4c.
5.3.3 Signal label (C2)
The C2 octet is allocated to indicate the construction of the VC-4-4c payload. The value of this octet shall
be set to code 14 HEX, which indicates an IEEE Standard 802.6 [6] payload and overhead structure.
5.3.4 Path status (G1)
The G1 octet is allocated to convey the received PLCP status and performance to the transmitting PLCP.
This octet permits the status and performance of the complete duplex PLCP path to be monitored by
either PLCP entity. The coding of the G1 octet is illustrated in figure 3.
4 bits 1 bit 3 bits
FEBE FERF Reserved
Far End Block Error Far End
Recieve
Failure
Figure 3: Path status (G1) coding
The four most significant bits of the G1 octet are the Far End Block Error (FEBE) code which shall be
used to convey the count of interleaved-bit blocks that have been detected to be in error by the PLCP BIP-
8 code in the preceding VC-4-4c. This count has nine legal values, namely zero (0000) to eight (1000)
errors. The remaining seven possible codes (1001 through 1111) shall be interpreted as zero errors.
The fifth bit is the Far End Receive Failure (FERF) signal. The FERF alerts the transmitting PLCP that a
received failure indication has been declared along the PLCP path. When an incoming failure (i.e. the
framing state machine in Loss-Of-Frame or Loss-Of-Slot-Delineation states, (see subclause 5.6.1.2) is
detected on Bus x (x = A or B) which persists for 2,5 ± 0,5 seconds, a FERF shall be generated on Bus y
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ETS 300 276: March 1994
(y = B or A) by setting the fifth bit of the G1 octet to one (1). FERF is detected by a one (1) in the fifth bit of
the G1 octet for ten consecutive VC-4-4cs. When the incoming failure has ceased for 15 ± 5 seconds,
FERF shall be removed from Bus y by setting the fifth bit of the G1 octet to zero (0). Removal of FERF is
detected by a zero (0) in the fifth bit of the G1 octet for ten consecutive VC-4-4c's.
The remaining three least significant bits are reserved for future standardisation. The transmitting PLCP
shall encode these bits to the default code of (000). The receiver PLCP shall be capable of ignoring the
values contained in these bits.
5.3.5 Multiframe indicator (H4)
The H4 octet is the multiframe indicator for payloads. The coding of the H4 octet is illustrated in figure 4.
2 bits 6 bits
LSS Slot Offset Indicator
Link Status Signal
Figure 4: Multiframe indicator (H4) coding
The two most significant bits shall be used for the LSS code as described in section 11.3.2 of IEEE
Standard 802.6 [6]. The LSS shall be used to communicate information about the status of the
transmission link between two adjacent PLCP entities.
The LSS codes for the H4 octet are shown in table 1.
Table 1: LSS codes
LSS code LSS name Link status
00 connected Received link connected
11 rx_link_dn Received link down, no input or
forced down
01 rx_link_up Received link up
10 hob_incapable Lack of upstream head of bus
capability
The six least significant bits of the H4 octet form the slot offset indicator. The slot offset indicator shall
contain a binary number indicating the offset in o
...