IEC 62530:2007

IEC 62530
Edition 1.0 2007-11
™
IEEE 1800
INTERNATIONAL
STANDARD
Standard for SystemVerilog – Unified Hardware Design, Specification, and
Verification Language
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IEC 62530
Edition 1.0 2007-11
™
IEEE 1800
INTERNATIONAL
STANDARD
Standard For SystemVerilog – Unified +ardware 'esign, 6pecification, and
Verification Language
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
XH
ICS 25.040 ISBN 2-8318-9349-6
– 2 – IEC 62530:2007(E)
IEEE 1800-2005(E)
CONTENTS
IEEE introduction. 10
FOREWORD . 13
1. Overview. 14
1.1 Scope. 14
1.2 Purpose. 14
1.3 Conventions used in this standard . 16
1.4 Syntactic description. 16
1.5 Use of color in this standard . 17
1.6 Contents of this standard. 17
1.7 Examples. 20
1.8 Prerequisites. 20
2. Normative references. 22
3. Literal values. 24
3.1 Introduction. 24
3.2 Literal value syntax. 24
3.3 Integer and logic literals . 25
3.4 Real literals . 25
3.5 Time literals . 25
3.6 String literals. 25
3.7 Array literals . 26
3.8 Structure literals. 26
4. Data types . 22
4.1 Introduction. 28
4.2 Data type syntax. 29
4.3 Integer data types . 30
4.4 Real and shortreal data types . 31
4.5 Void data type. 31
4.6 Chandle data type. 31
4.7 String data type . 32
4.8 Event data type. 37
4.9 User-defined types . 37
4.10 Enumerations . 39
4.11 Structures and unions. 44
4.12 Class. 50
4.13 Singular and aggregate types . 50
4.14 Casting . 50
4.15 $cast dynamic casting . 51
4.16 Bit-stream casting . 52
4.17 Default attribute type . 55
5. Arrays. 56
5.1 Introduction. 56
5.2 Packed and unpacked arrays . 56
5.3 Multiple dimensions . 57
5.4 Indexing and slicing of arrays. 58
5.5 Array querying functions . 59
5.6 Dynamic arrays . 59
5.7 Array assignment . 61
5.8 Arrays as arguments. 62
5.9 Associative arrays . 63
Published by IEC under licence from IEEE. © 2005 IEEE. All rights reserved.
IEEE 1800-2005(E)
5.10 Associative array methods .66
5.11 Associative array assignment.68
5.12 Associative array arguments.69
5.13 Associative array literals.69
5.14 Queues .69
5.15 Array manipulation methods .72
6. Data declarations.78
6.1 Introduction.78
6.2 Data declaration syntax.78
6.3 Constants.79
6.4 Variables . 83
6.5 Nets . 84
6.6 Scope and lifetime .85
6.7 Nets, regs, and logic.86
6.8 Signal aliasing.87
6.9 Type compatibility.89
6.10 Type operator.92
7. Classes .94
7.1 Introduction.94
7.2 Syntax .94
7.3 Overview.95
7.4 Objects (class instance).96
7.5 Object properties.96
7.6 Object methods .97
7.7 Constructors .97
7.8 Static class properties.98
7.9 Static methods.99
7.10 This .99
7.11 Assignment, renaming, and copying. 100
7.12 Inheritance and subclasses . 101
7.13 Overridden members. 101
7.14 Super . 102
7.15 Casting . 103
7.16 Chaining constructors . 103
7.17 Data hiding and encapsulation.104
7.18 Constant class properties . 104
7.19 Abstract classes and virtual methods .105
7.20 Polymorphism: dynamic method lookup.106
7.21 Class scope resolution operator :: .106
7.22 Out-of-block declarations .107
7.23 Parameterized classes .108
7.24 Typedef class .109
7.25 Classes and structures .110
7.26 Memory management .110
8. Operators and expressions .112
8.1 Introduction.112
8.2 Operator syntax.112
8.3 Assignment operators . 114
8.4 Operations on logic and bit types . 114
8.5 Wild equality and wild inequality. 115
8.6 Real operators . 115
Published by IEC under licence from IEEE. © 2005 IEEE. All rights reserved.

– 4 – IEC 62530:2007(E)
IEEE 1800-2005(E)
8.7 Size. 116
8.8 Sign . 116
8.9 Operator precedence and associativity . 116
8.10 Built-in methods . 116
8.11 Static prefixes . 117
8.12 Concatenation . 118
8.13 Assignment patterns. 119
8.14 Tagged union expressions and member access. 124
8.15 Aggregate expressions . 125
8.16 Operator overloading . 125
8.17 Streaming operators (pack/unpack) . 127
8.18 Conditional operator . 131
8.19 Set membership. 131
9. Scheduling semantics. 134
9.1 Execution of a hardware model and its verification environment . 134
9.2 Event simulation . 134
9.3 The stratified event scheduler . 134
9.4 The PLI callback control points. 138
10. Procedural statements and control flow. 140
10.1 Introduction. 140
10.2 Statements. 140
10.3 Blocking and nonblocking assignments . 141
10.4 Selection statements. 142
10.5 Loop statements . 149
10.6 Jump statements. 151
10.7 Final blocks. 151
10.8 Named blocks and statement labels . 152
10.9 Disable . 153
10.10 Event control. 154
10.11 Level-sensitive sequence controls . 156
10.12 Procedural assign and deassign removal . 156
11. Processes. 158
11.1 Introduction. 158
11.2 Combinational logic. 158
11.3 Latched logic. 159
11.4 Sequential logic. 159
11.5 Continuous assignments .159
11.6 fork.join. 160
11.7 Process execution threads .161
11.8 Process control. 161
11.9 Fine-grain process control .163
12. Tasks and functions . 166
12.1 Introduction. 166
12.2 Tasks . 166
12.3 Functions. 168
12.4 Task and function argument passing . 170
12.5 Import and export functions. 173
13. Random constraints. 176
13.1 Introduction. 176
Published by IEC under licence from IEEE. © 2005 IEEE. All rights reserved.

IEEE 1800-2005(E)
13.2 Overview. 176
13.3 Random variables . 179
13.4 Constraint blocks . 181
13.5 Randomization methods . 194
13.6 In-line constraints—randomize() with. 197
13.7 Disabling random variables with rand_mode() . 197
13.8 Controlling constraints with constraint_mode() . 198
13.9 Dynamic constraint modification. 199
13.10 In-line random variable control . 200
13.11 Randomization of scope variables—std::randomize(). 201
13.12 Random number system functions and methods . 202
13.13 Random stability . 204
13.14 Manually seeding randomize . 206
13.15 Random weighted case—randcase . 207
13.16 Random sequence generation—randsequence. 208
14. Interprocess synchronization and communication. 216
14.1 Introduction. 216
14.2 Semaphores. 216
14.3 Mailboxes. 217
14.4 Parameterized mailboxes . 220
14.5 Event . 221
14.6 Event sequencing: wait_order() . 223
14.7 Event variables. 224
15. Clocking blocks . 226
15.1 Introduction. 226
15.2 Clocking block declaration . 226
15.3 Input and output skews . 228
15.4 Hierarchical expressions . 229
15.5 Signals in multiple clocking blocks . 229
15.6 Clocking block scope and lifetime. 229
15.7 Multiple clocking blocks example. 230
15.8 Interfaces and clocking blocks. 230
15.9 Clocking block events. 232
15.10 Cycle delay: ## . 232
15.11 Default clocking. 233
15.12 Input sampling . 234
15.13 Synchronous events . 234
15.14 Synchronous drives. 235
16. Program block. 238
16.1 Introduction. 238
16.2 The program construct . 238
16.3 Eliminating testbench races . 240
16.4 Blocking tasks in cycle/event mode. 241
16.5 Programwide space and anonymous programs. 241
16.6 Program control tasks . 242
17. Assertions. 244
17.1 Introduction. 244
17.2 Immediate assertions. 244
17.3 Concurrent assertions overview. 246
17.4 Boolean expressions . 247
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Published by IEC under licence from IEEE. © 2005 IEEE. All rights reserved.

– 6 – IEC 62530:2007(E)
IEEE 1800-2005(E)
17.5 Sequences. 249
17.6 Declaring sequences . 252
17.7 Sequence operations . 255
17.8 Manipulating data in a sequence. 262
17.9 Calling subroutines on match of a sequence. 276
17.10 System functions. 277
17.11 Declaring properties. 277
17.12 Multiclock support. 290
17.13 Concurrent assertions. 298
17.14 Clock resolution. 304
17.15 Binding properties to scopes or instances. 310
17.16 Expect statement . 312
17.17 Clocking blocks and concurrent assertions. 313
18. Coverage . 316
18.1 Introduction. 316
18.2 Defining the coverage model: covergroup. 316
18.3 Using covergroup in classes . 319
18.4 Defining coverage points . 321
18.5 Defining cross coverage. 327
18.6 Specifying coverage options. 331
18.7 Predefined coverage methods . 336
18.8 Predefined coverage system tasks and functions. 337
18.9 Organization of option and type_option members . 337
18.10 Coverage computation . 338
19. Hierarchy . 340
19.1 Introduction. 340
19.2 Packages. 340
19.3 Compilation unit support .345
19.4 Top-level instance. 346
19.5 Module declarations. 347
19.6 Nested modules. 347
19.7 Extern modules . 349
19.8 Port declarations . 350
19.9 List of port expressions. 351
19.10 Time unit and precision . 339
19.11 Module instances . 353
19.12 Port connection rules . 357
19.13 Name spaces . 359
19.14 Hierarchical names . 360
20. Interfaces. 362
20.1 Introduction. 362
20.2 Interface syntax. 363
20.3 Ports in interfaces. 367
20.4 Modports. 368
20.5 Interfaces and specify blocks. 374
20.6 Tasks and functions in interfaces. 375
20.7 Parameterized interfaces . 381
20.8 Virtual interfaces. 383
20.9 Access to interface objects. 387
21. Configuration libraries. 390
Published by IEC under licence from IEEE. © 2005 IEEE. All rights reserved.

IEEE 1800-2005(E)
21.1 Introduction. 390
21.2 Libraries . 390
22. System tasks and system functions. 392
22.1 Introduction. 392
22.2 Type name function . 392
22.3 Expression size system function . 393
22.4 Range system function. 393
22.5 Shortreal conversions. 394
22.6 Array querying system functions. 394
22.7 Assertion severity system tasks . 396
22.8 Assertion control system tasks. 397
22.9 Assertion system functions . 397
22.10 Random number system functions. 398
22.11 Program control . 398
22.12 Coverage system functions . 398
22.13 Enhancements to Verilog system tasks. 398
22.14 $readmemb and $readmemh. 400
22.15 $writememb and $writememh . 400
22.16 File format considerations for multidimensional unpacked arrays. 401
22.17 System task arguments for multidimensional unpacked arrays. 402
23. Compiler directives. 404
23.1 Introduction. 404
23.2 ‘define macros. 404
23.3 `include . 405
23.4 `begin_keywords and `end_keywords . 405
24. Value change dump (VCD) data. 408
24.1 Introduction. 408
24.2 VCD extensions . 408
25. Deprecated constructs . 410
25.1 Introduction. 410
25.2 Defparam statements. 410
25.3 Procedural assign and deassign statements. 410
26. Direct programming interface (DPI). 412
26.1 Overview. 412
26.2 Two layers of the DPI. 413
26.3 Global name space of imported and exported functions. 414
........................................................................................... 415
26.4 Imported tasks and functions .
26.5 Calling imported functions . 421
26.6 Exported functions. 423
26.7 Exported tasks. 423
26.8 Disabling DPI tasks and functions. 424
27. SystemVerilog VPI object model . 426
27.1 Introduction. 426
27.2 Module (supersedes 26.6.1 of IEEE Std 1364). 428
27.3 Interface . 429
27.4 Modport .
...