ISO 17987-8:2019

INTERNATIONAL ISO
STANDARD 17987-8
First edition
2019-10
Road vehicles — Local Interconnect
Network (LIN) —
Part 8:
Electrical physical layer (EPL)
specification: LIN over DC powerline
(DC-LIN)
Véhicules routiers — Réseau Internet local (LIN) —
Partie 8: Spécification de couche physique électrique (EPL): LIN sur
ligne d'alimentation en courant continu (DC-LIN)
Reference number
©
ISO 2019
© ISO 2019
All rights reserved. Unless otherwise specified, or required in the context of its implementation, no part of this publication may
be reproduced or utilized otherwise in any form or by any means, electronic or mechanical, including photocopying, or posting
on the internet or an intranet, without prior written permission. Permission can be requested from either ISO at the address
below or ISO’s member body in the country of the requester.
ISO copyright office
CP 401 • Ch. de Blandonnet 8
CH-1214 Vernier, Geneva
Phone: +41 22 749 01 11
Fax: +41 22 749 09 47
Email: copyright@iso.org
Website: www.iso.org
Published in Switzerland
ii © ISO 2019 – All rights reserved

Contents Page
Foreword .iv
Introduction .v
1 Scope . 1
2 Normative references . 1
3 Terms, definitions, symbols, and abbreviated terms . 1
3.1 Terms and definitions . 2
3.2 Symbols and abbreviated terms. 2
4 Electrical physical layer requirements . 5
4.1 General . 5
4.2 Transmitter characteristics . 6
4.2.1 Transmit signal specification . 6
4.2.2 Byte field modulation scheme . 7
4.2.3 Break field modulation scheme .14
4.2.4 Wake-up signal modulation scheme .15
4.3 Timing requirements .18
4.3.1 Bit rate tolerance .18
4.3.2 Bit timing .19
4.3.3 Bit sample timing .19
4.3.4 TXD assert timeout event .19
4.3.5 Delay between transmitted byte field (DC-LIN node A) and received byte
field (DC-LIN node A).19
4.3.6 Delay between transmitted byte field (DC-LIN node A) and received byte
field (DC-LIN node B) . .19
4.4 Receiver characteristics .21
4.5 Electrical parameters .21
4.5.1 General configuration — Coupling to the DC powerline .21
4.5.2 Signal specification .22
4.5.3 Line-out monitoring .23
4.5.4 ESD compliance .28
4.6 Communication in the presence of faults.28
Annex A (informative) DC-LIN EPL peripheral interface design considerations .30
Annex B (normative) DC-LIN EPL conformance test plan .31
Bibliography .56
Foreword
ISO (the International Organization for Standardization) is a worldwide federation of national standards
bodies (ISO member bodies). The work of preparing International Standards is normally carried out
through ISO technical committees. Each member body interested in a subject for which a technical
committee has been established has the right to be represented on that committee. International
organizations, governmental and non-governmental, in liaison with ISO, also take part in the work.
ISO collaborates closely with the International Electrotechnical Commission (IEC) on all matters of
electrotechnical standardization.
The procedures used to develop this document and those intended for its further maintenance are
described in the ISO/IEC Directives, Part 1. In particular, the different approval criteria needed for the
different types of ISO documents should be noted. This document was drafted in accordance with the
editorial rules of the ISO/IEC Directives, Part 2 (see www .iso .org/directives).
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. ISO shall not be held responsible for identifying any or all such patent rights. Details of
any patent rights identified during the development of the document will be in the Introduction and/or
on the ISO list of patent declarations received (see www .iso .org/patents).
Any trade name used in this document is information given for the convenience of users and does not
constitute an endorsement.
For an explanation of the voluntary nature of standards, the meaning of ISO specific terms and
expressions related to conformity assessment, as well as information about ISO's adherence to the
World Trade Organization (WTO) principles in the Technical Barriers to Trade (TBT) see www .iso
.org/iso/foreword .html.
This document was prepared by Technical Committee ISO/TC 22, Road vehicles, Subcommittee SC 31,
Data communication.
A list of all parts in the ISO 17987 series can be found on the ISO website.
Any feedback or questions on this document should be directed to the user’s national standards body. A
complete listing of these bodies can be found at www .iso .org/members .html.
iv © ISO 2019 – All rights reserved

Introduction
ISO 17987 (all parts) specifies the use cases, communication protocol and physical layer requirements
of an in-vehicle communication network called Local Interconnect Network (LIN).
The LIN protocol as proposed is an automotive-focused low speed UART-based network (Universal
Asynchronous Receiver Transmitter). Some of the key characteristics of the LIN protocol are signal-
based communication, schedule table-based frame transfer, master/slave communication with error
detection, node configuration and diagnostic service transportation.
The LIN protocol is for low cost automotive control applications, for example door module and air
conditioning systems. It serves as a communication infrastructure for low-speed control applications
in vehicles by providing:
— signal-based communication to exchange information between applications in different nodes;
— bit rate support from 1 kbit/s to 20 kbit/s;
— deterministic schedule table-based frame communication;
— network management that wakes up and puts the LIN cluster into sleep mode in a controlled manner;
— status management that provides error handling and error signalling;
— transport layer that allows large amount of data to be transported (such as diagnostic services);
— specification of how to handle diagnostic services;
— electrical physical layer specifications;
— node description language describing properties of slave nodes;
— network description file describing behaviour of communication;
— application programmer's interface.
ISO 17987 (all parts) is based on the open systems interconnection (OSI) basic reference model as
specified in ISO/IEC 7498-1 which structures communication systems into seven layers.
The OSI model structures data communication into seven layers called (top down) application layer
(layer 7), presentation layer, session layer, transport layer, network layer, data link layer and physical
layer (layer 1). A subset of these layers is used in ISO 17987 (all parts).
ISO 17987 (all parts) distinguishes between the services provided by a layer to the layer above it and
the protocol used by the layer to send a message between the peer entities of that layer. The reason for
this distinction is to make the services, especially the application layer services and the transport layer
services, reusable also for other types of networks than LIN. In this way, the protocol is hidden from the
service user and it is possible to change the protocol if special system requirements demand it.
ISO 17987 (all parts) provides all documents and references required to support the implementation of
the requirements related to the following.
— ISO 17987-1: This part provides an overview of the ISO 17987 (all parts) and structure along with
the use case definitions and a common set of resources (definitions, references) for use by all
subsequent parts.
— ISO 17987-2: This part specifies the requirements related to the transport protocol and the network
layer requirements to transport the PDU of a message between LIN nodes.
— ISO 17987-3: This part specifies the requirements for implementations of the LIN protocol on the
logical level of abstraction. Hardware related properties are hidden in the defined constraints.
— ISO 17987-4: This part specifies the requirements for implementations of active hardware
components which are necessary to interconnect the protocol implementation.
— ISO/TR 17987-5: This part specifies the LIN application programmers interface (API) and the
node configuration and identification services. The node configuration and identification services
are specified in the API and define how a slave node is configured and how a slave node uses the
identification service.
— ISO 17987-6: This part specifies tests to check the conformance of the LIN protocol implementation
according to ISO 17987-2 and ISO 17987-3. This comprises tests for the data link layer, the network
layer and the transport layer.
— ISO 17987-7: This part specifies tests to check the conformance of the LIN electrical physical layer
implementation (logical level of abstraction) according to ISO 17987-4.
— ISO 17987-8: This part specifies the requirements for implementations of the DC powerline electrical
physical layer (EPL) for the LIN communications system as well as a conformance test plan for the EPL.
vi © ISO 2019 – All rights reserved

INTERNATIONAL STANDARD ISO 17987-8:2019(E)
Road vehicles — Local Interconnect Network (LIN) —
Part 8:
Electrical physical layer (EPL) specification: LIN over DC
powerline (DC-LIN)
1 Scope
This document specifies an additional electrical physical layer (EPL) for the Local Interconnect Network
(LIN) of the ISO 17987 series. It specifies the transmission over DC powerline without affecting the LIN
higher layers, hereafter named DC-LIN.
The DC-LIN EPL uses a high-frequency modulated carrier to propagate UART bytes (byte-oriented)
over the DC powerline.
This document specifies the electrical characteristics, the modulation method of the transmission, and
how to impose the carrier signal on the DC powerlines.
The DC-LIN EPL supports bit rates of 9 615 bit/s, 10 417 bit/s, and 19 230 bit/s.
The DC-LIN EPL is applicable for a wide range of DC powerlines including 12-V and 24-V operations,
allowing communicating between different DC powerlines via a coupling capacitor. A DC-LIN EPL
interface to powerline example is described in Annex A.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies. For
undated references, the latest edition of the referenced document (including any amendments) applies.
ISO 17987-4:2016, Road vehicles — Local Interconnect Network (LIN) — Part 4: Electrical physical layer
(EPL) specification 12 V/24 V
ISO 17987-6, Road vehicles — Local Interconnect Network (LIN) — Part 6: Protocol conformance test
specification
IEC 61000-4-2, Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques -
Electrostatic discharge immunity test
3 Terms, definitions, symbols, and abbreviated terms
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminological databases for use in standardization at the following addresses:
— ISO Online browsing platform: available at https: //www .iso .org/obp
— IEC Electropedia: available at http: //www .electropedia .org/
3.1 Terms and definitions
3.1.1
BR_9_6K
DC-LIN EPL operating at nominal bit rate of 9 615 bit/s
3.1.2
BR_10K
DC-LIN EPL operating at nominal bit rate of 10 417 bit/s
3.1.3
BR_19_2K
DC-LIN EPL operating at nominal bit rate of 19 230 bit/s
3.1.4
byte field
byte that consists of one start bit, eight data bits, and one stop bit
3.1.5
byte field sync preamble
sequence of phase shifts at the beginning of EPL byte field modulation used for byte synchronization
3.1.6
carrier frequency
DC-LIN EPL center frequency that is altered (modulated) to transfer data
3.1.7
coupling capacitor
capacitor for blocking the DC powerline voltage to/from a DC-LIN EPL
3.1.8
DC-LIN EPL RX mode
mode that DC-LIN EPL de-asserts line-out and controls RXD according to signal at line-in
3.1.9
DC-LIN EPL TX mode
mode that DC-LIN EPL controls line-out according to logic state present at TXD
3.1.10
start bit
logic low (‘0’) of the first bit of a byte field
3.1.11
stop bit
logic high (‘1’) of the last bit of a byte field
3.2 Symbols and abbreviated terms
'0' logical 0
'1' logical 1
AC alternate current
API application programmers interface
B byte field data bit signalled on RXD at DC-LIN EPL receiver side
data_bit
B byte field data bit signalled on RXD at DC-LIN EPL transmitter side
data_bit_local
2 © ISO 2019 – All rights reserved

B break delimiter signalled on RXD at DC-LIN EPL receiver side
del
B break delimiter signalled on RXD at DC-LIN EPL transmitter side
del_local
B byte field error data bit signalled on RXD at DC-LIN EPL transmitter side
err_data_bit_local
B byte field frame error stop bit signalled on RXD at DC-LIN EPL receiver side
fe_stop_bit
B byte field frame error stop bit signalled on RXD at DC-LIN EPL transmitter side
fe_stop_bit_local
B break field delimiter frame error signalled on RXD at DC-LIN EPL transmitter side
fe_del_local
B byte field frame error start bit signalled on RXD at DC-LIN EPL transmitter side
fe_start_bit_local
BR DC-LIN EPL operating bit rate
B byte field start bit signalled on RXD at DC-LIN EPL receiver side
start_bit
B byte field start bit signalled on RXD at DC-LIN EPL transmitter side
start_bit_local
B byte field stop bit signalled on RXD at DC-LIN EPL receiver side
stop_bit
B byte field stop bit signalled on RXD at DC-LIN EPL transmitter side
stop_bit_local
CB consecutive byte field transmission
TX
CF maximal number of carrier frequencies implemented in IUT transmit signal
max
DC direct current
EPL electrical physical layer
ESD electrostatic discharge
fc carrier frequency
i
FB first byte field transmission
TX
I in-phase signal component
IUT implementation under test
bit/s bit per second
LIN Local Interconnect Network
line-in modulated carrier signal input pin to the EPL from the DC powerline
line-out modulated carrier signal output pin from the EPL to the DC powerline
LT lower tester
L line-out sampled monitoring level
out_lev
L line-out monitoring peak threshold level
out_thr_lev
L line-out monitoring error condition
out_err_cond
max. maximum
min. minimum
P nominal length of modulated byte field in t
byte_length BIT
P nominal length of modulated byte field data bit
data_bit_len
P data bit modulation phases
data
st
P data bit ‘1’ 1 phase shift
dh_1
nd
P data bit ‘1’ 2 phase shift
dh_2
rd
P data bit ‘1’ 3 phase shift
dh_3
st
P data bit ‘0’ 1 phase shift
dl_1
nd
P data bit ‘0’ 2 phase shift
dl_2
rd
P data bit ‘0’ 3 phase shift
dl_3
P reference phase of consecutive byte transmission
ref_consec
P reference phase of the first byte transmission
ref_first
P sync preamble modulation phases
sync_p
st
P sync preamble 1 phase shift
sp_1
nd
P sync preamble 2 phase shift
sp_2
rd
P sync preamble 3 phase shift
sp_3
th
P sync preamble 4 phase shift
sp_4
th
P sync preamble 5 phase shift
sp_5
th
P sync preamble 6 phase shift
sp_6
th
P sync preamble 7 phase shift
sp_7
th
P sync preamble 8 phase shift
sp_8
th
P sync preamble 9 phase shift
sp_9
th
P sync preamble 10 phase shift
sp_10
th
P sync preamble 11 phase shift
sp_11
th
P sync preamble 12 phase shift
sp_12
th
P sync preamble 13 phase shift
sp_13
th
P sync preamble 14 phase shift
sp_14
th
P sync preamble 15 phase shift
sp_15
th
P sync preamble 16 phase shift
sp_16
th
P sync preamble 17 phase shift
sp_17
th
P sync preamble 18 phase shift
sp_18
P nominal length of modulated byte field sync preamble
sync_pre_len
4 © ISO 2019 – All rights reserved

Q quadrature signal component
R DC-LIN EPL RX mode
rx_mode
RX DC-LIN EPL RX node error condition
err_cond
t bit time
BIT
t break field data bits ‘0’ length in t
break_field BIT
t line-out monitoring active duration
l_out_mon_l
t line-out monitoring sample time
l_out_mon_samp
t start time of line-out monitoring
l_out_mon_start
t delay between transmitted byte field over to the DC powerline and the receiver
RX_delay
reconstructed byte field from the DC powerline
t delay between transmitted byte field on TXD and the received byte field on RXD at
RX_delay_local
a DC-LIN EPL node (locally)
t maximum process time at RX DC-LIN EPL side
rx_proc_max
t minimum process time at RX DC-LIN EPL side
rx_proc_min
t start time of byte field sync preamble transmission on line-out
SB_TX
T DC-LIN EPL TX mode
tx_mode
t minimum TXD assert (‘0’) time without timeout event (deactivating T )
txd_min_assert tx_mode
t minimum TXD deassert (‘1’) time after timeout event (T remains deactivated)
txd_min_recover tx_mode
logical inverted TXD (i.e. '0' becomes '1' and vice versa)
TXD
typ. typical
UT upper tester
Vpp volt peak-to-peak
V maximum rating for the DC powerline
PWL_max
φ carrier phases
∆fc carrier frequency resolution
i
° degree
4 Electrical physical layer requirements
4.1 General
The DC-LIN EPL is the physical media access sub-layer, which links the data link layer as standardized
in ISO 17987-3 and the DC powerlines (physical medium dependent sub-layer). Figure 1 depicts an
example of a DC-LIN EPL. The EPL consists of a modem, which encodes the data from the data link layer
into the modulated carrier signal that is coupled to the DC powerline. The modem also decodes the
received data on the DC powerline and provides this to the data link layer at the receivers. Follow the
DC-LIN EPL conformance test plan in Annex B.
The DC-LIN EPL transmitter encodes each byte field sent by the data link layer on TXD into a modulated
carrier signal, which is transferred over the DC powerline. The modulation consists of a predefined
combination of phase shifts according to the byte field modulation scheme specified in 4.2.2.
The DC-LIN EPL receiver decodes the received modulated byte from the DC powerline and signals it on
RXD to the data link layer.
Key
1 RXD receive data pin
2 TXD transmit data pin
3 modem
4 line-out
5 line-in
6 coupling capacitor
7 DC powerline
Figure 1 — Example of a DC-LIN EPL
4.2 Transmitter characteristics
4.2.1 Transmit signal specification
The transmit signal shall be constructed as the sum of up to four (redundant) selectable modulated
carrier frequencies.
The definition of the transmit signal is given in Formula (1).
Definition of the formula:
n
Transmit signal=×Afcos 360°× ct× +ϕ()t (1)
[]()
∑ i
i=1
where
6 © ISO 2019 – All rights reserved

A is the gain amplitude of the carrier signal in volts;
t is the time in seconds;
fc is the selected carrier frequency;
i
φ(t) is the carrier frequency phase; φ(t) = 0°, 90°, 180°, 270°;
φ(t) changes as a function of the byte field modulation scheme;
n is the maximal carrier frequency selection per transmit signal;
n = 1, 2, 3, 4.
Table 1 specifies the DC-LIN EPL carrier frequency.
Table 1 — Carrier frequency specification
Parameter Description Min. Max. Unit Accuracy
fc Carrier frequency band 5 30 MHz ±0,02 %
i
∆fc Carrier frequency resolution 0,1 0,1 MHz
i
In essence, fc ∈{5 MHz; 5,1 MHz; 5,2 MHz; . 29,8 MHz; 29,9 MHz; 30 MHz}.
i
4.2.2 Byte field modulation scheme
4.2.2.1 Byte field modulation scheme structure
A byte field modulation scheme shall consist of a byte field sync preamble modulation (specified in
4.2.2.3) and a byte field data bit modulation (specified in 4.2.2.4). A first byte field modulation shall
start with a dedicated reference phase (specified in 4.2.2.2).
A byte field start bit and stop bit shall not be included in a byte field modulation scheme. At receiving
nodes, the DC-LIN EPL shall reconstruct both the start bit and stop bit artificially on RXD (see 4.4).
Figure 2 depicts a byte field modulation scheme structure.
Key
1 TXD DC-LIN node A
2 DC powerline
3 byte field
4 reference phase
5 byte field sync preamble
6 8 modulated data bits
a
Start.
b
Stop.
Figure 2 — Byte field modulation scheme structure
The byte field modulation scheme shall consist of a sequence of ±90° phase shifts while L is
out_err_cond
inactive (see 4.2.2.3 and 4.2.2.4).
While L is active, and only after completion of byte field sync preamble transmission, the
out_err_cond
transmit signal shall consist of no phase shifts (i.e. constant phase transmission) for the remaining field
transmission time (see 4.5.3).
Figure 3 specifies the transmitting phases for 0°, 90°, 180°, and 270° [i.e. φ(t)].
Figure 3 — Transmitter phase’s definition
8 © ISO 2019 – All rights reserved

4.2.2.2 Reference phase
The DC-LIN EPL shall transmit a reference phase (P ) prior to the first phase transmission of a
ref_first
byte field sync preamble modulation.
A first byte field transmission (FB ) shall be interpreted as a start of a byte field transmission by the
TX
data link layer with an inter-byte space longer than 1/3 t .
BIT
A consecutive byte field transmission (CB ) shall be interpreted as a start of a byte field transmission
TX
by the data link layer with an inter-byte space no longer than 1/3 t .
BIT
In the case of a FB , a dedicated reference phase shall be transmitted (P ) as specified in Figure 4.
TX ref_first
In the case of a CB (i.e. not a FB ), the last phase of the previous byte field modulation transmission
TX TX
shall be used as the reference phase (P ) of the next byte field sync preamble modulation (as
ref_consec
specified in Figure 5).
Figure 4 shows an example of byte field sync preamble modulation of a first byte field transmission.
Key
1 TXD DC-LIN node A 7 byte field sync preamble - actual TX phases
2 DC powerline 8 byte field sync preamble - phase shifts
3 TX phases 9 DC-LIN first byte field transmission of node A
4 phase shifts 10 Inter-byte space > 1/3 t
BIT
a
5 actual TX phases Start.
b
6 byte field sync preamble Stop.
Figure 4 — Example of byte field sync preamble modulation of first byte field TX
Figure 5 shows an example of byte field sync preamble modulation of consecutive byte field
transmissions.
P is the last phase of the previous byte field transmission.
ref_consec
Key
1 TXD DC-LIN node A 8 byte field sync preamble – phase shifts
2 DC powerline 9 consecutive byte field transmission
3 example of TX phases 10 Inter-byte space < 1/3 t
BIT
4 phase shifts 11 first byte field transmission
a
5 example of TX phases Start.
b
6 byte field sync preamble Stop.
7 byte field sync preamble – TX phases
Figure 5 — Example of byte field sync preamble modulation of consecutive byte field TX
Table 2 specifies the reference phase length and value.
Table 2 — Reference phase length and value definition
Min. phase Max. phase
Parameter Description Phase Unit
length length
P Reference phase of a first 0° 2/9 1/3 t
ref_first BIT
byte field transmission
(shown in Figure 4)
P Reference phase of a con- Last byte field 1/3 2/3 t
ref_consec BIT
secutive byte field trans- transmitted phase
mission (shown in Figure 5) (0°/90°/180°/270°)
10 © ISO 2019 – All rights reserved

4.2.2.3 Byte field sync preamble modulation
Upon detection of falling edge of a start bit (t ) from the data link layer, a byte field sync preamble
SB_TX
modulation transmission shall start on line-out.
Table 3 specifies the start time of a byte field sync preamble transmission.
Table 3 — Start time of byte field sync preamble transmission definition
Parameter Description Min. Typ. Max. Unit
t Start time of byte field sync preamble — — 2/16 t
SB_TX BIT
transmission on line-out (shown in
Figure 4)
The byte field sync preamble modulation shall consist of 18 phase shifts.
The nominal length of modulated byte field sync preamble (P ) is given in Formula (2).
sync_pre_len
Definition of the formula:
P = 2 t (2)
sync_pre_len BIT
Table 4 specifies the byte field sync preamble phase shifts.
Table 4 — Byte field sync preamble phase shifts definition
Phase
Parameter Description Phase shift
length
st
P Sync preamble 1 phase shift +90° 1/9 t
sp_1 BIT
nd
P Sync preamble 2 phase shift +90°
(shown in
sp_2
rd Figure 4
P Sync preamble 3 phase shift −90°
sp_3
and
th
P Sync preamble 4 phase shift +90°
sp_4
Figure 5)
th
P Sync preamble 5 phase shift −90°
sp_5
th
P Sync preamble 6 phase shift −90°
sp_6
th
P Sync preamble 7 phase shift +90°
sp_7
th
P Sync preamble 8 phase shift +90°
sp_8
th
P Sync preamble 9 phase shift −90°
sp_9
th
P Sync preamble 10 phase shift +90°
sp_10
th
P Sync preamble 11 phase shift −90°
sp_11
th
P Sync preamble 12 phase shift −90°
sp_12
th
P Sync preamble 13 phase shift +90°
sp_13
th
P Sync preamble 14 phase shift +90°
sp_14
th
P Sync preamble 15 phase shift −90°
sp_15
th
P Sync preamble 16 phase shift +90°
sp_16
th
P Sync preamble 17 phase shift −90°
sp_17
th
P Sync preamble 18 phase shift −90°
sp_18
4.2.2.4 Byte field data bit modulation
Upon completion of the byte field sync preamble transmission period (P ), the DC-LIN EPL
sync_pre_len
shall transmit a byte field data bit modulation, bit-by-bit, for each one of the eight data bits transmitted
from the data link layer.
The byte field data bit modulation shall consist of three phase shifts.
The nominal length of a modulated byte field data bit (P ) is given in Formula (3).
data_bit_len
Definition of the formula:
P = 1 t (3)
data_bit_len BIT
Table 5 specifies the phase shift of the byte field data bit modulation.
Table 5 — Byte field data bit phase shift modulation definition
Data bit Phase Condition/
Parameter Description Phase shift
value length comment
st
1 P 1 phase shift +90°
dh_1
nd
P 2 phase shift +90°
dh_2
L is
out_err_cond
rd
P 3 phase shift +90°
dh_3
inactive
1/3 t
BIT
st
0 P 1 phase shift −90°
dl_1
(see 4.5.3)
nd
P 2 phase shift −90°
dl_2
rd
P 3 phase shift −90°
dl_3
Figure 6 shows a bit modulation example of data bit ‘0’.
Key
1 TXD
2 DC powerline
3 byte field
a
Start.
b
Stop.
Figure 6 — Example of bit ‘0’ modulation
Figure 7 shows a bit modulation example of data bit ‘1’.
12 © ISO 2019 – All rights reserved

Key
1 TXD
2 DC powerline
3 byte field
a
Start.
b
Stop.
Figure 7 — Example of data bit ‘1’ modulation
The nominal length of one modulated byte (P ) is given in Formula (4).
byte_length
Definition of the formula:
P = P + 8 × P = 10 t (4)
byte_length sync_pre_len data_bit_len BIT
Figure 8 shows an example of modulation scheme of data byte 01110111 .
Key
1 TXD DC-LIN node A
2 RXD DC-LIN node A
3 DC powerline
4 RXD DC-LIN node B
5 byte field sync preamble
6 DC-LIN byte field reception of node B
7 DC-LIN byte field transmission of node A
a
Start.
b
Stop.
Figure 8 — Example of a byte modulation scheme between a transmitting node A and
receiving node B
4.2.3 Break field modulation scheme
The DC-LIN EPL shall transmit the break field over the DC powerline with the number of bits of the
detected break field on TXD. The break field modulation scheme is the same as the byte field modulation
scheme, but all data bits are ‘0’s.
Figure 9 shows an example of break field modulation transmission.
14 © ISO 2019 – All rights reserved

Key
1 TXD DC-LIN node A
2 RXD DC-LIN node A
3 DC powerline
4 RXD DC-LIN node B
5 byte field sync preamble
6 DC-LIN break field reception of node B
7 DC-LIN break field transmission of node A
a
Start.
b
Break delimiter.
Figure 9 — Example of a break field modulation transmission between a transmitting node A
and receiving node B
4.2.4 Wake-up signal modulation scheme
The wake-up signal modulation is subject to the wake-up signal length on TXD (as specified in
ISO 17987-2:2016, 5.3.1) and shall be transmitted either as a byte field modulation or as a break field
modulation.
When the wake-up signal length on TXD is at least 10 t (i.e. a break field), the wake-up signal
BIT
modulation shall be transmitted as a break field modulation scheme (see 4.2.3).
When the wake-up signal length on TXD is less than 10 t , the wake-up signal modulation shall be
BIT
transmitted as a byte field modulation scheme (see 4.2.2.4) consisting of ‘0’ and ‘1’ data bit modulation
(i.e. the wake-up signal is padded with ‘1’ data bit modulation to a complete byte field modulation
transmission).
Figures 10, 11, and 12 show examples of a wake-up signal modulation transmission by a DC-LIN EPL
that is set to BR_19_2K.
EXAMPLE Figure 10 depicts a wake-up signal with the length of 260 µs. The wake-up signal is encoded by
the DC-LIN EPL to a start bit, four ‘0’ data bits, four ‘1’ data bits and a stop bit (i.e. F0 ).
The wake-up signal modulation is similar to a F0 byte field modulation
16 .
Key
1 TXD wake-up signal DC-LIN node A
2 RXD wake-up signal DC-LIN node A
3 DC powerline
4 ref phase 0°
5 byte field sync preamble
6 DC-LIN wake-up signal transmission of node A
a
Start.
b
Stop.
Figure 10 — Example of a wake-up signal modulation similar to byte field modulation
EXAMPLE Figure 11 depicts a wake-up signal with the length of 294 µs. The wake-up signal is encoded by
the DC-LIN EPL to a start bit, five ‘0’ data bits, three ‘1’ data bits and a stop bit (i.e. E0 ).
The wake-up signal modulation is similar to a E0 byte field modulation.
16 © ISO 2019 – All rights reserved

Key
1 TXD wake-up signal DC-LIN node A
2 RXD wake-up signal DC-LIN node A
3 DC powerline
4 ref phase 0°
5 byte field sync preamble
6 DC-LIN wake-up signal transmission of node A
a
Start.
b
Stop.
Figure 11 — Example of a wake-up signal modulation similar to byte field modulation
EXAMPLE Figure 12 depicts a wake-up signal with the length of 676 µs. The wake-up signal is encoded by
the DC-LIN EPL to a start bit, twelve ‘0’ data bits and a stop bit (i.e. a break field).
The wake-up signal modulation is then similar to a break field modulation
.
Key
1 TXD wake-up signal DC-LIN node A
2 RXD wake-up signal DC-LIN node A
3 DC powerline
4 ref phase 0°
5 byte field sync preamble
6 DC-LIN wake-up signal transmission of node A
a
Start.
b
Stop.
Figure 12 — Example of a wake-up signal modulation similar to break field modulation
4.3 Timing requirements
4.3.1 Bit rate tolerance
The bit rate tolerance describes the allowed deviation of the actual bit rate from the nominal bit rate for
a DC-LIN EPL.
Table 6 specifies the bit rate tolerances for both master node and slave node DC-LIN EPL.
Table 6 — DC-LIN EPL bit rate tolerances
Bit rate Deviation
BR_9_6K <±0,5 %
BR_10K <±0,5 %
BR_19_2K <±0,5 %
The specified DC-LIN EPL bit rate deviation provides sufficient nominal bit rate, which is complying
with EPL sync byte field quantization automatic bit rate detection as specified in ISO 17987-4:2016,
5.2.2, and with EPL bit rate deviation specified in ISO 17987-4:2016, 5.1.
18 © ISO 2019 – All rights reserved

4.3.2 Bit timing
The bit time is defined according to the selected bit rate (given in Table 6).
Calculation of a bit time is given in Formula (5).
Definition of the formula:
t = 1/(BR) (5)
BIT
4.3.3 Bit sample timing
The bit sample timing on TXD shall apply the bit sampling timing specified in ISO 17987-4:2016, 5.2.3.
4.3.4 TXD assert timeout event
The minimum TXD assert (‘0’) time without timeout event is given in Formula (6).
Definition of the formula:
t = 6 ms (6)
txd_min_assert
The minimum TXD deassert (‘1’) time after timeout event (i.e. timeout recovery time) is given in
Formula (7).
Definition of the formula:
t = 10 t (7)
txd_min_recover BIT
Optionally, the DC-LIN EPL may detect a TXD assert timeout event when TXD assert time > t
txd_min_assert.
At the occurrence of TXD assert timeout event, the DC-LIN EPL’s T may be deactivated until the
tx_mode
next falling edge on TXD, which ocuurs after TXD deassert (‘1’) time > t .
txd_min_recover
4.3.5 Delay between transmitted byte field (DC-LIN node A) and received byte field (DC-LIN
node A)
The delay between transmitted byte field on TXD and the received byte field on RXD at a DC-LIN EPL
node (locally) (t ) is given in Formula (8).
RX_delay_local
Definition of the formula:
t = t (8)
RX_delay_local SB_TX
4.3.6 Delay between transmitted byte field (DC-LIN node A) and received byte field (DC-LIN
node B)
The delay between the transmitted byte field, over to the DC powerline, and the receiver reconstructed
byte field (t ) is given in Table 7.
RX_delay
The maximum process time at RX DC-LIN EPL side is given in Formula (9).
Definition of the formula:
t = 6/9 t (9)
rx_proc_max BIT
The minimum process time at RX DC-LIN EPL side is given in Formula (10).
Definition of the formula:
t = 2/9 t (10)
rx_proc_min BIT
(The transmission delay on the DC powerline is negligible as compared to t , and hence not included
BIT
in t calculation).
RX_delay
Table 7 — Delay between TXD (DC-LIN EPL node A) to RXD (DC-LIN EPL node B)
Parameter Min. Typ. Max. Unit Condition / comment
t 22/9 — 25/8 t t = t (2/16) + P (3/9) +
RX_delay BIT RX_delay_max SB_TX ref_first
P (18/9) + t (6/9);
sync_pre_len rx_proc_max
t = P (2/9) + P
RX_delay_min ref_first sync_pre_len
(18/9) + t (2/9)
rx_proc_min
Figure 13 shows an example of a single byte field transmission, demonstrating the t , and
RX_delay_max
t .
RX_delay_local
Key
1 TXD DC-LIN node A
2 RXD DC-LIN node A
3 DC powerline
4 ref phase 0°
5 byte field sync preamble
6 DC-LIN byte field reception of node B
7 DC-LIN byte field transmission of node A
8 RXD DC-LIN node B
a
Start.
b
Stop.
Figure 13 — Delay between TXD and RXD over the powerline between a transmitting node A
and receiving node B
20 © ISO 2019 – All rights reserved

4.4 Receiver characteristics
At the receiver node side, the DC-LIN EPL (e.g. node B) shall decode a received byte/break field
modulation from DC-LIN EPL (e.g. node A) into bits transferred on RXD to the data link layer (see
Figures 8 and 9).
DC-LIN EPL RX node (e.g. node B) error condition (RX ) is defined active when decoding of the
err_cond
received modulation from DC-LIN EPL (e.g. node A) results in detection of no phase shifts for the
duration of at least 1 t . RX shall remain active for the remaining duration until completion of
BIT err_cond
transmission B to the data link layer (see Table 8 and Figure 18).
fe_stop_bit
Table 8 specifies RXD behaviour at receiver DC-LIN EPL node side.
If not otherwise stated, RXD logic level shall be set to ‘1’.
Table 8 — RXD behaviour at DC-LIN EPL receiver node side
Nominal bit
Parameter RXD Logic level Start time Condition/comment
length
B Low (‘0’) t 1 t R is active
start_bit RX_delay BIT rx_mode
B Low (‘0’) when decoding bit t 1 t 1 t R is active
data_bit RX_delay + BIT BIT rx_mode
modulation of data bit ‘0’
The start time is defined for
or the first data bit (least signif-
icant bit), the rest of data bits
High (‘1’) when decoding bit
are transmitted sequentially.
modulation of data bit ‘1’ or
when RX is active
err_cond
B High (‘1’) t 9 t 1 t R is active
stop_bit RX_delay + BIT BIT rx_mode
RX is inactive
err_cond
Byte field receiving
B Low (‘0’) t 9 t 1 t R is active
fe_stop_bit RX_delay + BIT BIT rx_mode
RX is active
err_cond
Byte field receiving
B High (‘1’) t +1 t 1 t R is active
del RX_delay BIT + BIT rx_mode
t
break_field
RX is inactive
err_cond
Break field receiving
4.5 Electrical parameters
4.5.1 General configuration — Coupling to the DC powerline
The coupling to the DC powerline may include a coupling capacitor and a protection network.
Figure 14 shows an example of a protection network using diodes.
Key
1 RXD receive data pin
2 TXD transmit data pin
3 GND
4 line-out
5 line-in
6 coupling capacitor
7 DC powerline
8 protection network
Figure 14 — Example of powerline coupling circuit with protection network
4.5.2 Signal specification
Table 9 specifies the electrical parameters of the DC-LIN EPL signal on the line-out and line-in.
Table 9 — Electrical parameters of the DC-LIN EPL
Symbol Description Min. Typ. Max. Unit Condition/comment
Line-in Input voltage level at line-in pin 0,005 — 1,44 V Volt peak-to-peak
Measurement-point is be-
tween line-in and the cou-
pling capacitor with 50-Ω
load (shown in Figure 15).
Line-in input impedance 5 — — kΩ
Line-out Output voltage level at line-out pin 0,96 1,2 1,44 V Volt peak-to-peak
Measurement-point is be-
tween line-in and the cou-
pling capacitor with 50-Ω
load (shown in Figure 16).
T is active
tx_mode
Output voltage level at line-out pin 0 — 0,1 V Volt peak-to-peak
Measurement-point is be-
tween line-in and the cou-
pling capacitor with 50-Ω
load (shown in Figure 16).
T is inactive or
tx_mode
low-power mode is active
Line-out input impedance 100 — — kΩ T is inactive or
tx_mode
low-power mode is active
22 © ISO 2019 – All rights reserved

Figure 15 illustrates DC-LIN EPL line-in measure point test set-up.
Key
1 RXD receive data pin 7 RX signal level measure point
2 TXD transmit data pin 8 DC powerline
3 GND 9 power supply
4 line-out 10 unit under test
5 line-in 11 test set-up
a
6 coupling capacitor Load.
Figure 15 — DC-LIN EPL line-in measurement-point: test set-up
Figure 16 illustrates DC-LIN EPL line-out measure point test set-up.
Key
1 RXD receive data pin 7 TX signal level measure point
2 TXD transmit data pin 8 DC powerline
3 GND 9 power supply
4 line-out 10 unit under test
5 line-in 11 test set-up
a
6 coupling capacitor Load.
Figure 16 — DC-LIN EPL line-out measurement-point: test set-up
4.5.3 Line-out monitoring
The DC-LIN EPL shall monitor its transmitted output level at line-out. The DC-LIN EPL line-out
monitoring function shall provide an error indication on RXD to the data link layer in case the sampled
line-out peak level is below L .
out_thr_lev
Table 10 specifies the line-out monitoring peak threshold level (L ).
out_thr_lev
Table 10 — Line-out monitoring peak threshold level
Parameter Description Min. Typ. Max. Unit
L Line-out monitoring peak 25 — 50 mV
out_thr_lev
threshold level
Start time of line-out monitoring (t is given in Formula (11).
l_out_mon_start)
Definition of the formula:
t = t (11)
l_out_mon_start SB_TX
t is given in Table 3.
SB_TX
Li
...