ETSI TR 102 300-7 V1.2.1 (2016-11)

ETSI TR 102 300-7 V1.2.1 (2016-11)






TECHNICAL REPORT
Terrestrial Trunked Radio (TETRA);
Voice plus Data (V+D): Designers' guide;
Part 7: TETRA High-Speed Data (HSD);
TETRA Enhanced Data Service (TEDS)

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2 ETSI TR 102 300-7 V1.2.1 (2016-11)



Reference
RTR/TCCE-04185
Keywords
data, service, TETRA

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3 ETSI TR 102 300-7 V1.2.1 (2016-11)
Contents
Intellectual Property Rights . 9
Foreword . 9
Modal verbs terminology . 9
1 Scope . 10
2 References . 10
2.1 Normative references . 10
2.2 Informative references . 10
3 Definitions and abbreviations . 12
3.1 Definitions . 12
3.2 Abbreviations . 18
4 TETRA layered architecture . 22
4.1 OSI reference model . 22
4.2 TETRA protocol stack . 23
4.2.1 Protocol architecture . 23
4.2.2 Inter-layer communication . 25
4.2.3 Testable boundaries . 25
4.2.4 Service access points . 25
5 Overview of TETRA High-Speed Data (HSD) . . 25
5.1 Introduction . 25
5.2 Physical layer and lower MAC layer enhancements . 27
5.3 Higher protocol layer enhancements . 28
5.4 Services and applications . 28
6 Physical layer and lower MAC . 29
6.1 Physical resources . 29
6.2 TDMA frame structure . 30
6.3 Slot structure . 31
6.3.1 Slot structure for phase modulation . 31
6.3.2 Slot structure for QAM . 32
6.4 Radio transmission burst structure . 33
6.4.1 Burst structure for phase modulation . 33
6.4.2 Burst structure for QAM . 35
6.4.3 Burst structure formats . 36
6.4.3.1 Phase modulated burst formats . 36
6.4.3.2 QAM modulated burst formats . 37
6.5 Channel structure . 38
6.5.0 General . 38
6.5.1 Logical channels in phase modulation . 38
6.5.1.0 Logical channel categories . 38
6.5.1.1 Control CHannel (CCH) . 39
6.5.1.2 Traffic CHannel (TCH) . 39
6.5.2 QAM channels . 40
6.5.3 Mapping of logical channels into physical channels . 41
6.5.3.1 Mapping in phase modulation . 41
6.5.3.2 Mapping in QAM . 41
6.6 Reference configuration . 42
6.6.1 Reference configuration for phase modulation . 42
6.6.2 Reference configuration for QAM . 43
6.7 Modulation . 43
6.7.1 Phase modulation . 43
6.7.2 QAM . 45
6.7.2.1 Modulation types . 45
6.7.2.2 Bit to symbol mapping . 45
6.7.2.3 Comparison of gross bit rates . 49
ETSI

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4 ETSI TR 102 300-7 V1.2.1 (2016-11)
6.8 Error control (lower MAC) . 49
6.8.1 General . 49
6.8.2 Error control schemes for phase modulation . 51
6.8.3 Error control schemes for QAM channels . 52
6.8.3.0 General . 52
6.8.3.1 Slot Information CHannel - QAM/Uplink (SICH-Q/U). 53
6.8.3.2 Slot Information CHannel - QAM/Downlink (SICH-Q/D) . 53
6.8.3.3 Access Assignment CHannel - QAM (AACH-Q). 54
6.8.3.4 Signalling Channel - QAM/Half slot Uplink (SCH-Q/HU) . 54
6.8.3.5 Signalling CHannel - QAM/Uplink (SCH-Q/U) . 55
6.8.3.6 Signalling CHannel - QAM/Downlink (SCH-Q/D) and Broadcast Network CHannel - QAM
(BNCH-Q) . 55
6.8.3.7 Signalling CHannel - QAM/Random Access (SCH-Q/RA) . 55
6.8.3.8 Broadcast Synchronization CHannel - QAM (BSCH-Q) . 56
6.8.3.9 Signalling CHannel data set B - QAM (SCH-Q/B) . 56
6.8.4 Coding for phase modulation . 56
6.8.4.1 General . 56
6.8.4.2 16-state Rate-Compatible Punctured Convolutional (RCPC) codes . 56
6.8.4.3 Shortened (30,14) Reed-Muller block codes . 58
6.8.4.4 Cyclic Redundancy Check (CRC) block code . 58
6.8.5 Coding for QAM channels . 59
6.8.5.0 General . 59
6.8.5.1 8-state Parallel Concatenated Convolutional Code (PCCC) for QAM . 60
6.8.5.1.0 PCCC encoding . 60
6.8.5.1.1 Encoding by the upper 8-state RSC encoder of rate 1/2 . 60
6.8.5.1.2 Interleaving by the quadratic-congruence interleaver . 61
6.8.5.1.3 Encoding the interleaved bits by the lower 8 state RSC encoder of rate 1/2 . 62
6.8.5.1.4 Merging the systematic and parity bits for the PCCC encoder . 62
6.8.5.1.5 Puncturing scheme for the PCCC encoder . 62
6.8.5.1.6 Puncturing mask for the PCCC encoder with coding rate 2/3 . 63
6.8.5.1.7 Puncturing mask for the PCCC encoder with coding rate 1/2 . 63
6.8.5.2 (16,5) Reed-Muller (RM) code for QAM . 63
6.8.6 Interleaving for phase modulation . 63
6.8.7 Interleaving for QAM channels . 64
6.8.8 Scrambling . 65
6.8.8.1 General . 65
6.8.8.2 Scrambling method . 65
6.9 Synchronization and channel estimation . 66
6.9.1 Frequency and time synchronization . 66
6.9.1.1 Requirements . 66
6.9.1.1.1 BS requirements . 66
6.9.1.1.2 MS requirements . 66
6.9.1.2 Synchronization on a CA cell. 66
6.9.1.2.1 Initial synchronization via π/4-DQPSK plus π/8-D8PSK - CA . 66
6.9.1.2.2 Fine synchronization in QAM channels - CA . 67
6.9.1.3 Synchronization on a DA cell . 69
6.9.2 Channel estimation in QAM channels . 70
6.10 Power control . 71
6.11 Link adaptation in TETRA high speed channels . 71
7 Higher layer protocol. 72
7.1 Protocol architecture. 72
7.1.1 General packet data aspects . 72
7.1.2 Architecture of the TETRA protocol stack . 72
7.2 Multimedia Exchange layer . 74
7.2.1 General MEX features . 74
7.2.2 MEX routing services . 74
7.2.3 MEX precedence . 74
7.3 Subnetwork Dependent Convergence Protocol layer . 75
7.3.1 Outline of SNDCP . 75
7.3.2 Application-level QoS parameters . 78
7.3.3 QoS negotiation . 80
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5 ETSI TR 102 300-7 V1.2.1 (2016-11)
7.3.4 QoS filtering information for secondary PDP contexts . 80
7.3.5 Assignment of PDP contexts to layer 2 communication links . 81
7.3.6 Choice of layer 2 communication link parameters . 81
7.3.7 Selection of channel . 82
7.3.7.1 Initial PDCH access . 82
7.3.7.2 Changing PDCH requirements . 82
7.3.8 Header and data compression . 83
7.3.9 Data priority in SNDCP . 83
7.3.10 Reconnection following cell reselection . 83
7.4 Operation of the data link layer (layer 2) protocol . 84
7.4.1 Structure of the data link layer . 84
7.4.2 Control channel usage . 85
7.4.2.1 Common control channels and assigned channels . 85
7.4.2.1.1 General . 85
7.4.2.1.2 Common control channels . 85
7.4.2.1.3 Assigned channels . 86
7.4.2.1.4 Sharing channels between cells . 88
7.4.2.2 π/4-DQPSK channel . 88
7.4.2.3 D8PSK channel . 88
7.4.2.4 QAM channel . 89
7.4.2.5 Slot and TDMA frame arrangement on uplink and downlink . 89
7.4.2.6 Minimum mode for CA . 90
7.4.2.7 Discontinuous downlink transmissions - time-sharing mode . 90
7.4.2.8 Independent allocation of uplink and downlink . 91
7.4.3 Communication links provided by the LLC . 91
7.4.3.1 General . 91
7.4.3.2 Basic link . 92
7.4.3.3 Advanced link . 93
7.4.3.4 Advanced link usage . 94
7.4.3.4.1 Advanced link set-up . 94
7.4.3.4.2 Segment size for advanced link . 95
7.4.3.5 Layer 2 signalling . 96
7.4.4 Some MAC processes . 97
7.4.4.1 General . 97
7.4.4.2 Addressing . 98
7.4.4.2.1 General . 98
7.4.4.2.2 Layer 2 addressing . 99
7.4.4.3 Random access . 99
7.4.4.3.1 General . 99
7.4.4.3.2 Overview of random access channel on 25 kHz channel . 101
7.4.4.3.3 Overview of random access channel on 50 kHz, 100 kHz or 150 kHz QAM channel . 103
7.4.4.4 Reserved access . 104
7.4.4.4.1 Use of reserved access . 104
7.4.4.4.2 Basic slot granting . 104
7.4.4.4.3 Multiple slot granting . 104
7.4.4.5 Channel allocation . 105
7.4.4.6 Power control . 106
7.4.4.6.1 General . 106
7.4.4.6.2 Open loop power control . 106
7.4.4.6.3 Closed loop power control . 107
7.5 Link adaptation on D8PSK or QAM channel . 107
7.5.1 General . 107
7.5.2 Algorithm using predefined choice of bit rates . 108
7.5.3 Algorithm adapting with channel conditions . 109
7.6 Energy economy and napping . 111
7.6.0 Methods for reduced reception . 111
7.6.1 Energy economy, dual watch and part-time reception on common control channel . 111
7.6.1.1 Energy economy mode . 111
7.6.1.2 Dual watch mode . 112
7.6.1.3 Part-time reception on multi-slot MCCH-Q . 113
7.6.2 Napping on assigned channel. 113
7.7 Data priority . 114
ETSI

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6 ETSI TR 102 300-7 V1.2.1 (2016-11)
7.8 Scheduled access .
...