ETSI ETS 300 011-2 ed.2 (1998-03)

SLOVENSKI STANDARD
01-december-2003
Digitalno omrežje z integriranimi storitvami (ISDN) – Primarni vmesnik uporabnik-
omrežje (UNI) – 2. del: Specifikacija za preskušanje skladnosti za vmesnika IA in IB
Integrated Services Digital Network (ISDN); Primary rate User-Network Interface (UNI);
Part 2: Conformance test specification for interface IA and IB
Ta slovenski standard je istoveten z: ETS 300 011-2 Edition 2
ICS:
33.080 Digitalno omrežje z Integrated Services Digital
integriranimi storitvami Network (ISDN)
(ISDN)
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

EUROPEAN ETS 300 011-2
TELECOMMUNICATION March 1998
STANDARD Second Edition
Source: TM Reference: RE/TM-03037-2
ICS: 33.020
Key words: ISDN, layer 1, primary, rate, UNI, transmission, testing
Integrated Services Digital Network (ISDN);
Primary rate User-Network Interface (UNI);
Part 2: Conformance test specification for interface I and I
A B
ETSI
European Telecommunications Standards Institute
ETSI Secretariat
Postal address: F-06921 Sophia Antipolis CEDEX - FRANCE
Office address: 650 Route des Lucioles - Sophia Antipolis - Valbonne - FRANCE
Internet: secretariat@etsi.fr - http://www.etsi.fr - http://www.etsi.org
Tel.: +33 4 92 94 42 00 - Fax: +33 4 93 65 47 16
Copyright Notification: No part may be reproduced except as authorized by written permission. The copyright and the
foregoing restriction extend to reproduction in all media.
© European Telecommunications Standards Institute 1998. All rights reserved.

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ETS 300 011-2: March 1998
Whilst every care has been taken in the preparation and publication of this document, errors in content,
typographical or otherwise, may occur. If you have comments concerning its accuracy, please write to
"ETSI Editing and Committee Support Dept." at the address shown on the title page.

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ETS 300 011-2: March 1998
Contents
Foreword .5
1 Scope .7
2 Normative references.7
3 Definitions, symbols and abbreviations.7
3.1 Definitions .7
3.2 Symbols .9
3.3 Abbreviations .9
4 Conformance tests.9
4.1 General information .9
4.2 Additional information to support the test .9
4.3 Connection of the simulator to the IUT .10
5 Conformance tests specification .10
5.1 Functional characteristics tests.10
5.1.1 Frame structure.10
5.1.1.1 Number of bits per timeslot.10
5.1.1.2 Number of timeslots per frame.10
5.1.1.3 Generation of frame alignment word .11
5.1.1.4 S bits.11
a
5.1.2 Timeslot assignment .11
5.1.3 Test of signals sent by IUT.12
5.1.3.1 HDB3 coding and normal operational frame .12
5.1.3.2 Remote alarm indication.12
5.1.3.3 Alarm indication signal.12
5.1.3.4 CRC error information .13
5.1.3.5 Remote alarm indication and continuous CRC error
indication.13
5.1.4 Received and transmitted line code .13
5.1.4.1 Received line code .13
5.1.4.2 Transmitted line code .13
5.1.5 Timing considerations .13
5.1.5.1 AIS recognition .13
5.1.5.2 Synchronization .14
5.2 Interface procedures tests .15
5.2.1 States-matrix at the IUT network side.16
5.2.2 States-matrix at the IUT user side.17
5.2.3 Interframe (layer 2) time fill.18
5.2.4 Frame alignment (without the test of CRC procedure).18
5.2.5 CRC multiframe alignment.20
5.2.6 CRC processing .21
5.3 Electrical characteristics tests.23
5.3.1 Specifications at the output ports .23
5.3.1.1 Bit rate when unsynchronized.23
5.3.1.2 Pulse shape and amplitude of a mark (pulse) .24
5.3.1.3 Peak voltage of a space (no pulse) .25
5.3.1.4 Ratio of the amplitudes of positive and negative pulses at
the centre of the pulse interval.26
5.3.1.5 Ratio of the widths of positive and negative pulses at the
nominal half amplitude.27
5.3.1.6 Return loss at the output port .28
5.3.1.7 Impedance towards ground of the transmitter.29
5.3.2 Specifications at the input ports .30

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ETS 300 011-2: March 1998
5.3.2.1 Receiver sensitivity and input port immunity against
reflections. 30
5.3.2.2 Return loss at the input port. 31
5.3.2.3 Tolerable longitudinal voltage . 32
5.3.2.4 Impedance towards ground of the receiver. 33
5.4 Jitter. 34
5.4.1 Minimum tolerance to jitter and wander at inputs . 34
5.4.2 Output jitter . 35
5.4.2.1 Output jitter with jitter at the input supplying timing. 35
5.4.2.2 Output jitter at network side . 37
5.5 Power feeding . 38
5.5.1 Provision of power and feeding voltage. 38
5.5.2 Protection against short circuit. 39
5.5.3 Protection against overload . 39
5.5.4 Power consumption and interchange of wires. 40
History. 41

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ETS 300 011-2: March 1998
Foreword
This second edition European Telecommunication Standard (ETS) was produced by the Transmission
and Multiplexing (TM) Technical Committee of the European Telecommunications Standards Institute
(ETSI).
This ETS aims to meet urgent requirements of network operators and equipment manufacturers who are
designing equipment to operate with an Integrated Services Digital Network (ISDN) primary rate access
User Network Interface (UNI).
This ETS is based upon CCITT Recommendation I.431 and provides modifications and further
requirements to that document. It also is affected by CCITT Recommendations G.703, G.704 and G.706,
and modifications to these CCITT Recommendations are provided within this ETS.
This ETS also takes into account requirements contained in ECMA Standard 104: "Physical layer at the
primary rate access interface between data processing equipment and private switching networks (1985)",
which are given in annex A.
This ETS consists of 3 parts as follows:
Part 1: "Layer 1 specification";
Part 2: "Conformance test specification for interface I and I ";
A B
Part 3: "Implementation Conformance Statement (ICS) and Implementation eXtra Information for Testing
(IXIT) proforma specification for lnterface I and I ".
A B
Transposition dates
Date of adoption of this ETS: 6 March 1998
Date of latest announcement of this ETS (doa): 30 June 1998
Date of latest publication of new National Standard
or endorsement of this ETS (dop/e): 31 December 1998
Date of withdrawal of any conflicting National Standard (dow): 31 December 1998

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ETS 300 011-2: March 1998
1 Scope
This second edition European Telecommunication Standard (ETS) provides the test principles used to
determine the compliance of an Implementation Under Test (IUT) for the requirements specified in
ETS 300 011-1 [3].
It is outside the scope of this ETS to identify the specific tests required by an implementation where
equipment has to meet attachment approval.
This ETS is applicable to interfaces I and I as appropriate. The field of applicability is reported at the
A B
beginning of each test.
2 Normative references
This ETS incorporates, by dated or undated reference, provisions from other publications. These
normative references are cited at the appropriate places in the text and the publications are listed
hereafter. For dated references subsequent amendments to, or revisions of, any of these publications
apply to this ETS only when incorporated in it by amendments or revision. For undated references the
latest edition of the publication referred to applies.
[1] CCITT Recommendation O.151 (1992): "Error performance measuring
equipment operating at the primary rate and above".
[2] ETR 001: "Integrated Services Digital Network (ISDN); Customer access
maintenance".
[3] ETS 300 011-1: "Integrated Services Digital Network (ISDN); Primary rate User
Network Interface (UNI); Part 1: Layer 1 specification".
[4] ETS 300 233 (1994): "Integrated Services Digital Network (ISDN); Access digital
section for ISDN primary rate".
[5] CCITT Recommendation X.200 (1994): "Information technology - Open
Systems Interconnection - Basic reference model: The basic model".
[6] CCITT Recommendation O.162 (1992): "Equipment to perform in-service
monitoring on 2 048, 8 448, 34 368 and 139 264 kbit/s signals".
3 Definitions, symbols and abbreviations
3.1 Definitions
For the purposes of this ETS, the following definitions apply:
Alternate Mark Inversion (AMI): Is a code where ONEs are represented by alternate positive and
negative pulses, and ZEROs by spaces.
High-Density Bipolar 3 (HDB3): Is a modified AMI code. An exception occurs for blocks of 4 successive
ZEROs. Each block of 4 successive ZEROs is replaced by OOOV or BOOV where B represents an
inserted pulse conforming to the AMI and V represents an AMI violation. The choice of OOOV or BOOV is
made so that the number of B pulses between consecutive V pulses is odd. In other words, successive V
pulses are of alternate polarity so that no dc component is introduced.
Interface I : User side of the ISDN user-network interface for the primary rate access.
A
Interface I : Network side of the ISDN user-network interface for the primary rate access.
B
Network side: NT1, LT and ET functional groups in case of an interface at the T reference point; or
relevant parts of the NT2 functional group in case of an interface at the S reference point.

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ETS 300 011-2: March 1998
Network option 1: The digital link between interface at the T and V reference point does not provide a
CRC-4 processing, i.e. the CRC-4 is terminated in the TE and the ET. This digital link is called to be
"without CRC processing" (see subclause 7.2.2.2 of ETS 300 011-1 [3]).
NOTE 1: This option is not provided by the public ISDN at the T reference point. However it
might be used for PTNX interconnection using unstructured 2 048 kbit/s leased lines.
Network option 2: The digital link between interface at the T and V reference point provides CRC-4
processing in the NT1 and the ET according ETR 001 [2]. Therefore the combinations of CRC-4 error
information and RAI indicate the fault condition; FC1 or FC4 (see subclause 7.2.2.1 of ETS 300 011-1 [3]).
NOTE 2: Option 3 of CCITT Recommendation I.604 with CRC-4 processing in NT1, LT and ET
is not relevant for this ETS.
Network Termination (NT): An equipment providing interface I .
B
NOTE 3: This term is used in this ETS to indicate network-terminating aspects of NT1 and NT2
functional groups where these have an I interface.
B
Network Termination type 1 (NT1): This functional group includes functions broadly equivalent to layer 1
(physical) of the OSI reference model. These functions are associated with the proper physical and
electromagnetic termination of the network. NT1 functions are:
- line transmission termination;
- layer 1 maintenance functions and performance monitoring;
- timing;
- layer 1 multiplexing;
- interface termination.
Network Termination type 2 (NT2): this functional group includes functions broadly equivalent to layer 1
and higher layers of the CCITT Recommendation X.200 [5] reference model. Private Telecommunication
Network Exchange (PTNXs), local area networks and terminal controllers are examples of equipment or
combinations of equipment that provide NT2 functions. NT2 functions include:
- layer 2 and layer 3 protocol handling;
- layer 2 and layer 3 multiplexing;
- switching;
- concentration;
- maintenance functions;
- interface termination and other layer 1 functions.
Private Telecommunication Network eXchange (PTNX): A nodal identity in a private
telecommunication network which provides autonomous and automatic switching and call handling
functions used for the provision of telecommunication services which are based on the definitions for
those of the public ISDN.
Private Network Termination (PNT): A remote unit of equipment which terminates a transmission
system employed between the PTNX and the interface I and the S reference point.
B
Simulator: (terminal or network) device generating a stimulus signal conforming to this ETS to bring the
IUT into the required operational state and monitoring the receive signal from the IUT. It can either be a
simulator for the user side or the network side of the interface.
Terminal Adapter (TA): An equipment with interface I and one or more auxiliary interfaces that allow
A
non-ISDN terminals to be served by an ISDN user-network interface.
Terminal Equipment (TE): An equipment providing an interface I .
A
NOTE 4: This term is used in this ETS to indicate terminal-terminating layer 1 aspects of TE1,
TA and NT2 functional groups, where these have an I interface.
A
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ETS 300 011-2: March 1998
NOTE 5: In annex A of ETS 300 011-1 [3], this definition applies with the exception that the NT2
functional grouping is not covered.
Terminal Equipment type 1 (TE1): This functional group includes functions belonging to the functional
group TE, and with an interface that complies with the ISDN user-network interface standard.
User side: Terminal terminating layer 1 aspects of TE1, TA and NT2 functional groups.
3.2 Symbols
For the purposes of this ETS, the following symbols apply:
ONE binary "1"
ZERO binary "0"
3.3 Abbreviations
For the purposes of this ETS, the following abbreviations apply:
AIS Alarm Indication Signal
CRC Cyclic Redundancy Check
dc direct current
ET Exchange Termination
HDB3 High-Density Bi-polar 3 (line code)
HDLC High level Data Link Control
ICS Implementation Conformance Statement
IUT Implementation Under Test
NOF Normal Operational Frames
NT Network Termination
PRBS Pseudo-Random Binary Sequence
PTN Private Telecommunications Network
PTNX Private Telecommunications Network Exchange
RAI Remote Alarm Indication
Rx Interface signal receiver of IUT or simulator
SMF Sub-MultiFrame
TA Terminal Adapter
TE Terminal Equipment
Tx Interface signal transmitter of IUT or simulator
4 Conformance tests
4.1 General information
Detailed test equipment accuracy and the specification tolerance of the test devices is not a subject of this
ETS. Where such details are provided then those test details are considered as being an "informative"
addition to the test description.
The test configurations given do not imply a specific realization of test equipment, nor arrangement, nor
the use of specific test devices for conformance testing. However, any test configuration used shall
provide those test conditions specified under "system state", "stimulus" and "monitor" for each individual
test.
In the case of a multi-access implementation under test supporting interface I , unless otherwise stated,
A
only one access at a time shall receive the stimulus. All other accesses shall receive "no signal"
(state F3).
4.2 Additional information to support the test
It is assumed that, at least one of the following facilities is provided by IUT:
1) a transparent loopback of at least one timeslot towards the interface;

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ETS 300 011-2: March 1998
2) the ability to transmit a 2 -1 Pseudo-Random Binary Sequence (PRBS) in a timeslot.
When the IUT does not provide these facilities the equipment supplier may provide:
a) a test equipment using the same chip set and interface components as in the IUT and able to
provide a transparent loopback of at least one timeslot towards the interface; or
b) a test equipment using the same chip set and interface components as in the IUT and able to
provide a 2 -1 PRBS in a timeslot.
4.3 Connection of the simulator to the IUT
For testing the electrical characteristics of the IUT, the simulator, or its relevant part, shall be connected
directly to the interconnecting points for the interface wiring at the IUT unless otherwise stated. For the
tests given in subclauses 5.3 (except 5.3.1.1) and 5.5, a cord connected at an IUT shall be removed since
a cord is regarded as integral part of the interface wiring.
All other tests may be performed with interface wiring complying with the requirements given in
ETS 300 011-1 [3], subclause 4.3.
5 Conformance tests specification
5.1 Functional characteristics tests
These tests are designed to test conformance to the functional characteristics of the layer 1 of primary
rate interface.
5.1.1 Frame structure
These tests check the frame composition.
5.1.1.1 Number of bits per timeslot
This requirement cannot be verified via layer 1 procedures.
Test to be performed at higher protocol layers.
5.1.1.2 Number of timeslots per frame
This requirement cannot be verified via layer 1 procedures.
Test to be performed at higher protocol layers.

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5.1.1.3 Generation of frame alignment word
Test applicable for I and I interfaces.
A B
Purpose: To check the correct generation of frame alignment word, multiframe alignment
word, CRC bits C to C .
1 4
Test configuration:
RX TX
IUT Simulator
RX
TX
Figure 1: Test of frame alignment word
System state for I : Any state F1 to F5.
A
System state for I : State G1, G2, G3, G5.
B
Stimulus: Relevant signals defined to force IUT to enter the appropriate state.
Monitor: Correct frame alignment word pattern.
Results: No detection of incorrect frame alignment word, multiframe alignment word, and
no received sub-multiframes in error within 1 second measured in any state. For
IUT with CRC-DISABLE function activated (as defined in subclause A.2.3 of
ETS 300 011-1 [3]) bit 1 of timeslot 0 shall always be ONE.
During this test the E bit is not considered.
5.1.1.4 S bits
a
Test applicable for I and I interfaces.
A B
Purpose: To check the S bits contained in timeslot 0 of the frame not containing the
a
frame alignment signal:
- bits 4 and 8 are reserved for international use are not defined;
- bits 5, 6 and 7 are specified in ETS 300 233 [4] for use in the access
digital section.
Since no specific functions are defined for the S bits, no specific test is prescribed for the generation of
a
these S bits. The immunity of the receiving side to the S bits is implicitly tested with the test described in
a a
subclauses 5.2.1 and 5.2.2.
5.1.2 Timeslot assignment
This requirement cannot be verified via layer 1 procedures.
Test to be performed at higher protocol layers.

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5.1.3 Test of signals sent by IUT
These tests check the different signals sent by the IUT.
5.1.3.1 HDB3 coding and normal operational frame
Test applicable for I and I interfaces.
A B
Purpose: To check the coding, decoding, and the binary organization of Normal
Operational Frame (NOF).
Test configuration:
RX TX
IUT Simulator
TX RX
Figure 2: Test of HDB3 coding and NOF
System state for I : State F1. Application of one of the facilities defined in subclause 4.2 is required.
A
The IUT shall be tested with loopback 4 activated according to annex B of
ETS 300 011-1 [3].
System state for I : State G1.
B
Stimulus: NOF sent continuously from the Simulator with valid timeslot 0 including active
CRC and without CRC error. Pseudo-random pattern 2 -1 shall fill continuously
all the frame except timeslot 0 (net bit rate 1 984 kbit/s).
Monitor: The correct coding and the frame structure of the signal sent from the IUT.
Results: The signal received shall be encoded according to the HDB3 coding rule of
ETS 300 011-1 [3]. The frame shall comprise valid timeslot 0 with A bit set to 0,
E bit set to 1 and including correct CRC without CRC blocks in error. For IUT
with CRC-DISABLE function activated (as defined in subclause A.2.3 of
ETS 300 011-1 [3]) bit 1 of timeslot 0 shall always be ONE.
5.1.3.2 Remote alarm indication
Test applicable for I and I interfaces.
A B
This test is combined with test described in subclauses 5.2.1 and 5.2.2.
5.1.3.3 Alarm indication signal
Test applicable for I interface.
B
Purpose: To check the correct generation of Alarm Indication Signal (AIS).
This test is combined with test described in subclauses 5.2.1 and 5.2.2.

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5.1.3.4 CRC error information
Test applicable for I and I interfaces.
A B
Purpose: To check the detection of CRC blocks in error and the correct report with E bit.
This test is combined with test described in 5.2.6.
5.1.3.5 Remote alarm indication and continuous CRC error indication
Test applicable for I interface.
B
Purpose: To check the correct generation of remote Alarm Indication and continuous CRC
error information (RAI and E bit set to ZERO).
This test is combined with test described subclauses 5.2.1 and 5.2.2.
5.1.4 Received and transmitted line code
5.1.4.1 Received line code
Test applicable for I and I interfaces.
A B
Purpose: To test the line coding of the received frames.
This test is included in test 5.2.6 (CRC4 processing).
5.1.4.2 Transmitted line code
Test applicable for I and I interfaces.
A B
Purpose: To test the line coding of the transmitted frames.
This test is included in test 5.1.3.1 Normal Operational Frame (NOF).
5.1.5 Timing considerations
5.1.5.1 AIS recognition
Test applicable for I interface.
A
Purpose: To check the ability of IUT to recognize AIS.
Test configuration:
RX TX
IUT Simulator
TX RX
Figure 3: Test of AIS recognition

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ETS 300 011-2: March 1998
System state: State F4.
Stimulus: AIS signal with clock frequency 2 048 kbit/s ± 50 ppm.
It is not possible to distinguish between states F3 and F4 using only layer 1 information at the interface.
IUT suppliers shall provide information how IUT presents status indication (i.e. detected defect conditions
corresponding to MPH error indication or recovery from defect condition).
Monitor: The frames transmitted by IUT.
Results: IUT shall remain in state F4, therefore no change of error indication shall occur.
IUT having more than one access shall not synchronize its internal reference clock to the incoming signal
frequency.
5.1.5.2 Synchronization
Test applicable for I interface.
A
Purpose: The ability of IUT to synchronize its timing on the signal received from the
network.
Test configuration:
TX
RX
Simulator
IUT
TX RX
Figure 4: Test of synchronization
System state: State F1.
Stimulus: Normal operational frames with clock frequency variation from the nominal
value.
For IUT to be connected to T reference point the corresponding bit rate shall be
in the range 2 048 kbit/s ± 1 ppm.
For IUT to be connected to S reference point the corresponding bit rate shall be
in the range 2 048 kbit/s ± 32 ppm.
For interface at IUT for PTNX interconnection the corresponding bit rate shall be
in the range 2 048 kbit/s ± 32 ppm.
For implementation with free running clock frequency accuracy better than ± 1 ppm, as declared by the
equipment supplier the stimulus shall be in the range ± 1 ppm.
In case of multi-access IUT, this test has to be performed on each access declared to be capable to
extract synchronization from the network, while all other accesses are in state F3 or F4.
The stimulating signal is provided to a timing synchronizing input of IUT. The frequency of the output
signal at each access has to follow the input signal frequency.

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ETS 300 011-2: March 1998
Monitor: The frames transmitted by IUT.
Results: 1) The IUT shall remain in state F1.
2) The frequency of the outgoing signal at each access has to follow the
frequency of the stimulating input signal.
NOTE: The speed of the variation of the output frequency depends on the Q factor of the
reference clock recovery timing of the IUT.
5.2 Interface procedures tests
Definition of test sequences:
FAS: Frame with correct FAS (Frame Alignment Signal), correct bits C to C and
1 4
correct MFAS (CRC Multi Frame Alignment Signal) in timeslot 0.
/FAS: Frame with not correct FAS (Frame Alignment Signal), correct bits C to C and
1 4
correct MFAS in timeslot 0.
BIT 2: Bit 2 of timeslot 0 not containing the frame alignment signal.
FRAME A: Two consecutive frames having FAS in the first timeslot 0, BIT 2 = 1 in the
second timeslot 0 and no contiguous group of seven bits which simulates the
Frame Alignment Signal in timeslots 1 to 31.
FRAME B: Two consecutive frames having FAS in the first timeslot 0, BIT 2 = 1 in the
second timeslot 0, simulated BIT 2 = 1 in the first timeslot 31 and simulated FAS
(no corresponding MFAS) in the second timeslot 31.
FRAME C: Two consecutive frames having /FAS in the first timeslot 0, BIT 2 = 1 in the
second timeslot 0, simulated BIT 2 = 1 in the first timeslot 31 and simulated FAS
(no corresponding MFAS) in the second timeslot 31.
SMF A: Sub-multiframe having correct generation of C to C bits.
1 4
SMF B: Sub-multiframe having incorrect generation of C to C bits.
1 4
MF A: Multiframe having correct FAS, BIT 2 = 1, MFAS and correct C to C bits.
1 4
MF B: Multiframe having correct FAS, BIT 2 = 1, but incorrect MFAS and correct C to
C bits.
# n: # indicates that the sequence defined in the previous line may be repeated
before entering the next sub-sequence. If the parameter "n" is defined this
sequence shall be repeated at least "n" times.
Additional information regarding interface procedure tests for interface I :
B
- when monitoring interface I it has to be recognized that a time delay period independent of actual
B
response times of interface receivers/transmitters may be introduced (e.g. delays attributable to the
implementation of transmission systems between the NT and ET, where a line transmission
termination is present or where coding, decoding and processing occurs etc.). Therefore it is to be
expected that test state transitions may show a delay when monitored.
- separate test response descriptions for interfaces I and I are provided. Indication of state
A B
transition for I is given only where stimulus is repeated (indicated by a #). The expected signal
B
response to a repeated stimulus may however still display a time delay.

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5.2.1 States-matrix at the IUT network side
Test applicable for I interface.
B
Purpose: The tests defined in this subclause intend to check the different stable states at
the IUT side and the possible transitions between them. These tests are
performed by simulating the opposite side (and simulating internal fault in the
IUT for interface I ), monitoring the IUT at the interface and verifying appropriate
B
state transition.
Test configuration:
RX TX
IUT Simulator
TX RX
Figure 5: State-matrix test at the network side
System state: Any state G0 to G5.
It is not possible to distinguish between states G1 and G3 using only layer 1
information at the interface.
IUT suppliers shall provide information how IUT presents status indication (i.e.
detected defect conditions corresponding to MPH error indication or recovery
from defect condition).
Stimulus: For each initial state, each possible new event indicated in table 6 of
ETS 300 011-1 [3] shall be performed.
Stimulus shall be maintained for a time period sufficient to allow the expected
state transition.
S bits shall be set to binary ONE.
a
Monitor: The status indication provided by the IUT and the signal transmitted towards the
interface.
The final state shall be checked 1 second after the stimulus has been
transmitted.
Results: New state, transmitted signal and primitives sent to the higher layers according
to table 6 of ETS 300 011-1 [3].

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ETS 300 011-2: March 1998
5.2.2 States-matrix at the IUT user side
Test applicable for I interface.
A
Purpose: The tests defined in this subclause intend to check the different stable states at
the IUT side and the possible transitions between them. These tests are
performed by simulating the opposite side, monitoring the IUT at the interface
and verifying appropriate state transition.
Test configuration:
RX TX
IUT Simulator
RX
TX
Figure 6: State-matrix test at the user side
System state: Any state F0 to F5.
It is not possible to distinguish between states F1, F2 and F5 or between states
F3 and F4, using only layer 1 information at the interface.
IUT suppliers shall provide information how IUT presents status indication (i.e.
detected defect conditions corresponding to MPH error indication or recovery
from defect condition).
Stimulus: For each initial state, each possible new event indicated.
Stimulus shall be maintained for a time period sufficient to allow the expected
state transition.
S bits in signals having a frame structure shall contain PRBS pattern.
a
The test shall be made with both signals:
- AIS_2 Sequence of 512 bits composed of 510 ONEs and 2 binary ZEROs. This sequence to check
correct AIS recognition according to CCITT Recommendation O.162 [6].
- AIS_3 Sequence of 512 bits composed of 509 ONEs and 3 binary ZEROs. This sequence to check
incorrect AIS recognition according to CCITT Recommendation O.162 [6].
Monitor: The status indication provided by the IUT and the signal transmitted towards the
interface.
The final state shall be checked 1 second after the stimulus has been transmitted.
Results: IUT shall react on receipt of AIS_3 with state F3.
IUT shall react on receipt of AIS_2 with state F4.
New state, transmitted signal and primitives sent to the higher layers according
to table 5 of ETS 300 011-1 [3].

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5.2.3 Interframe (layer 2) time fill
Test applicable for I and I interfaces.
A B
Purpose: To test the pattern on the D Channel when the IUT does not send frames.
Test configuration:
TX
RX
Simulator
IUT
TX RX
Figure 7: Test of interframe time fill
System state for I : State F1.
A
System state for I : State G1.
B
Stimulus: Normal operational frames with contiguous HDLC flags in the D-channel from
the simulator.
Monitor: Pattern on the D Channel (timeslot 16).
Results: Contiguous HDLC flags.
NOTE: An HDLC flag is defined as an octet with a binary pattern 01111110. Therefore
contiguous HDLC flags are defined as the consecutive transmission of 8 bit flags.
There is no requirement to map the HDLC flag into an octet transmitted in timeslot 16
of one frame.
5.2.4 Frame alignment (without the test of CRC procedure)
Test applicable for I and I interfaces.
A B
Purpose: To test that IUT correctly executes the frame alignment procedure.
Test configuration:
RX TX
IUT Simulator
RX
TX
Figure 8: Test of frame alignment procedure

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ETS 300 011-2: March 1998
System state: Various states.
Stimulus: Consecutive correct and bad frame sequences (but including correct multiframe
alignment signal and correct bits C to C ) from the simulator, i.e. bit 2 to 8 of
1 4
timeslot 0 containing the frame alignment signal and bit 2 of timeslot 0 not
containing the frame alignment signal, as given below.
The test signal shall not contain any other contiguous group of seven bits which
simulates the Frame Alignment Signal.
Monitor: Output signal from the IUT.
Table 1: Result of frame alignment test
Stimulus Monitor Comment
BIT 2 = 1, FAS (see note 1) NOF Frame alignment tests.
#
BIT 2 = 1, /FAS NOF
BIT 2 = 1, FAS NOF
#
BIT 2 = 1, /FAS, BIT 2 = 1, /FAS NOF
BIT 2 = 1, FAS NOF
#
BIT 2 = 1, /FAS, BIT 2 = 1, /FAS, BIT 2 = 1, /FAS RAI
BIT 2 = 1, FAS, BIT 2 = 1, FAS NOF
#
BIT 2 = 1, /FAS, BIT 2 = 1, /FAS, BIT 2 = 1, /FAS RAI
BIT 2 = 1, FAS, BIT 2 = 1, /FAS RAI
#
BIT 2 = 1, FAS RAI
BIT 2 = 0, FAS RAI
#
BIT 2 = 1, FAS NOF
#
BIT 2 = 0, FAS, BIT 2 = 1, FAS, BIT 2 = 1, FAS NOF
#
BIT 2 = 0, FAS, BIT 2 = 0, FAS, BIT 2 = 1, FAS NOF
#
BIT 2 = 0, FAS, BIT 2 = 0, FAS, BIT 2 = 0, FAS RAI or NOF
# (see note 2)
BIT 2 = 1, FAS NOF
#
BIT 2 = 1
FRAME B NOF Correct frame alignment.
#
6 X FRAME C RAI -> NOF Loss of frame alignment and
frame alignment with simulated
frame alignment word.
FRAME B NOF
#
RAI and back to NOF will occur (if Multiframe No multiframe alignment on the
4 ms to 8 ms Alignment is operating properly), (see note 3). simulated frame alignment
word.
No further RAI shall occur within a time period of
20 ms.
NOTE 1: This stimulus shall be repeated in order to allow clock synchronization of the IUT, the
time taken to synchronize may be dependant on the implementation.
NOTE 2: RAI or NOF depending on the implementation options described in ETS 300 011-1 [3].
NOTE 3: The vertical bar indicates that the given monitor result shall appear at least once during
application of the stimulus.
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ETS 300 011-2: March 1998
5.2.5 CRC multiframe alignment
Test applicable for I and I interfaces.
A B
Purpose: To test the IUT correctly executes the CRC multiframe alignment.
Test configuration:
TX
RX
Simulator
IUT
TX RX
Figure 9: Test of multiframe frame alignment procedure
System state: Various states.
Stimulus: Consecutive correct and bad CRC multiframe alignment signals from the
simulator, i.e. bit 1 in frames not containing the frame alignment signal as given
below.
Monitor: Output signal from the IUT as given below.
Table 2: Results of multiframe alignment test
Stimulus Monitor Comment
FRAME B (see note)
# NOF
/FAS, BIT 2 = 1, /FAS, BIT 2 = 1, /Fas, BIT 2 = 1
MF A RAI Initial condition.
4 X MF B NOF
MF A RAI No multiframe alignment.
NOF
37 X MF B NOF, transition to RAI and
back to NOF
MF A, MF B, MF A, MF B, MF A, MF B NOF 2 MFAS within 8 ms in
MF B NOF the limit of 100 ms.
# 251 Stable NOF No RAI 500 ms after a
loss of multiframe
alignment.
/FAS, BIT 2 = 1, /FAS, BIT 2 = 1, /FAS, BIT 2 = 1 RAI Initial condition.
MF B NOF Correct basic frame
alignment but not
multiframe.
# 250 No multiframe alignment
MF B RAI within 500 ms.
MF A, 4 X MF B RAI
MF A, 2 X MF B, MF A Undefined condition
MF A, 2 X MF B, 2 X MF A NOF Multiframe alignment
MF B, MF A NOF reached.
#
NOTE: This stimulus shall be repeated in order to allow clock synchronization of the IUT, the time
taken to synchronize may be dependant on the implementation.

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ETS 300 011-2: March 1998
5.2.6 CRC processing
Test applicable for I and I interfaces.
A B
Purpose: To test the correct execution of CRC calculation, comparison with the received
bits C to C and generation of the CRC error report with bit E.
1 4
Test configuration:
RX TX
IUT Simulator
RX
TX
Figure 10: Test of CRC processing
System state for I : State F1.
A
System state for I : State G1.
B
Stimulus: SMF A and SMF B as given below.
Monitor: Output signal, i.e. E bits as given below.
Results: As listed in table 3.
A CRC error report, indicated by an E bit set to ZERO, shall be received within one second after the
generation of a SMF in error. Definition of a SMF in error is given in ETS 300 011-1 [3], subclause 5.5.4.

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ETS 300 011-2: March 1998
Table 3: Results of CRC processing test
Stimulus Monitor
I I option 1 I option 2
A B B
(see note 2) (see note 2)
SMF A No E bit set to zero = =
# Repeat more than 1 second
SMF B One E bit set to zero = =
SMF A No E bit set to zero = =
#
SMF B, SMF B Two contiguous E bits set to ZERO==
SMF A No E bit set to zero
# Repeat more than 1 second
914 X SMF B 914 contiguous E bits set to zero = =
86 X SMF A
914 X SMF B 914 contiguous E bits set to zero = =
SMF A No E bit set to zero = =
# Repeat more than 1 second
915 X SMF B Temporarily RAI (see note 3)
85 X SMF A = =
915 X SMF B (see note 1) (see note 1)
SMF A = =
#
/FAS, BIT 2 = 1, /FAS, BIT 2 = 1, RAI, no E bit set to zero = E bit set to 0
/FAS, BIT 2 = 1 plus RAI
# RAI, no E bit set to zero = E bit set to 0
plus RAI
NOTE 1: Due to possible delay temporary RAI may not be detected at I .
B
NOTE 2: Monitor for I option 1 and option 2 is considered to be the same as for I case (=) unless
B A
otherwise stated.
NOTE 3: The vertical bar indicates that the given monitor result shall appear at least once during
application of the stimulus.
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ETS 300 011-2: March 1998
5.3 Electrical characteristics tests
5.3.1 Specifications at the output ports
5.3.1.1 Bit rate when unsynchronized
Test applicable for I and I interface.
A B
Purpose: To measure the bit rate when the IUT (Implementation Under Test) is not
synchronized.
Test configuration:
TX
RX
Simulator
IUT
RX
TX
Extracted
clock
Frequency
Counter
Figure 11: Measurement of bit rate when IUT is unsynchronized
System state for I : State F3, IUT transmitting RAI.
A
System state for I : State G4, IUT transmitting AIS.
B
Stimulus: No signal from the simulator to the input supplying timing.
I case: Signal having an amplitude 20 dB below nominal level according to the
A
criterion of LOS in subclause 6.1, ETS 300 011-1 [3].
I case: interruption of the signal at any point between NT1 and ET or at the
B
interface I of a PTNX supplying timing.
A
Monitor: Measure bit rate with frequency counter, as extracted by the timing recovery
circuit of the network simulator.
The measurement overall accuracy shall be better than 1 % of the bit rate tolerance.
Results: I interface - For IUT as defined in subclause 5.8 of ETS 300 011-1 [3],
A
foreseen to act as a master, the corresponding bit rate shall be in the range
2 048 kbit/s ± 32 ppm, in all other cases the corresponding bit rate shall be in
the range 2 048 kbit/s ± 50 ppm.
I interface, T reference point - The corresponding bit rate shall be in the range
B
2 048 kbit/s ± 50 ppm.
I interface, S reference point - The corresponding bit rate shall be in the range
B
2 048 kbit/s ± 32 ppm (as defined in subclause 5.8 of ETS 300 011-1 [3]).

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ETS 300 011-2: March 1998
5.3.1.2 Pulse shape and amplitude of a mark (pulse)
Test applicable for I and I interfaces.
A B
Purpose: To check the conformance of the shape of all mark pulses, irrespective of the
polarity, transmitted by IUT.
Test configuration:
RX
IUT
T = Terminating resistor
TX
Digital
T
120 Ohm ± 0,25 %
Oscilloscope
Figure 12: Measurement of pulse shape and amplitude
System state for I : Any state F1 to F5.
A
System state for I : Any state G1 to G5.
B
Stimulus: Relevant signals defined to force IUT to enter the appropriate state.
Monitor: The marks transmitted by IUT.
Results: Both positive and negative pulse shall be within the mask of figure 8 of
ETS 300 011-1 [3], assuming V = 100 %, to be 3 V.
NOTE 1: The measurement overall accuracy should be better than 1 % of the nominal
amplitude of a mark (i.e. 3V).
NOTE 2: All the measurements should be performed using a digital oscilloscope in dc mode.
NOTE 3: Fixed zero level approach should be chosen taking into account the transformerless
implementation of the interface. Such an implementation might not be able to establish
a floating zero level which is dependant on the energy of the positive and the negative
pulses.
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ETS 300 011-2: March 1998
5.3.1.3 Peak voltage of a space (no pulse)
Test applicable for I and I interfaces.
A B
Purpose: To check the absence of any voltage higher than 10 % of the nominal peak
value of a pulse during the transmission of a space (no pulse).
Test configuration:
RX
IUT
T = Terminating resistor
TX
Digital
T
120 Ohm ± 0,25 %
Oscilloscope
Figure 13: Measurement of vol
...