ISO/IEC 11458:1993

lSO/IEC
INTERNATIONAL
11458
STANDARD
First edition
1993-l 2-01
Information technology -
Microprocessor systems -
VlCbus - llnter-crate cable bus
Technologies de /‘information -
Syst&mes a microprocesseurs -
WCbus - Bus a cables inter-chassis
Reference number
ISOA EC 11458: l993( E)

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2
CONTENTS
Page
7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*.*.
FOREWORD
Clause
8
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scope
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Introduction to the ISO/IEC 11458 VICbus standard
9
........................................................................................................................
2.1 Objectives
9
.......................................................................................................
2.2 Standard terminology
9
.......................................................................................................
2.2.1 Rule
9
..................................................................................
2.2.2 Recommendation
10
...........................................................................................
2.2.3 Permission
10
.........................................................................................
2.2.4 Observation
10
..........................................................................................................
2.3 Other terminology
10
............................................................................................................
2.4 Timing diagrams
10
............................................................................................................................
2.5 Tables
10
.......................................................................................................
2.6 Data representation
11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Data transfer bus
11
3.1 Introduction .
11
.............................................................................................................
3.2 DTB cycle types
. 12
3.2.1 Direct cycles .
12
.........................................................................................
3.2.2 Transparent cycles
13
...................................................................................
3.3 Use of the DTB information lines
13
........................................................................................
3.3.1 The address phase
13
..............................................................................................
3.3.2 The data phase
13
...................................................................
Address / data lines AD31-ADO0
3.3.3
13
....................................................................................
Control lines CL3CLO
3.3.4
14
.............................................................................
Identification lines ID4-ID0
3.3.5
14
..................................................................
3.3.6 Device number signals DN4-DNO
14
...............................................................................
3.3.7 Address signals A31-A02
14
.............................................................
3.3.8 Address extension signals AES-AEO
14
...................................................................
Register select signals RS4-RSO
3.3.9
16
...............................................................................
Block transfer signal BLT
3.3.10
16
........................................................................................
3.3.11 Write signal WRITE
......... 16
3.3.12 Byte selection signals LWORD, AOl, ASELO, ASELI, DSELO, DSELI
. 18
....................
Interrupter number signals IN40IN0 .
3.3.13
18
.........................................................................
Slave response signal SERR
3.3.14
18
Data signals 031 -DO0 .
3.3.15
18
..........................................................................................
3.4 Transparent VME-A64 cycle
18
...............................................................
3.5 Data transfer cycle - bus protocols and timing
19
......................................................................................
3.5.1 Block transfer cycles
19
...............................................................................
3.52 Read-modify-write cycles
21
........................................................................................................
3.6 Compelled protocol
21
........................................................................................
The address phase
3.6.1
21
..............................................................................................
3 6.2 The data phase
:
23
...............................................................................................
3.7 Non-compelled protocols
25
.................................................................................
3.7.1 Non-compelled 1 (NCl)
27
.................................................................................
3.7.2 Non-compelled 2 (NC2)
28
..................................................................................
3.8 Slave participation in DTB cycles
Q ISO/lEC 1993
All rights reserved. No part of this publication may be reproduced or utilized in any form or by any means,
electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher.
ISOAEC Copyright Office l Case Postale 131 l CH-1211 Gen8ve 20 l Switzerland
Printed in Switzerland

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3
0 ISO/IEC 11458 : 1993
3.9 DTB timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
" 41
4 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
41 Introduction .
41
412 Lines .
41
4.3 Arbitration protocol .
42
4.4 Arbiter .
4.5 Requester . 43
4.6 Transfer of DTB mastership . 43
.......................................................................................................... 44
4.7 Loss of the arbiter
................................................................................................... 48
4.8 Arbitration timing rules
50
5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51 . Introduction . 50
5.2 . Lines and signals . ” 50
53 . Interrupt request signal selection . 50
54 . Interrupt protocol . 51
. . 52
55 Interrupter
............................................................................................................. 53
56 . Interrupt handler
55
57 . Timing regulations .
I
6 Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1 Introduction
Arbitration lock line ALOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*. 57
6.1 .l
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.2 Device failure line DEVFAIL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.3 Interrupt request select lines INTSELO and INTSELl
58
6.1.4 VlCbus reset line VICRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
6.2 INTSEL generator selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .~.
6.3.1 Global reset - VICRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.2 Selective reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Online and offline states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.4
6.4.1 Regulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
,
Power-up condition . . . . . . . . . . . l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.5 Fautt tolerance
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.6 Cable connection and disconnection in robust systems
66
7 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
7.1 Introduction .
66
7.2 Bus drivers and receivers .
67
7.3 Cables .
68
7.3.1 Cable characteristics .
68
.....................................................................................................................
7.4 Connectors
.................................................................................................................... 70
7.5 Terminators
Arbitration daisy-chain (BG line) termination . 70
7.5.1
Terminator power . 70
7.5.2
............................................................................. 70
7.5.3 Terminators and BGLOOP
72
7.6 Cable continuity for off line devices .
74
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 VlCbus registers
74
....................................................................................................................
8.1 Introduction
74
..........................................................................................................
8.2 Register summary
75
..................................................................................
8.3 Control and status register - CSR
76
.....................................................................................................
8.4 Online register - OLR
77
.................................................................................
8.5 Device operational register - DOR
78
........................................................................................................
8.6 Reset register - RR

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4 0 ISOllEC 11458 : 1993
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-.*. 79
8.7 Transparent register - TR
8.8 Device identification registers - DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Annexes
............................. . .................................................. 82
A Interfacing between VMEbus and VlCbus
.................................................................................................................... 82
A.1 Introduction
A.2 Data transfer bus . 83
A.201 Address and data . 83
A.202 VMEbus AM codes . 83
.................................................................................. 83
A-2.3 VlCbus slave response
........................................................................................... 84
A.204 VMEbus RETRY*
................................................................................... 84
A-2.5 VMEbus 064 transfers
A-2.6 . 84
VMEbus address only cycles
A.207 . 84
Block transfers
........................................................................................................................ 86
A.3 Interrupts
87
A.4 Utilities .
A.401 System failure . 87
A-4.2. System reset . 88
A.5 VMEbus interface functions . 89
................................................................................................................................... 90
Glossary
Summary of lines and signals . 93
Arbitration dead lock . 95
Wired-OR glitch . 96
.............................................................................................. 97
VlCbus electrical cha.racteristics
..................................................................................................... 97
F-1 Electrical termination
................................................................................. 98
F-2 Practical VlCbus implementations

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0 ISOAEC 11458 : 1993
Page
Tables
10
.....................................................................................................
1 VICbus data representation
12
.............................................................................................................................
2 Direct cycles
12
...................................................................................................................
3 Transparent cycles
........................................................ 15
4 Use of the address / data, control and identification lines
17
...........................................................................................................
5 VMEbus byte alignment
17
.................................................................................................................
6 Byte lane alignment
18
................................................................................
7 Transparent VME-A64 signal assignment
28
.........................................................................
8 Summary of slave participation in DTB cycles
36
.......................................................................................................
9 Master - timing regulations
39
.........................................................................................................
10 Slave - timing regulations
48
.......................................................................................................
11 Arbiter - timing regulations
49
.................................................................................................
12 Requester - timing regulations
50
...................................................................................................
13 Interrupt request multiplexing
52
14 IACK byte alignment .
54
Summary of interrupt protocol actions .
15 .
56
...................................................................................................
16 Interrupts - timing regulations
.
60
.....................................................................
17 INTSEL generator selection - timing regulations
............................. 62
18 Summary of the online / offline state of a device following various actions
62
.............................................
Summary of actions permitted in the three online / off line states
19
67
.............................................................................................................................
20 VlCbus lines
69
..........................................................................................
21 VlCbus connector pin assignments
74
....................................................................................................................
22 Register summary
75
...................................................................................................
23 Command and status register
76
24 Online register .
77
......................................................................................................
Device operational register
25
78
...........................................................................................................................
26 Reset register
79
.................................................................................................................
27 Transparent register
80
...................................................................
28 Device identification registers - byte assignments
81
.....................................................................
29 Device identification register 2 - bit assignments
81
.....................................................................
30 Device identification register 3 - bit assignments
89
........................................................................
Al . VMEbus interface control and status functions

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0 ISOIIEC II458 : 1993
6
,
Page
Figures
13
1 DTB cycle .
20
..................................................................................................................
2 Compelled protocol
24
........................................................................................................
3 Non-compelled 1 protocol
26
........................................................................................................
4 Non-compelled 2 protocol
30
.......................................................................................................................
5 Compelled cycle
31
................................................................
6 Compelled cycle last data transfer and end of cycle
32
..............................................................................
7 NC1 address phase and first data transfer
33
...................................................................................
NC1 last data transfer and end of cycle
8
34
..............................................................................
9 NC2 address phase and first data transfer
35
...................................................................................
NC2 last data transfer and end of cycle
10
45
Arbitration-l .
11
46
Arbitration-2 .
12
47
Arbitration-3 .
13
55
.............................................................................................
14 Interrupt request selection timing
59
.....................................................................................................
15 INTSEL generator selection
71
.............................................................................................................
16 Electrical transmission
.
72
.......................................................................................
17 Bus grant daisy-chain and BGLOOP
73
.............................................
Bus Grant termination and continuity of lines in robust systems
18
85
........................................................................................................
Al Inter-crate block transfers
............................... 87
A2 . DEVFAIL / SYSFAlL* interconnection for a VMEbus to VlCbus interface
88
.......................................................................
Reset circuit for a VMEbus to VlCbus interface
A3
95
...............................................................................................
Dl . Arbitration dead-lock resolution
96
.......................................................................................................................
El . Wired-OR glitch
97
..................................................................................................................
Fl . VlCbus termination
98
.................................................................................................
F2 . Device / cable length derating

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0 ISOAEC II458 : 1993
Foreword
IS0 (the International Organization for Standardization) and IEC (the International Electrotechnical
Commission) form the specialised system for world-wide standardisation. National bodies that are
members of IS0 or IEC participate in the development of International Standards through technical
committees established by the respective organisation to deal with particular fields of technical
activity. IS0 and IEC technical committees collaborate in fields of mutual interest. Other international
organisations, governmental and non-governmental, in liaison with IS0 and IEC, also take part in the
work.
In the field of information technology, IS0 and IEC have established a joint technical committee,
ISO/IEC JTCI. Draft International Standards adopted by the joint technical committee are circulated
to national bodies for voting. Publication as an International Standard requires approval by at least
75 % of the national bodies casting a vote.
International Standard lSO/IEC 11458 was prepared by Joint technical committee ISO/IEC JTC 1,
Informafr’on technology, SC 26: Microprocessor Systems.
Annex A forms an integral part of ISO/IEC 11458. Annexes B to F are for information only.

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8 0 ISO/IEC 11458 : 1993
Information technology - Microprocessor systems -
VICbus - Inter-crate cable bus
The widespread use of high-performance, multi-processor systems based on backplane buses such
as the IEC 821 bus (VMEbus), has inevitably led to the requirement to create multi-crate (subrack,
-chassis, etc.) systems. The VlCbu,s inter-crate cable bus is designed to achieve such assemblies in
a standard way.
VICbus, a multiplexed, multi-master, multi-slave cable bus, connects multiple backplane buses or
stand-alone devices, providing transparent, softwareless interconnection for low latency short data
transactions and fast transmission of data blocks over cables of up to 100 m in length. Address and
data signals, each of 32 bits, together with those necessary for the control of the bus protocols,
signal multiplexing, reset and error reporting are transmitted on twisted-wire pairs using differential
line drivers and receivers. Up to 31 devices are permitted on a single VICbus cable.
VICbus data transfer protocols include both a compelled mode with end-to-end acknowledgement as
well as two, high speed, non-compelled modes for high rate data transfers. The compelled protocols
allow both broadcast (master write) and broadcall (master read) data transfers. One of the non-
compelled protocols allows broadcast transfers, whereas neither permit broadcall operation.
Inter-master arbitration uses an efficient, modified single-level, daisy-chained mechanism. The
interrupt mechanism allows 32 interrupt requests, multiplexed on eight physical lines. The
specification includes system failure reporting, reset and live connection and disconnection, as well
as the specification of control and status registers. Particular attention has been paid to redundancy
-
of operation.
Whilst VlCbus has been derived with multi-crate backplane bus systems in mind, this specificat.ion
does not preclude the design of stand-alone VlCbus devices. A normative annex giving rules and
recommendations for a VMEbus to VlCbus interface has been included, and further, similar annexes
for other backplane bus standards wil
...