ISO/IEC 15776:2001

INTERNATIONAL ISO/IEC
STANDARD
First edition
2001-12
VME64bus – Specification
Reference number
INTERNATIONAL ISO/IEC
STANDARD
First edition
2001-12
VME64bus – Specification
 ISO/IEC 2001
All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by any
means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher.
ISO/IEC Copyright Office Case postale 56 CH-1211 Genève 20 Switzerland
• • •
PRICE CODE
XF
For price, see current catalogue

– 2 – 15776 © ISO/IEC:2001(E)
CONTENTS
FOREWORD .8
INTRODUCTION.9
1 General.13
1.1 Scope and object .13
1.2 Normative references.13
1.3 VMEbus interface system elements.14
1.4 VMEbus specification diagrams.20
1.5 Specification terminology .22
1.6 Protocol specification .24
1.7 System examples and explanations.25
2 Data transfer bus.25
2.1 Introduction.25
2.2 Data-transfer-bus lines.27
2.3 DTB modules – Basic description .38
2.4 Typical operation.64
2.5 Data-transfer-bus acquisition .73
2.6 DTB timing rules and observations .75
3 Data transfer bus arbitration.120
3.1 Bus arbitration philosophy.120
3.2 Arbitration bus lines.122
3.3 Functional modules .124
3.4 Typical operation.132
3.5 Race conditions between master requests and arbiter grants.141
4 Priority interrupt bus.141
4.1 Introduction.141
4.2 Priority interrupt bus lines.144
4.3 Priority interrupt bus modules – Basic description .146
4.4 Typical operation.159
4.5 Race conditions.165
4.6 Priority interrupt bus timing rules and observations .166
5 Utility bus .183
5.1 Introduction.183
5.2 Utility bus signal lines. .183
5.3 Utility bus modules .183
5.4 System initialization and diagnostics.186
5.5 Power and ground pins .190
5.6 Reserved line .191
5.7 Auto slot ID.191
5.8 Auto system controller.198
6 Electrical specifications .199
6.1 Introduction.199
6.2 Power distribution.200
6.3 Electrical signal characteristics .201
6.4 Bus driving and receiving requirements .202

15776 © ISO/IEC:2001(E) – 3 –
6.5 Backplane signal line interconnections .206
6.6 User defined signals.210
6.7 Signal line drivers and terminations .210
7 Mechanical specifications.212
7.1 Introduction.212
7.2 VMEbus boards.213
7.3 Front panels .217
7.4 Backplanes.220
7.5 Assembly of VMEbus subracks.222
7.6 Conduction cooled VMEbus systems.223
7.7 VMEbus backplane connectors and VMEbus board connectors .223
Annex A (normative) Glossary of VMEbus terms .245
Annex B (normative) VMEbus Connector/Pin description .251
Annex C (normative) Manufacturer’s board identification.255
Rule index.257
Figure 1 – System elements.15
Figure 2 – Functional modules and buses.21
Figure 3 – Signal timing notation .25
Figure 4 – Data transfer bus functional block diagram.28
Figure 5 – Block diagram – Master.39
Figure 6 – Block diagram – Slave.41
Figure 7 – Block diagram – Bus timer .43
Figure 8 – Block diagram – Location monitor.44
Figure 9 – Four ways in which 32 bits of data might be stored in memory.53
Figure 10 – Four ways in which 16 bits of data might be stored in memory.54
Figure 11 – Block diagram – Configuration ROM / Control & Status registers.59
Figure 12 – Example of a non-multiplexed address, single-byte read cycle .66
Figure 13 – Example of multiplexed address double-byte write cycle.67
Figure 14 – Example of non-multiplexed address quad-byte write cycle.69
Figure 15 – Example of an eight-byte block read cycle.70
Figure 16 – Data transfer bus master exchange sequence .74
Figure 17 – Address broadcast timing – All cycles.94
Figure 18 – A16, A24, A32 master, responding slave, and location monitor.95
Figure 19 – Master, slave, and location monitor – A16, A24 and A32 address broadcast timing .96
Figure 20 – Master, slave, and location monitor A16, A24, and A32 address broadcast timing .97
Figure 21 – Master, slave and location monitor – A64, A40, and ADOH address
broadcast timing .98
Figure 22 – Master, slave, and location monitor data transfer timing.99
Figure 23 – Master, slave, and location monitor data transfer timing.101

– 4 – 15776 © ISO/IEC:2001(E)
Figure 24 – Master, slave and location monitor data transfer timing A40 multiplexed
quad byte read, A40BLT multiplexed quad byte block read, MBLT eight byte block read .103
Figure 25 – Master, slave and location monitor data transfer timing.105
Figure 26 – Master, slave and location monitor data transfer timing.107
Figure 27 – Master, slave and location monitor data transfer timing A40 multiplexed
quad byte write, A40BLT multiplexed quad byte block write, MBLT eight byte block write .109
Figure 28 – Master, slave and location monitor data transfer timing single-byte RMW cycles .111
Figure 29 – Master, slave and location monitor data transfer timing double-byte
RMW cycles, quad-byte RMW cycles.112
Figure 30 – Address strobe inter-cycle timing .113
Figure 31 – Data strobe inter-cycle timing.113
Figure 32 – Data strobe inter-cycle timing.114
Figure 33 – Master, slave and bus timer data transfer timing timed-out cycle .114
Figure 34 – Master DTB control transfer timing.115
Figure 35 – Master and slave data transfer timing master responding to RETRY* line .116
Figure 36 – Master and slave data transfer timing master ignoring RETRY* line .117
Figure 37 – A40, MD32 read-modify-write.118
Figure 38 – Rescinding DTACK timing.119
Figure 39 – Arbitration functional block diagram .121
Figure 40 – Illustration of the daisy chain bus grant lines.123
Figure 41 – Block diagram – Arbiter .127
Figure 42 – Block diagram – Requester.130
Figure 43 – Arbitration flow diagram two requesters, two request levels .134
Figure 44 – Arbitration sequence diagram two requesters, two request levels .136
Figure 45 – Arbitration flow diagram two requesters, same request level.137
Figure 46 – Arbitration sequence diagram two requesters, same request level.140
Figure 47 – Priority interrupt bus functional diagram .142
Figure 48 – Interrupt subsystem structure – Single handler system .143
Figure 49 – Interrupt subsystem structure – Distributed system .144
Figure 50 – IACKIN*/IACKOUT* DAISY-CHAIN.146
Figure 51 – Block diagram – Interrupt handler .148
Figure 52 – Block diagram – Interrupter.151
Figure 53 – Block diagram – IACK daisy-chain driver .152
Figure 54 – Release of interrupt request lines by ROAK and RORA interrupters .156
Figure 55 – IACK daisy-chain driver and interrupter on the same board.158
Figure 56 – Two interrupters on the same board .159
Figure 57 – The three phases of an interrupt sequence.160
Figure 58 – Two interrupt handlers, each monitoring one interrupt request line .161
Figure 59 – Two interrupt handlers, each monitoring several interrupt request lines.162

15776 © ISO/IEC:2001(E) – 5 –
Figure 60 – Typical single handler interrupt system operation flow diagram.164
Figure 61 – Typical distributed interrupt system with two interrupt handlers, flow diagram.165
Figure 62 – Interrupt handler and interrupter – Interrupter selection timing single-byte,
double-byte and quad-byte interrupt acknowledge cycles.178
Figure 63 – IACK daisy-chain driver – Interrupter selection timing single-byte, double-byte,
and quad-byte interrupt acknowledge cycles.178
Figure 64 – Participating interrupter – Interrupter selection timing single-byte, double-byte,
and quad-byte interrupt acknowledge cycles.179
Figure 65 – Responding interrupter – Interrupter selection timing single-byte, double-byte,
and quad-byte interrupt acknowledge cycles.179
Figure 66 – Interrupt handler – Status/ID transfer timing single-byte interrupt acknowledge
cycle.180
Figure 67 – Interrupt handler – Status/ID transfer timing double-byte and quad-byte
interrupt acknowledge cycles.180
Figure 68 – Responding interrupter – Status/ID transfer timing single-byte interrupt
acknowledge cycle.181
Figure 69 – Responding interrupter – Status/ID transfer timing double-byte interrupt
acknowledge cycle quad-byte interrupt acknowledge cycle .182
Figure 70 – IACK daisy-chain driver, responding interrupter and participating interrupter
IACK daisy-chain inter-cycle timing .182
Figure 71 – Utility bus block diagram.184
Figure 72 – System clock driver timing.185
Figure 73 – Block diagram of power monitor module.186
Figure 74 – Power monitor power failure timing .187
Figure 75 – Power monitor system restart timing.187
Figure 76 – SYSRESET* and SYSFAIL* timing diagram .190
Figure 77 – Current rating for power pins.191
Figure 78 – CR/CSR auto ID slave initialization algorithm .195
Figure 79 – First slot detector (FSD) .198
Figure 80 – VMEbus signal levels .201
Figure 81 – Standard bus termination .208
Figure 82 – Subrack with mixed board sizes.226
Figure 83 – Single height board – Basic dimensions.227
Figure 84 – Double height board – Basic dimensions .228
Figure 85 – Connector positions on single and double height boards.229
Figure 86 – Cross-sectional view of board, connector, backplane, and front panel.230
Figure 87 – Optional enhanced DIN connector .231
Figure 88 – Component height, lead length and board warpage.232
Figure 89 – Single height, single width front panel .233
Figure 90 – Double height, single width front panel.234
Figure 91 – Front panel mounting brackets and dimension of single height boards. .235
Figure 92 – Front panel mounting brackets and dimension of double height boards.236
Figure 93 – Single height filler panel .237

– 6 – 15776 © ISO/IEC:2001(E)
Figure 94 – Double height filler panel .238
Figure 95 – Backplane detailed dimensions of a J1 and a J2 backplane.239
Figure 96 – Detailed dimensions of a J1/J2 backplane.240
Figure 97 – "Off-board type" backplane terminations (viewed from top of backplane) .241
Figure 98 – "On-board type" backplane terminations (viewed from top of backplane).242
Figure 99 – 21 slot subrack .243
Figure 100 – Board guide detail.244
Table 1 – The eight categories of byte locations .29
Table 2 – Address alignment on bus .29
Table 3 – Signal levels during data transfers used to select which byte location(s) are
accessed during a data transfer .31
Table 4 – Address modifier codes.33
Table 5 – Use of data lines to move data during nonmultiplexed data transfers.35
Table 6 – Use of the address and data lines for multiplexed data cycles.36
Table 7 – RULEs and PERMISSIONs specifying the use of the dotted lines by the
various types of masters.40
Table 8 – Slaves – RULEs and PERMISSIONs specifying the use of the dotted lines
by the various type of slaves.42
Table 9 – Use of the BTO( ) mnemonic specifying the time-out period of bus timers.43
Table 10 – Location monitors – RULEs and PERMISSIONs specifying the use of the
dotted lines by the various types of location monitors .45
Table 11 – Mnemonics specifying addressing capabilities.46
Table 12 – Mnemonics specifying basic data transfer capabilities.48
Table 13 – Mnemonics specifying block transfer capabilities.51
Table 14 – The mnemonic that specifies read-modify-write capabilities .52
Table 15 – Transferring 32 bits of data using multiple-byte transfer cycles .54
Table 16 – Transferring 16 bits of data using multiple-byte transfer cycles .55
Table 17 – Mnemonic that specifies unaligned transfer capability .55
Table 18 – Mnemonics specifying address only capability.56
Table 19 – Configuration ROM/control & status registers: RULEs and PERMISSIONs or
monitoring the dashed lines.60
Table 20 – Control and status register base definition .60
Table 21 – Configuration ROM definition.61
Table 22 – Timing diagrams defining master, slave, and location monitor operation (see Table
27 for timing values) .76
Table 23 – Definitions of mnemonics used in Tables 24, 25 and 26.78
Table 24 – Use of the address and data lines to select a byte group.78
Table 25 – Use of DS1*, DS0*, A1, A2, and LWORD* during the address phase of the various
cycles.79
Table 26 – Use of the data lines to transfer data.80

15776 © ISO/IEC:2001(E) – 7 –
Table 27 – Master, slave, and location monitor timing parameters.83
Table 28 – Bus-timer timing parameters (see also Table 32) .84
Table 29 – Master, timing RULEs and OBSERVATIONs.84
Table 30 – Slave, timing RULEs and OBSERVATIONs.89
Table 31 – Location monitor, timing OBSERVATIONs.93
Table 32 – BUS TIMER, timing RULEs .94
Table 33 – RULEs and PERMISSIONs specifying the use of the dotted lines by the various
types of arbiters .128
Table 34 – RULEs and PERMISSIONs specifying the use of the dotted lines by the various
types of requesters .131
Table 35 – RULEs and PERMISSIONs specifying the use of the dotted lines in Figure 51 by the
various types of interrupt handlers.149
Table 36 – RULEs and PERMISSIONs specifying the use of the dotted lines in Figure 52 by the
various types of interrupters .151
Table 37 – Use of the IH( ) mnemonic to specify interrupt request handling capabilities.153
Table 38 – Use of the I( ) mnemonic to specify interrupt request generation capabilities.153
Table 39 – Mnemonics specifying status/ID transfer capabilities.153
Table 40 – Mnemonics specifying interrupt request release capabilities .155
Table 41 – 3-bit interrupt acknowledge code.164
Table 42 – Timing diagrams defining interrupt handler and interrupter operation.167
Table 43 – Timing diagrams defining IACK daisy-chain driver operation.168
Table 44 – Timing diagrams defining participating interrupter operation.168
Table 45 – Timing diagrams that define responding interrupter operation.168
Table 46 – Definitions of mnemonics used in tables 47, 48 and 49 .169
Table 47 – Use of addressing lines during interrupt acknowledge cycles .169
Table 48 – Use of the DS1*, DS0*, LWORD* and WRITE* lines during iterrupt acknowledge
cycles.170
Table 49 – Use of the data bus lines to transfer the Status/ID.170
Table 50 – Interrupt handler, interrupter and IACK daisy-chain driver timing parameters .171
Table 51 – Interrupt handler, timing RULEs and OBSERVATIONs .172
Table 52 – Interrupter, timing RULEs and OBSERVATIONs .174
Table 53 – IACK daisy-chain driver, timing RULEs and OBSERVATIONs .177
Table 54 – Module drive during power-up and power-down sequences .189
Table 55 – Bus voltage specification .200
Table 56 – Bus driving and receiving requirements .202
Table 57 – Bus driver summary.211
Table 58 – J1/P1 pin assignments .224
Table 59 – J2/P2 pin assignments .225

– 8 – 15776 © ISO/IEC:2001(E)
VME64bus – SPECIFICATION
FOREWORD
1) ISO (the International Organization for Standardization) and IEC (the International Electrotechnical Commission) form the
specialized system for worldwide standardization. National bodies that are members of ISO or IEC participate in the
development of International Standards through technical committees established by the respective organization to deal
with particular fields of technical activity. ISO and IEC technical committees collaborate in fields of mutual interest. Other
international organizations, governmental and non-governmental, in liaison with ISO and IEC, also take part in the work.
2) In the field of information technology, ISO and IEC have established a joint technical committee, ISO/IEC JTC1. Draft
International Standards adopted by the joint technical committee are circulated to national bodies for voting. Publication as
an International Standard requires approval by at least 75 % of the national bodies casting a vote.
3) Attention is drawn to the possibility that some of the elements of this International Standard may be the subject of patent
rights. ISO and IEC shall not be held responsible for identifying any or all such patent rights.
International Standard ISO/IEC 15776 was prepared by subcommittee 26: Microprocessor systems, of
ISO/IEC joint technical committee 1: Information technology.
International Standards are drafted in accordance with ISO/IEC Directives, Part 3.
Annexes A, B and C form an integral part of this International Standard.

15776 © ISO/IEC:2001(E) – 9 –
INTRODUCTION
The architectural concepts of VMEbus are based on the VERSAbus developed by Motorola in the late
1970s. Motorola's European Microsystems group in Munich, West Germany proposed the
development of a VERSAbus-like product line of computers and controllers based on the Eurocard
mechanical standard. To demonstrate the concept, Max Loesel and Sven Rau developed three
prototype boards: (1) a 68000 CPU card, (2) a dynamic memory card, and (3) a static memory card.
They named the new bus VERSAbus-E, which was later renamed "VME" by Lyman Hevle, then VP of
the Motorola Microsystems Operation (and later the founder of VITA). VME is the acronym for VERSA-
module Europe. Motorola, Mostek, and Signetics agreed to jointly develop and support the new bus
architecture in early 1981.
John Black of Motorola, Craig McKenna of Mostek, and Cecil Kaplinsky of Signetics developed the first
draft of the VMEbus specification. In October of 1981, at the Systems 81 trade show in Munich, West
Germany, Motorola, Mostek, and Signetics announced their joint support for VMEbus, and placed
Revision A of the specification in the public domain.
In August of 1982, Revision B of the VMEbus specification was published by the newly formed
VMEbus Manufacturers Group (now VITA). This new revision refined the electrical specifications for
the signal line drivers and receivers, and also brought the mechanical specifications more in line with
the developing IEC 60297 standard, the formal specifications for Eurocard mechanical formats.
In the latter part of 1982, the French delegation of the International Electrotechnical Commission (IEC)
proposed Revision B of the VMEbus specification as an international standard. The IEC SC47B
subcommittee nominated Mira Pauker of Philips, France, as the chairperson of an editorial committee,
formally starting international standardization of the VMEbus.
In March of 1983, the IEEE Microprocessor Standards Committee (MSC) requested authorization to
establish a working group to standardize the VMEbus in the US. This request was approved by the
IEEE Standards Board, and the P1014 Working Group was established. Wayne Fischer was appointed
first chairman of the working group. John Black served as chairman of the P1014 Technical
Subcommittee.
The IEC, IEEE, and VMEbus Manufacturers Group (now VITA) distributed copies of Revision B for
comment, and received requests for changes to the document as a result. These comments made it
clear that it was time to go forward past revision B. In December of 1983, a meeting was held that
included John Black, Mira Pauker, Wayne Fischer, and Craig McKenna. It was agreed that a revision C
should be created, and that it should take into consideration all comments received by the three
organizations. John Black and Shlomo Pri-Tal of Motorola incorporated the changes from all sources
into a common document. The VMEbus Manufacturers Group (now VITA) labeled the document
Revision C.1 and placed it in the public domain. The IEEE labeled it P1014 Draft 1.2, and the IEC
labeled it IEC 60821 Bus. Subsequent ballots in the IEEE P1014 group and in the MSC resulted in
more comments, and required that the IEEE P1014 draft be updated. This work resulted in the
ANSI/IEEE 1014-1987 specification.
In 1989, John Peters of Performance Technologies, Inc. (Rochester, NY) developed the initial concept
of VME64: multiplexing address and data lines (A64/D64) on the VMEbus. This concept was shown for
the first time in 1989 and placed in the VITA Technical Committee in 1990 as a performance
enhancement to the VMEbus specification. In 1991, the PAR (Project Authorization Request) for
P1014R (revisions to the VMEbus specification) was granted by the IEEE. Ray Alderman, Technical
Director of VITA, co-chaired the activity with Kim Clohessy of DY 4 Systems (Nepean, Ontario,
Canada).
– 10 – 15776 © ISO/IEC:2001(E)
At the end of 1992, the additional enhancements to VMEbus (A40/D32, Locked Cycles, Rescinding
DTACK*, Autoslot-ID, Auto System Controller, and enhanced DIN connector mechanicals) required
more work to complete this document. In 1992, the VITA Technical Committee suspended work with
the IEEE and sought accreditation as a standards developer organization (SDO) with the American
National Standards Institute. The original IEEE Par P1014R was subsequently withdrawn by the IEEE.
The VITA Technical Committee returned to using the public domain VMEbus C.1 specification as its
base level document to which it added new enhancements. This enhancement work was undertaken
entirely by the VITA Technical Committee resulting in this document. The tremendous undertaking of
the document editing was accomplished by Kim Clohessy of DY 4 Systems, the technical co-chair of
the activity with great help from Frank Hom who created the mechanical drawings, and with
exceptional contributions by each chapter editor.
Additional enhancements proposed to the VME64 Subcommittee have been placed in another VITA
subcommittee: the VME64 Extensions Document. Two other activities began in late 1992: (1) BLLI
(VMEbus Board-level Live Insertion Specifications), and (2) VSLI (VMEbus System-level Live Insertion
with Fault Tolerance).
New activities begun in 1993 using the base-VME architecture involve the implementation of high-
speed serial and parallel sub-buses for use as I/O interconnections and data mover subsystems.
These architectures can be used as message switches, routers, and small multiprocessor parallel
architectures.
VITA’s application for recognition as an accredited standards developer organization of ANSI
(American National Standards Institute) was granted in June 1993. Numerous other documents,
including mezzanine, P2, and serial bus standards, have been placed with VITA as the Public Domain
Administrator of these technologies.
VMEbus Specification Genealogy
VMEbus Revision B and C.1 (Public Domain)
IEEE 1014-1987 Versatile Backplane Bus VMEbus
VITA 1-1994 VME64 Specification
IEEE 1096-1988 VSBbus Specification (IEEE)
IEC 60821:1991 VMEbus – Microprocessor system bus for 1 byte to 4 byte data
IEEE 1101.1 IEEE Standard for Mechanical Core Specifications for Microcomputers Using
IEC 60603-2 Connectors
IEEE 1101.2 IEEE Standard for Mechanical Core Specification for Conduction-Cooled
Eurocards
15776 © ISO/IEC:2001(E) – 11 –
This standard was constructed through the many hours of hard work by the members of the VME64
Subcommittee (of the VITA Technical Committee) and the commitment of their companies to this
standard.
NAME COMPANY
Ray Alderman PEP Modular Computers
Michael Humphrey VITA
John Rynearson VITA
Martin Blake BICC-VERO UK
Kim Clohessy DY 4 Systems, Inc.
Jing Kwok DY 4 Systems, Inc.
Clarence Peckham Heurikon Corporation
Dennis Terry Heurikon Corporation
Wayne Fischer Force Computers Inc.
Jack Regula Consultant
Tad Kubic Dawn VME Products, Inc.
Will Hamsher AMP, Inc.
Doug Reubendall AMP, Inc.
William Mahusen Performance Technologies, Inc.
Thanos Mentzelopoulos Ironics, Inc.
Joel Silverman Radstone Technology Corp.
Colin Davies Radstone Technology UK
Frank Hom Electronic Solutions
Keith Burgess Mizar
John Black Micrology PBT
Greg Hill Hewlett-Packard Co.
Sam Babb Hewlett Packard Co.
Ben LaPointe Motorola GEG
Chau Pham Motorola MCG
Mac Rush Motorola MCG
Mike Hasenfratz Micro Memory, Inc.
Richard DeBock Matrix Corp.
Richard O'Connor Newbridge Microsystems
Michael Bryant PEP Modular Computers
Dr. Chris Eck CERN-Geneva
Mike Thompson Schroff, Inc.
Eike Waltz Schroff, Inc.
Tom Baillio Mercury Computer Systems, Inc.
Steve Corbesero Mupac Corp.
Dave Horton Cypress Semiconductor
Mike Maas Cypress Semiconductor
Mike Munroe Hybricon Corp.
– 12 – 15776 © ISO/IEC:2001(E)
The following are acknowledged for their extra contributions as chapter editors.
Kim Clohessy DY-4 Systems Inc.
Wayne Fischer Force Computers, Inc.
Chau Pham Motorola MCG
Frank Hom Electronic Solutions
Richard DeBock Matrix Corp.
Jing Kwok DY 4 Systems, Inc.
Mike Hasenfratz Micro Memory, Inc.
CANVASS BALLOT
Consensus for this standard was achieved by use of the Canvass Method.
The following organizations, recognized as having an interest in the standardization of VME64,
participated in the Canvass Ballot process. Inclusion in this list does not necessarily imply that the
organization concurred with the submittal of the proposed standard to ANSI.
767 AWACS Micrology
Adept Technology MITRE Corporation
AMP Motorola Computer Group
AT&T Bell Laboratories Mupac Corporation
Berg Electronics Newbridge Microsystems
Bit 3 Computer Object Technology Inc.
CERN PEP Modular Computers
CSPI Philips Ind. Automation
Cypress Semiconductor Picosoft
Dawn VME Products Radstone Technology
Dialogic Corporation Schroff
Digital Equipment Corp. Technology Consulting
DY 4 Systems Texas Instruments
Electronic Solutions VERO Electronics
Force Computers VITA
Harting Elektronik VME MEMBER
Heurikon Corporation Winchester Electronics
Hewlett-Packard
Hughes Aircraft Company
Hybricon Corporation
IBM
IXTHOS
Loral Western Devel. Lab
Los Alamos Nat'l Lab
Matrix Corporation
Micro Memory
15776 © ISO/IEC:2001(E) – 13 –
VME64bus – SPECIFICATION
1 General
1.1 Scope and object
The VMEbus specification defines an interfacing system used to interconnect microprocessors, data
storage, and peripheral control devices in a closely coupled hardware configuration. The system has
been conceived with the following objectives:
a) to allow communication between devices on the VMEbus without disturbing the internal activities of
other devices interfaced to the VMEbus;
b) to specify the electrical and mechanical system characteristics required to design devices that will
reliably and unambiguously communicate with other devices interfaced to the VMEbus;
c) to specify protocols that precisely define the interaction between the VMEbus and devices
interfaced to it;
d) to provide terminology and definitions that describe the system protocol;
e) to allow a broad range of design latitude so that the designer can optimize cost and/or performance
without affecting system compatibility;
f) to provide a system where performance is primarily device limited, rather than system interface
limited.
1.2 Normative references
The following referenced documents are indispensable for the application of this document. For dated
references, only the edition cited applies. For undated references, the latest edition of the referenced
document (including any amendments) applies.
IEC 60297-1:1986, Dimensions of mechanical structures of the 482,6 mm (19 in) series – Part 1:
Panels and racks
IEC 60297-2:1982, Dimensions of mechanical structures of the 482,6 mm (19 in) series – Part 2:
Cabinets and pitches of rack structures
IEC 60297-3:1984, Dimensions of mechanical structures of the 482,6 mm (19 in) series – Part 3:
Subracks and associated plug-in units
IEC 60297-4:1995, Mechanical structures for electronic equipment – Dimensions of mechanical
structures of the 482,6 mm (19 in) series – Part 4: Subracks and associated plug-in units – Additional
dimensions
IEC 60603-2:1995, Connectors for frequencies below 3 MHz for use with printed boards – Part 2:
Detail specification for two-part connectors with assessed quality, for printed boards, for basic grid of
2.54 mm (0
...